Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	90406517	394497	0	0
check_regwen_rd_A	90406517	2281	0	0
check_timeout_rd_A	90406517	1318	0	0
check_trigger_regwen_rd_A	90406517	2235	0	0
consistency_check_period_rd_A	90406517	2267	0	0
creator_sw_cfg_read_lock_rd_A	90406517	1321	0	0
direct_access_address_rd_A	90406517	483	0	0
direct_access_wdata_0_rd_A	90406517	94	0	0
direct_access_wdata_1_rd_A	90406517	73	0	0
integrity_check_period_rd_A	90406517	2238	0	0
intr_enable_rd_A	90406517	2883	0	0
owner_sw_cfg_read_lock_rd_A	90406517	1464	0	0
rot_creator_auth_codesign_read_lock_rd_A	90406517	1390	0	0
rot_creator_auth_state_read_lock_rd_A	90406517	1397	0	0
vendor_test_read_lock_rd_A	90406517	1362	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90406517	394497	0	0
T14	180151	3681	0	0
T15	151433	2293	0	0
T16	0	6493	0	0
T21	0	9501	0	0
T88	0	11991	0	0
T89	0	9971	0	0
T183	12011	0	0	0
T271	0	4642	0	0
T282	0	1949	0	0
T292	0	5062	0	0
T313	0	3555	0	0
T314	34434	0	0	0
T315	9018	0	0	0
T316	14703	0	0	0
T317	42985	0	0	0
T318	51649	0	0	0
T319	65818	0	0	0
T320	100860	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90406517	2281	0	0
T15	151433	31	0	0
T88	0	22	0	0
T104	0	41	0	0
T183	12011	0	0	0
T271	0	40	0	0
T283	0	38	0	0
T292	0	26	0	0
T313	0	20	0	0
T317	42985	0	0	0
T318	51649	0	0	0
T319	65818	0	0	0
T320	100860	0	0	0
T352	0	31	0	0
T353	0	7	0	0
T354	0	6	0	0
T355	44957	0	0	0
T356	23166	0	0	0
T357	17250	0	0	0
T358	4603	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90406517	1318	0	0
T15	151433	24	0	0
T88	0	17	0	0
T104	0	51	0	0
T183	12011	0	0	0
T271	0	39	0	0
T283	0	38	0	0
T292	0	31	0	0
T313	0	32	0	0
T317	42985	0	0	0
T318	51649	0	0	0
T319	65818	0	0	0
T320	100860	0	0	0
T352	0	17	0	0
T353	0	12	0	0
T354	0	6	0	0
T355	44957	0	0	0
T356	23166	0	0	0
T357	17250	0	0	0
T358	4603	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90406517	2235	0	0
T15	151433	25	0	0
T88	0	19	0	0
T104	0	45	0	0
T183	12011	0	0	0
T271	0	58	0	0
T283	0	39	0	0
T292	0	17	0	0
T313	0	29	0	0
T317	42985	0	0	0
T318	51649	0	0	0
T319	65818	0	0	0
T320	100860	0	0	0
T352	0	12	0	0
T353	0	10	0	0
T354	0	15	0	0
T355	44957	0	0	0
T356	23166	0	0	0
T357	17250	0	0	0
T358	4603	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90406517	2267	0	0
T15	151433	18	0	0
T88	0	33	0	0
T104	0	79	0	0
T183	12011	0	0	0
T271	0	20	0	0
T283	0	40	0	0
T292	0	20	0	0
T313	0	28	0	0
T317	42985	0	0	0
T318	51649	0	0	0
T319	65818	0	0	0
T320	100860	0	0	0
T352	0	20	0	0
T353	0	23	0	0
T354	0	8	0	0
T355	44957	0	0	0
T356	23166	0	0	0
T357	17250	0	0	0
T358	4603	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90406517	1321	0	0
T15	151433	14	0	0
T88	0	20	0	0
T104	0	33	0	0
T183	12011	0	0	0
T271	0	33	0	0
T283	0	44	0	0
T292	0	27	0	0
T313	0	17	0	0
T317	42985	0	0	0
T318	51649	0	0	0
T319	65818	0	0	0
T320	100860	0	0	0
T352	0	34	0	0
T353	0	16	0	0
T354	0	15	0	0
T355	44957	0	0	0
T356	23166	0	0	0
T357	17250	0	0	0
T358	4603	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90406517	483	0	0
T15	151433	11	0	0
T88	0	18	0	0
T104	0	68	0	0
T183	12011	0	0	0
T271	0	38	0	0
T283	0	45	0	0
T292	0	30	0	0
T313	0	32	0	0
T317	42985	0	0	0
T318	51649	0	0	0
T319	65818	0	0	0
T320	100860	0	0	0
T352	0	25	0	0
T353	0	5	0	0
T354	0	4	0	0
T355	44957	0	0	0
T356	23166	0	0	0
T357	17250	0	0	0
T358	4603	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90406517	94	0	0
T15	151433	2	0	0
T88	0	8	0	0
T104	0	6	0	0
T183	12011	0	0	0
T283	0	10	0	0
T292	0	3	0	0
T317	42985	0	0	0
T318	51649	0	0	0
T319	65818	0	0	0
T320	100860	0	0	0
T355	44957	0	0	0
T356	23166	0	0	0
T357	17250	0	0	0
T358	4603	0	0	0
T359	0	20	0	0
T360	0	28	0	0
T361	0	17	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90406517	73	0	0
T25	12985	0	0	0
T104	0	16	0	0
T161	9665	0	0	0
T271	0	15	0	0
T287	250338	0	0	0
T289	0	3	0	0
T292	288815	2	0	0
T313	0	3	0	0
T359	0	4	0	0
T360	0	5	0	0
T361	0	14	0	0
T362	0	11	0	0
T363	58613	0	0	0
T364	60385	0	0	0
T365	24519	0	0	0
T366	127529	0	0	0
T367	59099	0	0	0
T368	13205	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90406517	2238	0	0
T15	151433	39	0	0
T88	0	23	0	0
T104	0	31	0	0
T183	12011	0	0	0
T271	0	47	0	0
T283	0	41	0	0
T292	0	35	0	0
T313	0	13	0	0
T317	42985	0	0	0
T318	51649	0	0	0
T319	65818	0	0	0
T320	100860	0	0	0
T352	0	22	0	0
T353	0	6	0	0
T354	0	18	0	0
T355	44957	0	0	0
T356	23166	0	0	0
T357	17250	0	0	0
T358	4603	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90406517	2883	0	0
T15	151433	26	0	0
T88	0	27	0	0
T154	0	44	0	0
T183	12011	0	0	0
T271	0	22	0	0
T292	0	12	0	0
T313	0	47	0	0
T317	42985	0	0	0
T318	51649	0	0	0
T319	65818	0	0	0
T320	100860	0	0	0
T352	0	32	0	0
T355	44957	0	0	0
T356	23166	0	0	0
T357	17250	0	0	0
T358	4603	0	0	0
T369	0	46	0	0
T370	0	38	0	0
T371	0	5	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90406517	1464	0	0
T15	151433	27	0	0
T88	0	16	0	0
T104	0	25	0	0
T183	12011	0	0	0
T271	0	36	0	0
T283	0	53	0	0
T292	0	19	0	0
T313	0	13	0	0
T317	42985	0	0	0
T318	51649	0	0	0
T319	65818	0	0	0
T320	100860	0	0	0
T352	0	32	0	0
T353	0	2	0	0
T354	0	14	0	0
T355	44957	0	0	0
T356	23166	0	0	0
T357	17250	0	0	0
T358	4603	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90406517	1390	0	0
T15	151433	21	0	0
T88	0	41	0	0
T104	0	48	0	0
T183	12011	0	0	0
T271	0	19	0	0
T283	0	34	0	0
T292	0	33	0	0
T313	0	27	0	0
T317	42985	0	0	0
T318	51649	0	0	0
T319	65818	0	0	0
T320	100860	0	0	0
T352	0	12	0	0
T353	0	11	0	0
T354	0	9	0	0
T355	44957	0	0	0
T356	23166	0	0	0
T357	17250	0	0	0
T358	4603	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90406517	1397	0	0
T15	151433	16	0	0
T88	0	20	0	0
T104	0	57	0	0
T183	12011	0	0	0
T271	0	40	0	0
T283	0	32	0	0
T292	0	35	0	0
T313	0	24	0	0
T317	42985	0	0	0
T318	51649	0	0	0
T319	65818	0	0	0
T320	100860	0	0	0
T352	0	17	0	0
T353	0	15	0	0
T354	0	5	0	0
T355	44957	0	0	0
T356	23166	0	0	0
T357	17250	0	0	0
T358	4603	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90406517	1362	0	0
T15	151433	17	0	0
T88	0	29	0	0
T104	0	50	0	0
T183	12011	0	0	0
T271	0	25	0	0
T283	0	42	0	0
T292	0	19	0	0
T313	0	26	0	0
T317	42985	0	0	0
T318	51649	0	0	0
T319	65818	0	0	0
T320	100860	0	0	0
T352	0	20	0	0
T353	0	13	0	0
T354	0	1	0	0
T355	44957	0	0	0
T356	23166	0	0	0
T357	17250	0	0	0
T358	4603	0	0	0