Line Coverage for Module :
prim_generic_otp
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 110 | 107 | 97.27 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 84 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 86 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
| ALWAYS | 180 | 71 | 71 | 100.00 |
| CONT_ASSIGN | 329 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 353 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
| ALWAYS | 362 | 0 | 0 | |
| ALWAYS | 362 | 3 | 3 | 100.00 |
| ALWAYS | 396 | 3 | 3 | 100.00 |
| ALWAYS | 399 | 19 | 19 | 100.00 |
75 logic [PwrSeqWidth-1:0] unused_pwr_seq_h;
76 1/1 assign unused_pwr_seq_h = pwr_seq_h_i;
Tests: T2 T3 T4
77 assign pwr_seq_o = '0;
78
79 logic unused_obs;
80 0/1 ==> assign unused_obs = |obs_ctrl_i;
81 assign otp_obs_o = '0;
82
83 wire unused_ext_voltage;
84 0/1 ==> assign unused_ext_voltage = ext_voltage_io;
85 logic unused_test_ctrl_i;
86 0/1 ==> assign unused_test_ctrl_i = ^test_ctrl_i;
87
88 logic unused_scan;
89 1/1 assign unused_scan = ^{scanmode_i, scan_en_i, scan_rst_ni};
Tests: T2 T3 T4
90
91 logic intg_err, fsm_err;
92 1/1 assign fatal_alert_o = intg_err || fsm_err;
Tests: T1 T2 T3
93 assign recov_alert_o = 1'b0;
94
95 assign test_vect_o = '0;
96 assign test_status_o = '0;
97
98 ////////////////////////////////////
99 // TL-UL Test Interface Emulation //
100 ////////////////////////////////////
101
102 otp_ctrl_reg_pkg::otp_ctrl_prim_reg2hw_t reg2hw;
103 otp_ctrl_reg_pkg::otp_ctrl_prim_hw2reg_t hw2reg;
104 otp_ctrl_prim_reg_top u_reg_top (
105 .clk_i,
106 .rst_ni,
107 .tl_i (test_tl_i ),
108 .tl_o (test_tl_o ),
109 .reg2hw (reg2hw ),
110 .hw2reg (hw2reg ),
111 .intg_err_o(intg_err )
112 );
113
114 logic unused_reg_sig;
115 1/1 assign unused_reg_sig = ^reg2hw;
Tests: T1 T2 T3
116 assign hw2reg = '0;
117
118 ///////////////////
119 // Control logic //
120 ///////////////////
121
122 // Encoding generated with:
123 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 9 -n 10 \
124 // -s 2599950981 --language=sv
125 //
126 // Hamming distance histogram:
127 //
128 // 0: --
129 // 1: --
130 // 2: --
131 // 3: --
132 // 4: --
133 // 5: |||||||||||||||||||| (52.78%)
134 // 6: ||||||||||||||| (41.67%)
135 // 7: | (2.78%)
136 // 8: | (2.78%)
137 // 9: --
138 // 10: --
139 //
140 // Minimum Hamming distance: 5
141 // Maximum Hamming distance: 8
142 // Minimum Hamming weight: 3
143 // Maximum Hamming weight: 8
144 //
145 localparam int StateWidth = 10;
146 typedef enum logic [StateWidth-1:0] {
147 ResetSt = 10'b1100000110,
148 InitSt = 10'b1000110011,
149 IdleSt = 10'b0101110000,
150 ReadSt = 10'b0010011111,
151 ReadWaitSt = 10'b1001001101,
152 WriteCheckSt = 10'b1111101011,
153 WriteWaitSt = 10'b0011000010,
154 WriteSt = 10'b0110100101,
155 ErrorSt = 10'b1110011000
156 } state_e;
157
158 state_e state_d, state_q;
159 err_e err_d, err_q;
160 logic valid_d, valid_q;
161 logic integrity_en_d, integrity_en_q;
162 logic req, wren, rvalid;
163 logic [1:0] rerror;
164 logic [AddrWidth-1:0] addr_q;
165 logic [SizeWidth-1:0] size_q;
166 logic [SizeWidth-1:0] cnt_d, cnt_q;
167 logic cnt_clr, cnt_en;
168 logic read_ecc_on, write_ecc_on;
169 logic wdata_inconsistent;
170
171
172 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T2 T3
173 (cnt_en) ? cnt_q + 1'b1 : cnt_q;
174
175 1/1 assign valid_o = valid_q;
Tests: T1 T2 T3
176 1/1 assign err_o = err_q;
Tests: T1 T2 T3
177
178 always_comb begin : p_fsm
179 // Default
180 1/1 state_d = state_q;
Tests: T1 T2 T3
181 1/1 ready_o = 1'b0;
Tests: T1 T2 T3
182 1/1 valid_d = 1'b0;
Tests: T1 T2 T3
183 1/1 err_d = err_q;
Tests: T1 T2 T3
184 1/1 req = 1'b0;
Tests: T1 T2 T3
185 1/1 wren = 1'b0;
Tests: T1 T2 T3
186 1/1 cnt_clr = 1'b0;
Tests: T1 T2 T3
187 1/1 cnt_en = 1'b0;
Tests: T1 T2 T3
188 1/1 read_ecc_on = 1'b1;
Tests: T1 T2 T3
189 1/1 write_ecc_on = 1'b1;
Tests: T1 T2 T3
190 1/1 fsm_err = 1'b0;
Tests: T1 T2 T3
191 1/1 integrity_en_d = integrity_en_q;
Tests: T1 T2 T3
192
193 1/1 unique case (state_q)
Tests: T1 T2 T3
194 // Wait here until we receive an initialization command.
195 ResetSt: begin
196 1/1 err_d = NoError;
Tests: T1 T2 T3
197 1/1 ready_o = 1'b1;
Tests: T1 T2 T3
198 1/1 if (valid_i) begin
Tests: T1 T2 T3
199 1/1 if (cmd_i == Init) begin
Tests: T1 T2 T3
200 1/1 state_d = InitSt;
Tests: T1 T2 T3
201 end
==> MISSING_ELSE
202 end
MISSING_ELSE
203 end
204 // Wait for some time until the OTP macro is ready.
205 InitSt: begin
206 1/1 state_d = IdleSt;
Tests: T1 T2 T3
207 1/1 valid_d = 1'b1;
Tests: T1 T2 T3
208 1/1 err_d = NoError;
Tests: T1 T2 T3
209 end
210 // In the idle state, we basically wait for read or write commands.
211 IdleSt: begin
212 1/1 ready_o = 1'b1;
Tests: T1 T2 T3
213 1/1 err_d = NoError;
Tests: T1 T2 T3
214 1/1 if (valid_i) begin
Tests: T1 T2 T3
215 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T3
216 1/1 err_d = NoError;
Tests: T1 T2 T3
217 1/1 unique case (cmd_i)
Tests: T1 T2 T3
218 Read: begin
219 1/1 state_d = ReadSt;
Tests: T1 T2 T3
220 1/1 integrity_en_d = 1'b1;
Tests: T1 T2 T3
221 end
222 Write: begin
223 1/1 state_d = WriteCheckSt;
Tests: T2 T3 T5
224 1/1 integrity_en_d = 1'b1;
Tests: T2 T3 T5
225 end
226 ReadRaw: begin
227 1/1 state_d = ReadSt;
Tests: T1 T2 T3
228 1/1 integrity_en_d = 1'b0;
Tests: T1 T2 T3
229 end
230 WriteRaw: begin
231 1/1 state_d = WriteCheckSt;
Tests: T2 T3 T4
232 1/1 integrity_en_d = 1'b0;
Tests: T2 T3 T4
233 end
234 default: ;
235 endcase // cmd_i
236 end
MISSING_ELSE
237 end
238 // Issue a read command to the macro.
239 ReadSt: begin
240 1/1 state_d = ReadWaitSt;
Tests: T1 T2 T3
241 1/1 req = 1'b1;
Tests: T1 T2 T3
242 // Suppress ECC correction if needed.
243 1/1 read_ecc_on = integrity_en_q;
Tests: T1 T2 T3
244 end
245 // Wait for response from macro.
246 ReadWaitSt: begin
247 // Suppress ECC correction if needed.
248 1/1 read_ecc_on = integrity_en_q;
Tests: T1 T2 T3
249 1/1 if (rvalid) begin
Tests: T1 T2 T3
250 1/1 cnt_en = 1'b1;
Tests: T1 T2 T3
251 // Uncorrectable error, bail out.
252 1/1 if (rerror[1] && integrity_en_q) begin
Tests: T1 T2 T3
253 1/1 state_d = IdleSt;
Tests: T4 T98 T99
254 1/1 valid_d = 1'b1;
Tests: T4 T98 T99
255 1/1 err_d = MacroEccUncorrError;
Tests: T4 T98 T99
256 end else begin
257 1/1 if (cnt_q == size_q) begin
Tests: T1 T2 T3
258 1/1 state_d = IdleSt;
Tests: T1 T2 T3
259 1/1 valid_d = 1'b1;
Tests: T1 T2 T3
260 end else begin
261 1/1 state_d = ReadSt;
Tests: T1 T2 T3
262 end
263 // Correctable error, carry on but signal back.
264 1/1 if (rerror[0] && integrity_en_q) begin
Tests: T1 T2 T3
265 1/1 err_d = MacroEccCorrError;
Tests: T99 T82 T116
266 end
MISSING_ELSE
267 end
268 end
MISSING_ELSE
269 end
270 // First, read out to perform the write blank check and
271 // read-modify-write operation.
272 WriteCheckSt: begin
273 1/1 state_d = WriteWaitSt;
Tests: T2 T3 T5
274 1/1 req = 1'b1;
Tests: T2 T3 T5
275 // Register raw memory contents without correction so that we can
276 // perform the read-modify-write correctly.
277 1/1 read_ecc_on = 1'b0;
Tests: T2 T3 T5
278 end
279 // Wait for readout to complete first.
280 WriteWaitSt: begin
281 // Register raw memory contents without correction so that we can
282 // perform the read-modify-write correctly.
283 1/1 read_ecc_on = 1'b0;
Tests: T2 T3 T5
284 1/1 if (rvalid) begin
Tests: T2 T3 T5
285 1/1 cnt_en = 1'b1;
Tests: T2 T3 T5
286
287 1/1 if (cnt_q == size_q) begin
Tests: T2 T3 T5
288 1/1 cnt_clr = 1'b1;
Tests: T2 T3 T5
289 1/1 state_d = WriteSt;
Tests: T2 T3 T5
290 end else begin
291 1/1 state_d = WriteCheckSt;
Tests: T2 T3 T5
292 end
293 end
MISSING_ELSE
294 end
295 // If the write data attempts to clear an already programmed bit,
296 // the MacroWriteBlankError needs to be asserted.
297 WriteSt: begin
298 1/1 req = 1'b1;
Tests: T2 T3 T5
299 1/1 wren = 1'b1;
Tests: T2 T3 T5
300 1/1 cnt_en = 1'b1;
Tests: T2 T3 T5
301 // Suppress ECC calculation if needed.
302 1/1 write_ecc_on = integrity_en_q;
Tests: T2 T3 T5
303
304 1/1 if (wdata_inconsistent) begin
Tests: T2 T3 T5
305 1/1 err_d = MacroWriteBlankError;
Tests: T8 T9 T10
306 end
MISSING_ELSE
307
308 1/1 if (cnt_q == size_q) begin
Tests: T2 T3 T5
309 1/1 valid_d = 1'b1;
Tests: T2 T3 T5
310 1/1 state_d = IdleSt;
Tests: T2 T3 T5
311 end
MISSING_ELSE
312 end
313 // If the FSM is glitched into an invalid state.
314 ErrorSt: begin
315 1/1 fsm_err = 1'b1;
Tests: T22 T23 T24
316 end
317 default: begin
318 state_d = ErrorSt;
319 fsm_err = 1'b1;
320 end
321 endcase // state_q
322 end
323
324 ///////////////////////////////////////////
325 // Emulate using ECC protected Block RAM //
326 ///////////////////////////////////////////
327
328 logic [AddrWidth-1:0] addr;
329 1/1 assign addr = addr_q + AddrWidth'(cnt_q);
Tests: T1 T2 T3
330
331 logic [Width-1:0] rdata_corr;
332 logic [Width+EccWidth-1:0] rdata_d, wdata_ecc, rdata_ecc, wdata_rmw;
333 logic [2**SizeWidth-1:0][Width-1:0] wdata_q, rdata_reshaped;
334 logic [2**SizeWidth-1:0][Width+EccWidth-1:0] rdata_q;
335
336 // Use a standard Hamming ECC for OTP.
337 prim_secded_hamming_22_16_enc u_enc (
338 .data_i(wdata_q[cnt_q]),
339 .data_o(wdata_ecc)
340 );
341
342 prim_secded_hamming_22_16_dec u_dec (
343 .data_i (rdata_ecc),
344 .data_o (rdata_corr),
345 .syndrome_o ( ),
346 .err_o (rerror)
347 );
348
349 1/1 assign rdata_d = (read_ecc_on) ? {{EccWidth{1'b0}}, rdata_corr}
Tests: T1 T2 T3
350 : rdata_ecc;
351
352 // Read-modify-write (OTP can only set bits to 1, but not clear to 0).
353 1/1 assign wdata_rmw = (write_ecc_on) ? wdata_ecc | rdata_q[cnt_q]
Tests: T1 T2 T3
354 : {{EccWidth{1'b0}}, wdata_q[cnt_q]} | rdata_q[cnt_q];
355
356 // This indicates if the write data is inconsistent (i.e., if the operation attempts to
357 // clear an already programmed bit to zero).
358 1/1 assign wdata_inconsistent = (rdata_q[cnt_q] & wdata_ecc) != rdata_q[cnt_q];
Tests: T1 T2 T3
359
360 // Output data without ECC bits.
361 always_comb begin : p_output_map
362 1/1 for (int k = 0; k < 2**SizeWidth; k++) begin
Tests: T1 T2 T3
363 1/1 rdata_reshaped[k] = rdata_q[k][Width-1:0];
Tests: T1 T2 T3
364 end
365 1/1 rdata_o = rdata_reshaped;
Tests: T1 T2 T3
366 end
367
368 prim_ram_1p_adv #(
369 .Depth (Depth),
370 .Width (Width + EccWidth),
371 .MemInitFile (MemInitFile),
372 .EnableInputPipeline (1),
373 .EnableOutputPipeline (1)
374 ) u_prim_ram_1p_adv (
375 .clk_i,
376 .rst_ni,
377 .req_i ( req ),
378 .write_i ( wren ),
379 .addr_i ( addr ),
380 .wdata_i ( wdata_rmw ),
381 .wmask_i ( {Width+EccWidth{1'b1}} ),
382 .rdata_o ( rdata_ecc ),
383 .rvalid_o ( rvalid ),
384 .rerror_o ( ),
385 .cfg_i ( '0 ),
386 .alert_o ( )
387 );
388
389 // Currently it is assumed that no wrap arounds can occur.
390 `ASSERT(NoWrapArounds_A, req |-> (addr >= addr_q))
391
392 //////////
393 // Regs //
394 //////////
395
396 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
396.1 `ifdef SIMULATION
396.2 prim_sparse_fsm_flop #(
396.3 .StateEnumT(state_e),
396.4 .Width($bits(state_e)),
396.5 .ResetValue($bits(state_e)'(ResetSt)),
396.6 .EnableAlertTriggerSVA(1),
396.7 .CustomForceName("state_q")
396.8 ) u_state_regs (
396.9 .clk_i ( clk_i ),
396.10 .rst_ni ( rst_ni ),
396.11 .state_i ( state_d ),
396.12 .state_o ( )
396.13 );
396.14 always_ff @(posedge clk_i or negedge rst_ni) begin
396.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
396.16 1/1 state_q <= ResetSt;
Tests: T1 T2 T3
396.17 end else begin
396.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
396.19 end
396.20 end
396.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
396.22 else begin
396.23 `ifdef UVM
396.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
396.25 "../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv", 396, "", 1);
396.26 `else
396.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
396.28 `PRIM_STRINGIFY(u_state_regs_A));
396.29 `endif
396.30 end
396.31 `else
396.32 prim_sparse_fsm_flop #(
396.33 .StateEnumT(state_e),
396.34 .Width($bits(state_e)),
396.35 .ResetValue($bits(state_e)'(ResetSt)),
396.36 .EnableAlertTriggerSVA(1)
396.37 ) u_state_regs (
396.38 .clk_i ( `PRIM_FLOP_CLK ),
396.39 .rst_ni ( `PRIM_FLOP_RST ),
396.40 .state_i ( state_d ),
396.41 .state_o ( state_q )
396.42 );
396.43 `endif397
398 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
399 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
400 1/1 valid_q <= '0;
Tests: T1 T2 T3
401 1/1 err_q <= NoError;
Tests: T1 T2 T3
402 1/1 addr_q <= '0;
Tests: T1 T2 T3
403 1/1 wdata_q <= '0;
Tests: T1 T2 T3
404 1/1 rdata_q <= '0;
Tests: T1 T2 T3
405 1/1 cnt_q <= '0;
Tests: T1 T2 T3
406 1/1 size_q <= '0;
Tests: T1 T2 T3
407 1/1 integrity_en_q <= 1'b0;
Tests: T1 T2 T3
408 end else begin
409 1/1 valid_q <= valid_d;
Tests: T1 T2 T3
410 1/1 err_q <= err_d;
Tests: T1 T2 T3
411 1/1 cnt_q <= cnt_d;
Tests: T1 T2 T3
412 1/1 integrity_en_q <= integrity_en_d;
Tests: T1 T2 T3
413 1/1 if (ready_o && valid_i) begin
Tests: T1 T2 T3
414 1/1 addr_q <= addr_i;
Tests: T1 T2 T3
415 1/1 wdata_q <= wdata_i;
Tests: T1 T2 T3
416 1/1 size_q <= size_i;
Tests: T1 T2 T3
417 end
MISSING_ELSE
418 1/1 if (rvalid) begin
Tests: T1 T2 T3
419 1/1 rdata_q[cnt_q] <= rdata_d;
Tests: T1 T2 T3
420 end
MISSING_ELSE
Cond Coverage for Module :
prim_generic_otp
| Total | Covered | Percent |
|---|
| Conditions | 30 | 29 | 96.67 |
| Logical | 30 | 29 | 96.67 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 92
EXPRESSION (intg_err || fsm_err)
----1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T22,T23,T24 |
| 1 | 0 | Covered | T22,T23,T24 |
LINE 172
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 172
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 199
EXPRESSION (cmd_i == Init)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
LINE 252
EXPRESSION (rerror[1] && integrity_en_q)
----1---- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T4,T98,T99 |
LINE 257
EXPRESSION (cnt_q == size_q)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 264
EXPRESSION (rerror[0] && integrity_en_q)
----1---- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T4,T6 |
| 1 | 1 | Covered | T99,T82,T116 |
LINE 287
EXPRESSION (cnt_q == size_q)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T5 |
| 1 | Covered | T2,T3,T5 |
LINE 308
EXPRESSION (cnt_q == size_q)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T5 |
| 1 | Covered | T2,T3,T5 |
LINE 349
EXPRESSION (read_ecc_on ? ({{EccWidth {1'b0}}, rdata_corr}) : rdata_ecc)
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 353
EXPRESSION (write_ecc_on ? ((wdata_ecc | rdata_q[cnt_q])) : (({{EccWidth {1'b0}}, wdata_q[cnt_q]} | rdata_q[cnt_q])))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION ((rdata_q[cnt_q] & wdata_ecc) != rdata_q[cnt_q])
------------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 413
EXPRESSION (ready_o && valid_i)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
FSM Coverage for Module :
prim_generic_otp
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
9 |
9 |
100.00 |
(Not included in score) |
| Transitions |
11 |
11 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| ErrorSt |
314 |
Covered |
T22,T23,T24 |
| IdleSt |
206 |
Covered |
T1,T2,T3 |
| InitSt |
200 |
Covered |
T1,T2,T3 |
| ReadSt |
219 |
Covered |
T1,T2,T3 |
| ReadWaitSt |
240 |
Covered |
T1,T2,T3 |
| ResetSt |
195 |
Covered |
T1,T2,T3 |
| WriteCheckSt |
223 |
Covered |
T2,T3,T5 |
| WriteSt |
289 |
Covered |
T2,T3,T5 |
| WriteWaitSt |
273 |
Covered |
T2,T3,T5 |
| transitions | Line No. | Covered | Tests |
| IdleSt->ReadSt |
219 |
Covered |
T1,T2,T3 |
| IdleSt->WriteCheckSt |
223 |
Covered |
T2,T3,T5 |
| InitSt->IdleSt |
206 |
Covered |
T1,T2,T3 |
| ReadSt->ReadWaitSt |
240 |
Covered |
T1,T2,T3 |
| ReadWaitSt->IdleSt |
253 |
Covered |
T1,T2,T3 |
| ReadWaitSt->ReadSt |
261 |
Covered |
T1,T2,T3 |
| ResetSt->InitSt |
200 |
Covered |
T1,T2,T3 |
| WriteCheckSt->WriteWaitSt |
273 |
Covered |
T2,T3,T5 |
| WriteSt->IdleSt |
310 |
Covered |
T2,T3,T5 |
| WriteWaitSt->WriteCheckSt |
291 |
Covered |
T2,T3,T5 |
| WriteWaitSt->WriteSt |
289 |
Covered |
T2,T3,T5 |
Branch Coverage for Module :
prim_generic_otp
| Line No. | Total | Covered | Percent |
| Branches |
|
41 |
39 |
95.12 |
| TERNARY |
172 |
3 |
3 |
100.00 |
| TERNARY |
349 |
2 |
2 |
100.00 |
| TERNARY |
353 |
2 |
2 |
100.00 |
| CASE |
193 |
27 |
25 |
92.59 |
| IF |
396 |
2 |
2 |
100.00 |
| IF |
399 |
5 |
5 |
100.00 |
172 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
173 (cnt_en) ? cnt_q + 1'b1 : cnt_q;
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
349 assign rdata_d = (read_ecc_on) ? {{EccWidth{1'b0}}, rdata_corr}
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
353 assign wdata_rmw = (write_ecc_on) ? wdata_ecc | rdata_q[cnt_q]
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T2,T3,T4 |
193 unique case (state_q)
-1-
194 // Wait here until we receive an initialization command.
195 ResetSt: begin
196 err_d = NoError;
197 ready_o = 1'b1;
198 if (valid_i) begin
-2-
199 if (cmd_i == Init) begin
-3-
200 state_d = InitSt;
==>
201 end
MISSING_ELSE
==>
202 end
MISSING_ELSE
==>
203 end
204 // Wait for some time until the OTP macro is ready.
205 InitSt: begin
206 state_d = IdleSt;
==>
207 valid_d = 1'b1;
208 err_d = NoError;
209 end
210 // In the idle state, we basically wait for read or write commands.
211 IdleSt: begin
212 ready_o = 1'b1;
213 err_d = NoError;
214 if (valid_i) begin
-4-
215 cnt_clr = 1'b1;
216 err_d = NoError;
217 unique case (cmd_i)
-5-
218 Read: begin
219 state_d = ReadSt;
==>
220 integrity_en_d = 1'b1;
221 end
222 Write: begin
223 state_d = WriteCheckSt;
==>
224 integrity_en_d = 1'b1;
225 end
226 ReadRaw: begin
227 state_d = ReadSt;
==>
228 integrity_en_d = 1'b0;
229 end
230 WriteRaw: begin
231 state_d = WriteCheckSt;
==>
232 integrity_en_d = 1'b0;
233 end
234 default: ;
==>
235 endcase // cmd_i
236 end
MISSING_ELSE
==>
237 end
238 // Issue a read command to the macro.
239 ReadSt: begin
240 state_d = ReadWaitSt;
==>
241 req = 1'b1;
242 // Suppress ECC correction if needed.
243 read_ecc_on = integrity_en_q;
244 end
245 // Wait for response from macro.
246 ReadWaitSt: begin
247 // Suppress ECC correction if needed.
248 read_ecc_on = integrity_en_q;
249 if (rvalid) begin
-6-
250 cnt_en = 1'b1;
251 // Uncorrectable error, bail out.
252 if (rerror[1] && integrity_en_q) begin
-7-
253 state_d = IdleSt;
==>
254 valid_d = 1'b1;
255 err_d = MacroEccUncorrError;
256 end else begin
257 if (cnt_q == size_q) begin
-8-
258 state_d = IdleSt;
==>
259 valid_d = 1'b1;
260 end else begin
261 state_d = ReadSt;
==>
262 end
263 // Correctable error, carry on but signal back.
264 if (rerror[0] && integrity_en_q) begin
-9-
265 err_d = MacroEccCorrError;
==>
266 end
MISSING_ELSE
==>
267 end
268 end
MISSING_ELSE
==>
269 end
270 // First, read out to perform the write blank check and
271 // read-modify-write operation.
272 WriteCheckSt: begin
273 state_d = WriteWaitSt;
==>
274 req = 1'b1;
275 // Register raw memory contents without correction so that we can
276 // perform the read-modify-write correctly.
277 read_ecc_on = 1'b0;
278 end
279 // Wait for readout to complete first.
280 WriteWaitSt: begin
281 // Register raw memory contents without correction so that we can
282 // perform the read-modify-write correctly.
283 read_ecc_on = 1'b0;
284 if (rvalid) begin
-10-
285 cnt_en = 1'b1;
286
287 if (cnt_q == size_q) begin
-11-
288 cnt_clr = 1'b1;
==>
289 state_d = WriteSt;
290 end else begin
291 state_d = WriteCheckSt;
==>
292 end
293 end
MISSING_ELSE
==>
294 end
295 // If the write data attempts to clear an already programmed bit,
296 // the MacroWriteBlankError needs to be asserted.
297 WriteSt: begin
298 req = 1'b1;
299 wren = 1'b1;
300 cnt_en = 1'b1;
301 // Suppress ECC calculation if needed.
302 write_ecc_on = integrity_en_q;
303
304 if (wdata_inconsistent) begin
-12-
305 err_d = MacroWriteBlankError;
==>
306 end
MISSING_ELSE
==>
307
308 if (cnt_q == size_q) begin
-13-
309 valid_d = 1'b1;
==>
310 state_d = IdleSt;
311 end
MISSING_ELSE
==>
312 end
313 // If the FSM is glitched into an invalid state.
314 ErrorSt: begin
315 fsm_err = 1'b1;
==>
316 end
317 default: begin
318 state_d = ErrorSt;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | Status | Tests |
| ResetSt |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ResetSt |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| InitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
- |
- |
1 |
Read |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
- |
- |
1 |
Write |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T5 |
| IdleSt |
- |
- |
1 |
ReadRaw |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
- |
- |
1 |
WriteRaw |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
| IdleSt |
- |
- |
1 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| IdleSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ReadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ReadWaitSt |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T98,T99 |
| ReadWaitSt |
- |
- |
- |
- |
1 |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ReadWaitSt |
- |
- |
- |
- |
1 |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ReadWaitSt |
- |
- |
- |
- |
1 |
0 |
- |
1 |
- |
- |
- |
- |
Covered |
T99,T82,T116 |
| ReadWaitSt |
- |
- |
- |
- |
1 |
0 |
- |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ReadWaitSt |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| WriteCheckSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T5 |
| WriteWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
Covered |
T2,T3,T5 |
| WriteWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
Covered |
T2,T3,T5 |
| WriteWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T2,T3,T5 |
| WriteSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T8,T9,T10 |
| WriteSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T2,T3,T5 |
| WriteSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T2,T3,T5 |
| WriteSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T2,T3,T5 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T22,T23,T24 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T22,T23,T24 |
396 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
399 if (!rst_ni) begin
-1-
400 valid_q <= '0;
==>
401 err_q <= NoError;
402 addr_q <= '0;
403 wdata_q <= '0;
404 rdata_q <= '0;
405 cnt_q <= '0;
406 size_q <= '0;
407 integrity_en_q <= 1'b0;
408 end else begin
409 valid_q <= valid_d;
410 err_q <= err_d;
411 cnt_q <= cnt_d;
412 integrity_en_q <= integrity_en_d;
413 if (ready_o && valid_i) begin
-2-
414 addr_q <= addr_i;
==>
415 wdata_q <= wdata_i;
416 size_q <= size_i;
417 end
MISSING_ELSE
==>
418 if (rvalid) begin
-3-
419 rdata_q[cnt_q] <= rdata_d;
==>
420 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
1 |
Covered |
T1,T2,T3 |
| 0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_generic_otp
Assertion Details
CheckCommands0_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
87543204 |
11575 |
0 |
0 |
| T1 |
5432 |
1 |
0 |
0 |
| T2 |
10698 |
3 |
0 |
0 |
| T3 |
25481 |
7 |
0 |
0 |
| T4 |
10281 |
3 |
0 |
0 |
| T5 |
4680 |
1 |
0 |
0 |
| T6 |
40011 |
9 |
0 |
0 |
| T7 |
36446 |
11 |
0 |
0 |
| T11 |
6282 |
1 |
0 |
0 |
| T12 |
98597 |
2 |
0 |
0 |
| T13 |
28315 |
5 |
0 |
0 |
CheckCommands1_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
87543204 |
1137942 |
0 |
0 |
| T1 |
5432 |
54 |
0 |
0 |
| T2 |
10698 |
196 |
0 |
0 |
| T3 |
25481 |
365 |
0 |
0 |
| T4 |
10281 |
144 |
0 |
0 |
| T5 |
4680 |
110 |
0 |
0 |
| T6 |
40011 |
740 |
0 |
0 |
| T7 |
36446 |
1421 |
0 |
0 |
| T11 |
6282 |
54 |
0 |
0 |
| T12 |
98597 |
141 |
0 |
0 |
| T13 |
28315 |
444 |
0 |
0 |
NoWrapArounds_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
87543204 |
3591831 |
0 |
0 |
| T1 |
5432 |
216 |
0 |
0 |
| T2 |
10698 |
771 |
0 |
0 |
| T3 |
25481 |
1453 |
0 |
0 |
| T4 |
10281 |
522 |
0 |
0 |
| T5 |
4680 |
352 |
0 |
0 |
| T6 |
40011 |
2525 |
0 |
0 |
| T7 |
36446 |
4097 |
0 |
0 |
| T11 |
6282 |
216 |
0 |
0 |
| T12 |
98597 |
590 |
0 |
0 |
| T13 |
28315 |
1590 |
0 |
0 |
SecDecWidth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1124 |
1124 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
87543204 |
86701732 |
0 |
0 |
| T1 |
5432 |
5382 |
0 |
0 |
| T2 |
10698 |
10452 |
0 |
0 |
| T3 |
25481 |
25010 |
0 |
0 |
| T4 |
10281 |
10014 |
0 |
0 |
| T5 |
4680 |
4619 |
0 |
0 |
| T6 |
40011 |
39222 |
0 |
0 |
| T7 |
36446 |
35679 |
0 |
0 |
| T11 |
6282 |
6220 |
0 |
0 |
| T12 |
98597 |
98413 |
0 |
0 |
| T13 |
28315 |
27844 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 110 | 107 | 97.27 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 84 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 86 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
| ALWAYS | 180 | 71 | 71 | 100.00 |
| CONT_ASSIGN | 329 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 353 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
| ALWAYS | 362 | 0 | 0 | |
| ALWAYS | 362 | 3 | 3 | 100.00 |
| ALWAYS | 396 | 3 | 3 | 100.00 |
| ALWAYS | 399 | 19 | 19 | 100.00 |
75 logic [PwrSeqWidth-1:0] unused_pwr_seq_h;
76 1/1 assign unused_pwr_seq_h = pwr_seq_h_i;
Tests: T2 T3 T4
77 assign pwr_seq_o = '0;
78
79 logic unused_obs;
80 0/1 ==> assign unused_obs = |obs_ctrl_i;
81 assign otp_obs_o = '0;
82
83 wire unused_ext_voltage;
84 0/1 ==> assign unused_ext_voltage = ext_voltage_io;
85 logic unused_test_ctrl_i;
86 0/1 ==> assign unused_test_ctrl_i = ^test_ctrl_i;
87
88 logic unused_scan;
89 1/1 assign unused_scan = ^{scanmode_i, scan_en_i, scan_rst_ni};
Tests: T2 T3 T4
90
91 logic intg_err, fsm_err;
92 1/1 assign fatal_alert_o = intg_err || fsm_err;
Tests: T1 T2 T3
93 assign recov_alert_o = 1'b0;
94
95 assign test_vect_o = '0;
96 assign test_status_o = '0;
97
98 ////////////////////////////////////
99 // TL-UL Test Interface Emulation //
100 ////////////////////////////////////
101
102 otp_ctrl_reg_pkg::otp_ctrl_prim_reg2hw_t reg2hw;
103 otp_ctrl_reg_pkg::otp_ctrl_prim_hw2reg_t hw2reg;
104 otp_ctrl_prim_reg_top u_reg_top (
105 .clk_i,
106 .rst_ni,
107 .tl_i (test_tl_i ),
108 .tl_o (test_tl_o ),
109 .reg2hw (reg2hw ),
110 .hw2reg (hw2reg ),
111 .intg_err_o(intg_err )
112 );
113
114 logic unused_reg_sig;
115 1/1 assign unused_reg_sig = ^reg2hw;
Tests: T1 T2 T3
116 assign hw2reg = '0;
117
118 ///////////////////
119 // Control logic //
120 ///////////////////
121
122 // Encoding generated with:
123 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 9 -n 10 \
124 // -s 2599950981 --language=sv
125 //
126 // Hamming distance histogram:
127 //
128 // 0: --
129 // 1: --
130 // 2: --
131 // 3: --
132 // 4: --
133 // 5: |||||||||||||||||||| (52.78%)
134 // 6: ||||||||||||||| (41.67%)
135 // 7: | (2.78%)
136 // 8: | (2.78%)
137 // 9: --
138 // 10: --
139 //
140 // Minimum Hamming distance: 5
141 // Maximum Hamming distance: 8
142 // Minimum Hamming weight: 3
143 // Maximum Hamming weight: 8
144 //
145 localparam int StateWidth = 10;
146 typedef enum logic [StateWidth-1:0] {
147 ResetSt = 10'b1100000110,
148 InitSt = 10'b1000110011,
149 IdleSt = 10'b0101110000,
150 ReadSt = 10'b0010011111,
151 ReadWaitSt = 10'b1001001101,
152 WriteCheckSt = 10'b1111101011,
153 WriteWaitSt = 10'b0011000010,
154 WriteSt = 10'b0110100101,
155 ErrorSt = 10'b1110011000
156 } state_e;
157
158 state_e state_d, state_q;
159 err_e err_d, err_q;
160 logic valid_d, valid_q;
161 logic integrity_en_d, integrity_en_q;
162 logic req, wren, rvalid;
163 logic [1:0] rerror;
164 logic [AddrWidth-1:0] addr_q;
165 logic [SizeWidth-1:0] size_q;
166 logic [SizeWidth-1:0] cnt_d, cnt_q;
167 logic cnt_clr, cnt_en;
168 logic read_ecc_on, write_ecc_on;
169 logic wdata_inconsistent;
170
171
172 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T2 T3
173 (cnt_en) ? cnt_q + 1'b1 : cnt_q;
174
175 1/1 assign valid_o = valid_q;
Tests: T1 T2 T3
176 1/1 assign err_o = err_q;
Tests: T1 T2 T3
177
178 always_comb begin : p_fsm
179 // Default
180 1/1 state_d = state_q;
Tests: T1 T2 T3
181 1/1 ready_o = 1'b0;
Tests: T1 T2 T3
182 1/1 valid_d = 1'b0;
Tests: T1 T2 T3
183 1/1 err_d = err_q;
Tests: T1 T2 T3
184 1/1 req = 1'b0;
Tests: T1 T2 T3
185 1/1 wren = 1'b0;
Tests: T1 T2 T3
186 1/1 cnt_clr = 1'b0;
Tests: T1 T2 T3
187 1/1 cnt_en = 1'b0;
Tests: T1 T2 T3
188 1/1 read_ecc_on = 1'b1;
Tests: T1 T2 T3
189 1/1 write_ecc_on = 1'b1;
Tests: T1 T2 T3
190 1/1 fsm_err = 1'b0;
Tests: T1 T2 T3
191 1/1 integrity_en_d = integrity_en_q;
Tests: T1 T2 T3
192
193 1/1 unique case (state_q)
Tests: T1 T2 T3
194 // Wait here until we receive an initialization command.
195 ResetSt: begin
196 1/1 err_d = NoError;
Tests: T1 T2 T3
197 1/1 ready_o = 1'b1;
Tests: T1 T2 T3
198 1/1 if (valid_i) begin
Tests: T1 T2 T3
199 1/1 if (cmd_i == Init) begin
Tests: T1 T2 T3
200 1/1 state_d = InitSt;
Tests: T1 T2 T3
201 end
==> MISSING_ELSE
202 end
MISSING_ELSE
203 end
204 // Wait for some time until the OTP macro is ready.
205 InitSt: begin
206 1/1 state_d = IdleSt;
Tests: T1 T2 T3
207 1/1 valid_d = 1'b1;
Tests: T1 T2 T3
208 1/1 err_d = NoError;
Tests: T1 T2 T3
209 end
210 // In the idle state, we basically wait for read or write commands.
211 IdleSt: begin
212 1/1 ready_o = 1'b1;
Tests: T1 T2 T3
213 1/1 err_d = NoError;
Tests: T1 T2 T3
214 1/1 if (valid_i) begin
Tests: T1 T2 T3
215 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T3
216 1/1 err_d = NoError;
Tests: T1 T2 T3
217 1/1 unique case (cmd_i)
Tests: T1 T2 T3
218 Read: begin
219 1/1 state_d = ReadSt;
Tests: T1 T2 T3
220 1/1 integrity_en_d = 1'b1;
Tests: T1 T2 T3
221 end
222 Write: begin
223 1/1 state_d = WriteCheckSt;
Tests: T2 T3 T5
224 1/1 integrity_en_d = 1'b1;
Tests: T2 T3 T5
225 end
226 ReadRaw: begin
227 1/1 state_d = ReadSt;
Tests: T1 T2 T3
228 1/1 integrity_en_d = 1'b0;
Tests: T1 T2 T3
229 end
230 WriteRaw: begin
231 1/1 state_d = WriteCheckSt;
Tests: T2 T3 T4
232 1/1 integrity_en_d = 1'b0;
Tests: T2 T3 T4
233 end
234 default: ;
Exclude Annotation: VC_COV_UNR
235 endcase // cmd_i
236 end
MISSING_ELSE
237 end
238 // Issue a read command to the macro.
239 ReadSt: begin
240 1/1 state_d = ReadWaitSt;
Tests: T1 T2 T3
241 1/1 req = 1'b1;
Tests: T1 T2 T3
242 // Suppress ECC correction if needed.
243 1/1 read_ecc_on = integrity_en_q;
Tests: T1 T2 T3
244 end
245 // Wait for response from macro.
246 ReadWaitSt: begin
247 // Suppress ECC correction if needed.
248 1/1 read_ecc_on = integrity_en_q;
Tests: T1 T2 T3
249 1/1 if (rvalid) begin
Tests: T1 T2 T3
250 1/1 cnt_en = 1'b1;
Tests: T1 T2 T3
251 // Uncorrectable error, bail out.
252 1/1 if (rerror[1] && integrity_en_q) begin
Tests: T1 T2 T3
253 1/1 state_d = IdleSt;
Tests: T4 T98 T99
254 1/1 valid_d = 1'b1;
Tests: T4 T98 T99
255 1/1 err_d = MacroEccUncorrError;
Tests: T4 T98 T99
256 end else begin
257 1/1 if (cnt_q == size_q) begin
Tests: T1 T2 T3
258 1/1 state_d = IdleSt;
Tests: T1 T2 T3
259 1/1 valid_d = 1'b1;
Tests: T1 T2 T3
260 end else begin
261 1/1 state_d = ReadSt;
Tests: T1 T2 T3
262 end
263 // Correctable error, carry on but signal back.
264 1/1 if (rerror[0] && integrity_en_q) begin
Tests: T1 T2 T3
265 1/1 err_d = MacroEccCorrError;
Tests: T99 T82 T116
266 end
MISSING_ELSE
267 end
268 end
MISSING_ELSE
269 end
270 // First, read out to perform the write blank check and
271 // read-modify-write operation.
272 WriteCheckSt: begin
273 1/1 state_d = WriteWaitSt;
Tests: T2 T3 T5
274 1/1 req = 1'b1;
Tests: T2 T3 T5
275 // Register raw memory contents without correction so that we can
276 // perform the read-modify-write correctly.
277 1/1 read_ecc_on = 1'b0;
Tests: T2 T3 T5
278 end
279 // Wait for readout to complete first.
280 WriteWaitSt: begin
281 // Register raw memory contents without correction so that we can
282 // perform the read-modify-write correctly.
283 1/1 read_ecc_on = 1'b0;
Tests: T2 T3 T5
284 1/1 if (rvalid) begin
Tests: T2 T3 T5
285 1/1 cnt_en = 1'b1;
Tests: T2 T3 T5
286
287 1/1 if (cnt_q == size_q) begin
Tests: T2 T3 T5
288 1/1 cnt_clr = 1'b1;
Tests: T2 T3 T5
289 1/1 state_d = WriteSt;
Tests: T2 T3 T5
290 end else begin
291 1/1 state_d = WriteCheckSt;
Tests: T2 T3 T5
292 end
293 end
MISSING_ELSE
294 end
295 // If the write data attempts to clear an already programmed bit,
296 // the MacroWriteBlankError needs to be asserted.
297 WriteSt: begin
298 1/1 req = 1'b1;
Tests: T2 T3 T5
299 1/1 wren = 1'b1;
Tests: T2 T3 T5
300 1/1 cnt_en = 1'b1;
Tests: T2 T3 T5
301 // Suppress ECC calculation if needed.
302 1/1 write_ecc_on = integrity_en_q;
Tests: T2 T3 T5
303
304 1/1 if (wdata_inconsistent) begin
Tests: T2 T3 T5
305 1/1 err_d = MacroWriteBlankError;
Tests: T8 T9 T10
306 end
MISSING_ELSE
307
308 1/1 if (cnt_q == size_q) begin
Tests: T2 T3 T5
309 1/1 valid_d = 1'b1;
Tests: T2 T3 T5
310 1/1 state_d = IdleSt;
Tests: T2 T3 T5
311 end
MISSING_ELSE
312 end
313 // If the FSM is glitched into an invalid state.
314 ErrorSt: begin
315 1/1 fsm_err = 1'b1;
Tests: T22 T23 T24
316 end
317 default: begin
318 state_d = ErrorSt;
319 fsm_err = 1'b1;
320 end
321 endcase // state_q
322 end
323
324 ///////////////////////////////////////////
325 // Emulate using ECC protected Block RAM //
326 ///////////////////////////////////////////
327
328 logic [AddrWidth-1:0] addr;
329 1/1 assign addr = addr_q + AddrWidth'(cnt_q);
Tests: T1 T2 T3
330
331 logic [Width-1:0] rdata_corr;
332 logic [Width+EccWidth-1:0] rdata_d, wdata_ecc, rdata_ecc, wdata_rmw;
333 logic [2**SizeWidth-1:0][Width-1:0] wdata_q, rdata_reshaped;
334 logic [2**SizeWidth-1:0][Width+EccWidth-1:0] rdata_q;
335
336 // Use a standard Hamming ECC for OTP.
337 prim_secded_hamming_22_16_enc u_enc (
338 .data_i(wdata_q[cnt_q]),
339 .data_o(wdata_ecc)
340 );
341
342 prim_secded_hamming_22_16_dec u_dec (
343 .data_i (rdata_ecc),
344 .data_o (rdata_corr),
345 .syndrome_o ( ),
346 .err_o (rerror)
347 );
348
349 1/1 assign rdata_d = (read_ecc_on) ? {{EccWidth{1'b0}}, rdata_corr}
Tests: T1 T2 T3
350 : rdata_ecc;
351
352 // Read-modify-write (OTP can only set bits to 1, but not clear to 0).
353 1/1 assign wdata_rmw = (write_ecc_on) ? wdata_ecc | rdata_q[cnt_q]
Tests: T1 T2 T3
354 : {{EccWidth{1'b0}}, wdata_q[cnt_q]} | rdata_q[cnt_q];
355
356 // This indicates if the write data is inconsistent (i.e., if the operation attempts to
357 // clear an already programmed bit to zero).
358 1/1 assign wdata_inconsistent = (rdata_q[cnt_q] & wdata_ecc) != rdata_q[cnt_q];
Tests: T1 T2 T3
359
360 // Output data without ECC bits.
361 always_comb begin : p_output_map
362 1/1 for (int k = 0; k < 2**SizeWidth; k++) begin
Tests: T1 T2 T3
363 1/1 rdata_reshaped[k] = rdata_q[k][Width-1:0];
Tests: T1 T2 T3
364 end
365 1/1 rdata_o = rdata_reshaped;
Tests: T1 T2 T3
366 end
367
368 prim_ram_1p_adv #(
369 .Depth (Depth),
370 .Width (Width + EccWidth),
371 .MemInitFile (MemInitFile),
372 .EnableInputPipeline (1),
373 .EnableOutputPipeline (1)
374 ) u_prim_ram_1p_adv (
375 .clk_i,
376 .rst_ni,
377 .req_i ( req ),
378 .write_i ( wren ),
379 .addr_i ( addr ),
380 .wdata_i ( wdata_rmw ),
381 .wmask_i ( {Width+EccWidth{1'b1}} ),
382 .rdata_o ( rdata_ecc ),
383 .rvalid_o ( rvalid ),
384 .rerror_o ( ),
385 .cfg_i ( '0 ),
386 .alert_o ( )
387 );
388
389 // Currently it is assumed that no wrap arounds can occur.
390 `ASSERT(NoWrapArounds_A, req |-> (addr >= addr_q))
391
392 //////////
393 // Regs //
394 //////////
395
396 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
396.1 `ifdef SIMULATION
396.2 prim_sparse_fsm_flop #(
396.3 .StateEnumT(state_e),
396.4 .Width($bits(state_e)),
396.5 .ResetValue($bits(state_e)'(ResetSt)),
396.6 .EnableAlertTriggerSVA(1),
396.7 .CustomForceName("state_q")
396.8 ) u_state_regs (
396.9 .clk_i ( clk_i ),
396.10 .rst_ni ( rst_ni ),
396.11 .state_i ( state_d ),
396.12 .state_o ( )
396.13 );
396.14 always_ff @(posedge clk_i or negedge rst_ni) begin
396.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
396.16 1/1 state_q <= ResetSt;
Tests: T1 T2 T3
396.17 end else begin
396.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
396.19 end
396.20 end
396.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
396.22 else begin
396.23 `ifdef UVM
396.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
396.25 "../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv", 396, "", 1);
396.26 `else
396.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
396.28 `PRIM_STRINGIFY(u_state_regs_A));
396.29 `endif
396.30 end
396.31 `else
396.32 prim_sparse_fsm_flop #(
396.33 .StateEnumT(state_e),
396.34 .Width($bits(state_e)),
396.35 .ResetValue($bits(state_e)'(ResetSt)),
396.36 .EnableAlertTriggerSVA(1)
396.37 ) u_state_regs (
396.38 .clk_i ( `PRIM_FLOP_CLK ),
396.39 .rst_ni ( `PRIM_FLOP_RST ),
396.40 .state_i ( state_d ),
396.41 .state_o ( state_q )
396.42 );
396.43 `endif397
398 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
399 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
400 1/1 valid_q <= '0;
Tests: T1 T2 T3
401 1/1 err_q <= NoError;
Tests: T1 T2 T3
402 1/1 addr_q <= '0;
Tests: T1 T2 T3
403 1/1 wdata_q <= '0;
Tests: T1 T2 T3
404 1/1 rdata_q <= '0;
Tests: T1 T2 T3
405 1/1 cnt_q <= '0;
Tests: T1 T2 T3
406 1/1 size_q <= '0;
Tests: T1 T2 T3
407 1/1 integrity_en_q <= 1'b0;
Tests: T1 T2 T3
408 end else begin
409 1/1 valid_q <= valid_d;
Tests: T1 T2 T3
410 1/1 err_q <= err_d;
Tests: T1 T2 T3
411 1/1 cnt_q <= cnt_d;
Tests: T1 T2 T3
412 1/1 integrity_en_q <= integrity_en_d;
Tests: T1 T2 T3
413 1/1 if (ready_o && valid_i) begin
Tests: T1 T2 T3
414 1/1 addr_q <= addr_i;
Tests: T1 T2 T3
415 1/1 wdata_q <= wdata_i;
Tests: T1 T2 T3
416 1/1 size_q <= size_i;
Tests: T1 T2 T3
417 end
MISSING_ELSE
418 1/1 if (rvalid) begin
Tests: T1 T2 T3
419 1/1 rdata_q[cnt_q] <= rdata_d;
Tests: T1 T2 T3
420 end
MISSING_ELSE
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 29 | 29 | 100.00 |
| Logical | 29 | 29 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 92
EXPRESSION (intg_err || fsm_err)
----1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T22,T23,T24 |
| 1 | 0 | Covered | T22,T23,T24 |
LINE 172
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 172
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 199
EXPRESSION (cmd_i == Init)
-------1-------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
LINE 252
EXPRESSION (rerror[1] && integrity_en_q)
----1---- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T4,T98,T99 |
LINE 257
EXPRESSION (cnt_q == size_q)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 264
EXPRESSION (rerror[0] && integrity_en_q)
----1---- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T4,T6 |
| 1 | 1 | Covered | T99,T82,T116 |
LINE 287
EXPRESSION (cnt_q == size_q)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T5 |
| 1 | Covered | T2,T3,T5 |
LINE 308
EXPRESSION (cnt_q == size_q)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T5 |
| 1 | Covered | T2,T3,T5 |
LINE 349
EXPRESSION (read_ecc_on ? ({{EccWidth {1'b0}}, rdata_corr}) : rdata_ecc)
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 353
EXPRESSION (write_ecc_on ? ((wdata_ecc | rdata_q[cnt_q])) : (({{EccWidth {1'b0}}, wdata_q[cnt_q]} | rdata_q[cnt_q])))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION ((rdata_q[cnt_q] & wdata_ecc) != rdata_q[cnt_q])
------------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 413
EXPRESSION (ready_o && valid_i)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
FSM Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
9 |
9 |
100.00 |
(Not included in score) |
| Transitions |
11 |
11 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| ErrorSt |
314 |
Covered |
T22,T23,T24 |
| IdleSt |
206 |
Covered |
T1,T2,T3 |
| InitSt |
200 |
Covered |
T1,T2,T3 |
| ReadSt |
219 |
Covered |
T1,T2,T3 |
| ReadWaitSt |
240 |
Covered |
T1,T2,T3 |
| ResetSt |
195 |
Covered |
T1,T2,T3 |
| WriteCheckSt |
223 |
Covered |
T2,T3,T5 |
| WriteSt |
289 |
Covered |
T2,T3,T5 |
| WriteWaitSt |
273 |
Covered |
T2,T3,T5 |
| transitions | Line No. | Covered | Tests |
| IdleSt->ReadSt |
219 |
Covered |
T1,T2,T3 |
| IdleSt->WriteCheckSt |
223 |
Covered |
T2,T3,T5 |
| InitSt->IdleSt |
206 |
Covered |
T1,T2,T3 |
| ReadSt->ReadWaitSt |
240 |
Covered |
T1,T2,T3 |
| ReadWaitSt->IdleSt |
253 |
Covered |
T1,T2,T3 |
| ReadWaitSt->ReadSt |
261 |
Covered |
T1,T2,T3 |
| ResetSt->InitSt |
200 |
Covered |
T1,T2,T3 |
| WriteCheckSt->WriteWaitSt |
273 |
Covered |
T2,T3,T5 |
| WriteSt->IdleSt |
310 |
Covered |
T2,T3,T5 |
| WriteWaitSt->WriteCheckSt |
291 |
Covered |
T2,T3,T5 |
| WriteWaitSt->WriteSt |
289 |
Covered |
T2,T3,T5 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
39 |
39 |
100.00 |
| TERNARY |
172 |
3 |
3 |
100.00 |
| TERNARY |
349 |
2 |
2 |
100.00 |
| TERNARY |
353 |
2 |
2 |
100.00 |
| CASE |
193 |
25 |
25 |
100.00 |
| IF |
396 |
2 |
2 |
100.00 |
| IF |
399 |
5 |
5 |
100.00 |
172 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
173 (cnt_en) ? cnt_q + 1'b1 : cnt_q;
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
349 assign rdata_d = (read_ecc_on) ? {{EccWidth{1'b0}}, rdata_corr}
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
353 assign wdata_rmw = (write_ecc_on) ? wdata_ecc | rdata_q[cnt_q]
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T2,T3,T4 |
193 unique case (state_q)
-1-
194 // Wait here until we receive an initialization command.
195 ResetSt: begin
196 err_d = NoError;
197 ready_o = 1'b1;
198 if (valid_i) begin
-2-
199 if (cmd_i == Init) begin
-3-
200 state_d = InitSt;
==>
201 end
MISSING_ELSE
==> (Excluded)
Exclude Annotation: VC_COV_UNR
202 end
MISSING_ELSE
==>
203 end
204 // Wait for some time until the OTP macro is ready.
205 InitSt: begin
206 state_d = IdleSt;
==>
207 valid_d = 1'b1;
208 err_d = NoError;
209 end
210 // In the idle state, we basically wait for read or write commands.
211 IdleSt: begin
212 ready_o = 1'b1;
213 err_d = NoError;
214 if (valid_i) begin
-4-
215 cnt_clr = 1'b1;
216 err_d = NoError;
217 unique case (cmd_i)
-5-
218 Read: begin
219 state_d = ReadSt;
==>
220 integrity_en_d = 1'b1;
221 end
222 Write: begin
223 state_d = WriteCheckSt;
==>
224 integrity_en_d = 1'b1;
225 end
226 ReadRaw: begin
227 state_d = ReadSt;
==>
228 integrity_en_d = 1'b0;
229 end
230 WriteRaw: begin
231 state_d = WriteCheckSt;
==>
232 integrity_en_d = 1'b0;
233 end
234 default: ;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
235 endcase // cmd_i
236 end
MISSING_ELSE
==>
237 end
238 // Issue a read command to the macro.
239 ReadSt: begin
240 state_d = ReadWaitSt;
==>
241 req = 1'b1;
242 // Suppress ECC correction if needed.
243 read_ecc_on = integrity_en_q;
244 end
245 // Wait for response from macro.
246 ReadWaitSt: begin
247 // Suppress ECC correction if needed.
248 read_ecc_on = integrity_en_q;
249 if (rvalid) begin
-6-
250 cnt_en = 1'b1;
251 // Uncorrectable error, bail out.
252 if (rerror[1] && integrity_en_q) begin
-7-
253 state_d = IdleSt;
==>
254 valid_d = 1'b1;
255 err_d = MacroEccUncorrError;
256 end else begin
257 if (cnt_q == size_q) begin
-8-
258 state_d = IdleSt;
==>
259 valid_d = 1'b1;
260 end else begin
261 state_d = ReadSt;
==>
262 end
263 // Correctable error, carry on but signal back.
264 if (rerror[0] && integrity_en_q) begin
-9-
265 err_d = MacroEccCorrError;
==>
266 end
MISSING_ELSE
==>
267 end
268 end
MISSING_ELSE
==>
269 end
270 // First, read out to perform the write blank check and
271 // read-modify-write operation.
272 WriteCheckSt: begin
273 state_d = WriteWaitSt;
==>
274 req = 1'b1;
275 // Register raw memory contents without correction so that we can
276 // perform the read-modify-write correctly.
277 read_ecc_on = 1'b0;
278 end
279 // Wait for readout to complete first.
280 WriteWaitSt: begin
281 // Register raw memory contents without correction so that we can
282 // perform the read-modify-write correctly.
283 read_ecc_on = 1'b0;
284 if (rvalid) begin
-10-
285 cnt_en = 1'b1;
286
287 if (cnt_q == size_q) begin
-11-
288 cnt_clr = 1'b1;
==>
289 state_d = WriteSt;
290 end else begin
291 state_d = WriteCheckSt;
==>
292 end
293 end
MISSING_ELSE
==>
294 end
295 // If the write data attempts to clear an already programmed bit,
296 // the MacroWriteBlankError needs to be asserted.
297 WriteSt: begin
298 req = 1'b1;
299 wren = 1'b1;
300 cnt_en = 1'b1;
301 // Suppress ECC calculation if needed.
302 write_ecc_on = integrity_en_q;
303
304 if (wdata_inconsistent) begin
-12-
305 err_d = MacroWriteBlankError;
==>
306 end
MISSING_ELSE
==>
307
308 if (cnt_q == size_q) begin
-13-
309 valid_d = 1'b1;
==>
310 state_d = IdleSt;
311 end
MISSING_ELSE
==>
312 end
313 // If the FSM is glitched into an invalid state.
314 ErrorSt: begin
315 fsm_err = 1'b1;
==>
316 end
317 default: begin
318 state_d = ErrorSt;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | Status | Tests | Exclude Annotation |
| ResetSt |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| ResetSt |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
| ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| InitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| IdleSt |
- |
- |
1 |
Read |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| IdleSt |
- |
- |
1 |
Write |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T5 |
|
| IdleSt |
- |
- |
1 |
ReadRaw |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| IdleSt |
- |
- |
1 |
WriteRaw |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
|
| IdleSt |
- |
- |
1 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
| IdleSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| ReadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| ReadWaitSt |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T98,T99 |
|
| ReadWaitSt |
- |
- |
- |
- |
1 |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| ReadWaitSt |
- |
- |
- |
- |
1 |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| ReadWaitSt |
- |
- |
- |
- |
1 |
0 |
- |
1 |
- |
- |
- |
- |
Covered |
T99,T82,T116 |
|
| ReadWaitSt |
- |
- |
- |
- |
1 |
0 |
- |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| ReadWaitSt |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| WriteCheckSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T5 |
|
| WriteWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
Covered |
T2,T3,T5 |
|
| WriteWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
Covered |
T2,T3,T5 |
|
| WriteWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T2,T3,T5 |
|
| WriteSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T8,T9,T10 |
|
| WriteSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T2,T3,T5 |
|
| WriteSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T2,T3,T5 |
|
| WriteSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T2,T3,T5 |
|
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T22,T23,T24 |
|
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T22,T23,T24 |
|
396 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
399 if (!rst_ni) begin
-1-
400 valid_q <= '0;
==>
401 err_q <= NoError;
402 addr_q <= '0;
403 wdata_q <= '0;
404 rdata_q <= '0;
405 cnt_q <= '0;
406 size_q <= '0;
407 integrity_en_q <= 1'b0;
408 end else begin
409 valid_q <= valid_d;
410 err_q <= err_d;
411 cnt_q <= cnt_d;
412 integrity_en_q <= integrity_en_d;
413 if (ready_o && valid_i) begin
-2-
414 addr_q <= addr_i;
==>
415 wdata_q <= wdata_i;
416 size_q <= size_i;
417 end
MISSING_ELSE
==>
418 if (rvalid) begin
-3-
419 rdata_q[cnt_q] <= rdata_d;
==>
420 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
1 |
Covered |
T1,T2,T3 |
| 0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic
Assertion Details
CheckCommands0_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
87543204 |
11575 |
0 |
0 |
| T1 |
5432 |
1 |
0 |
0 |
| T2 |
10698 |
3 |
0 |
0 |
| T3 |
25481 |
7 |
0 |
0 |
| T4 |
10281 |
3 |
0 |
0 |
| T5 |
4680 |
1 |
0 |
0 |
| T6 |
40011 |
9 |
0 |
0 |
| T7 |
36446 |
11 |
0 |
0 |
| T11 |
6282 |
1 |
0 |
0 |
| T12 |
98597 |
2 |
0 |
0 |
| T13 |
28315 |
5 |
0 |
0 |
CheckCommands1_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
87543204 |
1137942 |
0 |
0 |
| T1 |
5432 |
54 |
0 |
0 |
| T2 |
10698 |
196 |
0 |
0 |
| T3 |
25481 |
365 |
0 |
0 |
| T4 |
10281 |
144 |
0 |
0 |
| T5 |
4680 |
110 |
0 |
0 |
| T6 |
40011 |
740 |
0 |
0 |
| T7 |
36446 |
1421 |
0 |
0 |
| T11 |
6282 |
54 |
0 |
0 |
| T12 |
98597 |
141 |
0 |
0 |
| T13 |
28315 |
444 |
0 |
0 |
NoWrapArounds_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
87543204 |
3591831 |
0 |
0 |
| T1 |
5432 |
216 |
0 |
0 |
| T2 |
10698 |
771 |
0 |
0 |
| T3 |
25481 |
1453 |
0 |
0 |
| T4 |
10281 |
522 |
0 |
0 |
| T5 |
4680 |
352 |
0 |
0 |
| T6 |
40011 |
2525 |
0 |
0 |
| T7 |
36446 |
4097 |
0 |
0 |
| T11 |
6282 |
216 |
0 |
0 |
| T12 |
98597 |
590 |
0 |
0 |
| T13 |
28315 |
1590 |
0 |
0 |
SecDecWidth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1124 |
1124 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
87543204 |
86701732 |
0 |
0 |
| T1 |
5432 |
5382 |
0 |
0 |
| T2 |
10698 |
10452 |
0 |
0 |
| T3 |
25481 |
25010 |
0 |
0 |
| T4 |
10281 |
10014 |
0 |
0 |
| T5 |
4680 |
4619 |
0 |
0 |
| T6 |
40011 |
39222 |
0 |
0 |
| T7 |
36446 |
35679 |
0 |
0 |
| T11 |
6282 |
6220 |
0 |
0 |
| T12 |
98597 |
98413 |
0 |
0 |
| T13 |
28315 |
27844 |
0 |
0 |