Module Definition
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Module : prim_secded_inv_72_64_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 62.50 62.50
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 64.71 64.71
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 69.12 69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 69.12 69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 69.12 69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 71.32 71.32
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 75.00 75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 76.47 76.47
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 80.88 80.88
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 83.82 83.82
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 91.18 91.18
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.50 62.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.50 62.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.71 64.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.71 64.71


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.32 71.32


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.32 71.32


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.88 80.88


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.88 80.88


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.82 83.82


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.82 83.82


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.18 91.18


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.18 91.18


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T6,T17,T99 Yes T6,T12,T17 INPUT
data_o[63:0] Yes Yes T6,T17,T99 Yes T6,T12,T17 OUTPUT
syndrome_o[2:0] Yes Yes T107,T109,T179 Yes T107,T109,T179 OUTPUT
syndrome_o[7:3] No No No OUTPUT
err_o[0] Yes Yes *T107,*T109,*T179 Yes T107,T109,T179 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 170 62.50
Total Bits 0->1 136 85 62.50
Total Bits 1->0 136 85 62.50

Ports 2 0 0.00
Port Bits 272 170 62.50
Port Bits 0->1 136 85 62.50
Port Bits 1->0 136 85 62.50

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T6,*T7,*T17 Yes T6,T7,T17 INPUT
data_i[1] No No No INPUT
data_i[4:2] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[5] No No No INPUT
data_i[8:6] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[9] No No No INPUT
data_i[10] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[11] No No No INPUT
data_i[12] Yes Yes *T6,*T7,*T17 Yes T6,T7,T17 INPUT
data_i[13] No No No INPUT
data_i[15:14] Yes Yes T6,T7,T17 Yes T6,T7,T17 INPUT
data_i[17:16] No No No INPUT
data_i[22:18] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[24:23] No No No INPUT
data_i[28:25] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[29] No No No INPUT
data_i[30] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[32:31] No No No INPUT
data_i[36:33] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[37] No No No INPUT
data_i[38] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[41:39] No No No INPUT
data_i[44:42] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[46:45] No No No INPUT
data_i[48:47] Yes Yes T6,T7,T129 Yes T6,T7,T17 INPUT
data_i[49] No No No INPUT
data_i[51:50] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[53:52] No No No INPUT
data_i[54] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[56:55] No No No INPUT
data_i[59:57] Yes Yes T6,T7,T129 Yes T6,T7,T17 INPUT
data_i[60] No No No INPUT
data_i[62:61] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[64:63] No No No INPUT
data_i[71:65] Yes Yes T6,T13,T100 Yes T6,T13,T93 INPUT
data_o[0] Yes Yes *T6,*T7,*T17 Yes T6,T7,T17 OUTPUT
data_o[1] No No No OUTPUT
data_o[4:2] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[5] No No No OUTPUT
data_o[8:6] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[9] No No No OUTPUT
data_o[10] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[11] No No No OUTPUT
data_o[12] Yes Yes *T6,*T7,*T17 Yes T6,T7,T17 OUTPUT
data_o[13] No No No OUTPUT
data_o[15:14] Yes Yes T6,T7,T17 Yes T6,T7,T17 OUTPUT
data_o[17:16] No No No OUTPUT
data_o[22:18] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[24:23] No No No OUTPUT
data_o[28:25] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[29] No No No OUTPUT
data_o[30] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[32:31] No No No OUTPUT
data_o[36:33] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[37] No No No OUTPUT
data_o[38] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[41:39] No No No OUTPUT
data_o[44:42] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[46:45] No No No OUTPUT
data_o[48:47] Yes Yes T6,T7,T129 Yes T6,T7,T17 OUTPUT
data_o[49] No No No OUTPUT
data_o[51:50] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[53:52] No No No OUTPUT
data_o[54] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[56:55] No No No OUTPUT
data_o[59:57] Yes Yes T6,T7,T129 Yes T6,T7,T17 OUTPUT
data_o[60] No No No OUTPUT
data_o[62:61] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 176 64.71
Total Bits 0->1 136 88 64.71
Total Bits 1->0 136 88 64.71

Ports 2 0 0.00
Port Bits 272 176 64.71
Port Bits 0->1 136 88 64.71
Port Bits 1->0 136 88 64.71

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[1] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[2] No No No INPUT
data_i[5:3] Yes Yes T6,T129,T18 Yes T6,T17,T129 INPUT
data_i[6] No No No INPUT
data_i[12:7] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[14:13] No No No INPUT
data_i[15] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[16] No No No INPUT
data_i[18:17] Yes Yes T6,T129,T125 Yes T6,T17,T129 INPUT
data_i[19] No No No INPUT
data_i[20] Yes Yes *T6,*T129,*T125 Yes T6,T17,T129 INPUT
data_i[21] No No No INPUT
data_i[22] Yes Yes *T6,*T129,*T125 Yes T6,T17,T129 INPUT
data_i[24:23] No No No INPUT
data_i[25] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[26] No No No INPUT
data_i[27] Yes Yes *T6,*T129,*T125 Yes T6,T17,T129 INPUT
data_i[29:28] No No No INPUT
data_i[33:30] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[37:34] No No No INPUT
data_i[38] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[39] No No No INPUT
data_i[41:40] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[42] No No No INPUT
data_i[49:43] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[50] No No No INPUT
data_i[52:51] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[54:53] No No No INPUT
data_i[60:55] Yes Yes T125,T92,*T19 Yes T17,T125,T92 INPUT
data_i[61] No No No INPUT
data_i[62] Yes Yes *T125,*T92,*T19 Yes T17,T125,T92 INPUT
data_i[63] No No No INPUT
data_i[71:64] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_o[0] No No No OUTPUT
data_o[1] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[2] No No No OUTPUT
data_o[5:3] Yes Yes T6,T129,T18 Yes T6,T17,T129 OUTPUT
data_o[6] No No No OUTPUT
data_o[12:7] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[14:13] No No No OUTPUT
data_o[15] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[16] No No No OUTPUT
data_o[18:17] Yes Yes T6,T129,T125 Yes T6,T17,T129 OUTPUT
data_o[19] No No No OUTPUT
data_o[20] Yes Yes *T6,*T129,*T125 Yes T6,T17,T129 OUTPUT
data_o[21] No No No OUTPUT
data_o[22] Yes Yes *T6,*T129,*T125 Yes T6,T17,T129 OUTPUT
data_o[24:23] No No No OUTPUT
data_o[25] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[26] No No No OUTPUT
data_o[27] Yes Yes *T6,*T129,*T125 Yes T6,T17,T129 OUTPUT
data_o[29:28] No No No OUTPUT
data_o[33:30] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[37:34] No No No OUTPUT
data_o[38] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[39] No No No OUTPUT
data_o[41:40] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[42] No No No OUTPUT
data_o[49:43] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[50] No No No OUTPUT
data_o[52:51] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[54:53] No No No OUTPUT
data_o[60:55] Yes Yes T125,T92,*T19 Yes T17,T125,T92 OUTPUT
data_o[61] No No No OUTPUT
data_o[62] Yes Yes *T125,*T92,*T19 Yes T17,T125,T92 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 188 69.12
Total Bits 0->1 136 94 69.12
Total Bits 1->0 136 94 69.12

Ports 2 0 0.00
Port Bits 272 188 69.12
Port Bits 0->1 136 94 69.12
Port Bits 1->0 136 94 69.12

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[6:0] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[7] No No No INPUT
data_i[8] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[9] No No No INPUT
data_i[13:10] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[15:14] No No No INPUT
data_i[17:16] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[18] No No No INPUT
data_i[19] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[20] No No No INPUT
data_i[21] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[23:22] No No No INPUT
data_i[24] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[25] No No No INPUT
data_i[28:26] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[29] No No No INPUT
data_i[30] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[31] No No No INPUT
data_i[34:32] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[35] No No No INPUT
data_i[39:36] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[40] No No No INPUT
data_i[41] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[42] No No No INPUT
data_i[44:43] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[45] No No No INPUT
data_i[46] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[47] No No No INPUT
data_i[49:48] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[50] No No No INPUT
data_i[56:51] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[58:57] No No No INPUT
data_i[60:59] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[62:61] No No No INPUT
data_i[71:63] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_o[6:0] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[7] No No No OUTPUT
data_o[8] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[9] No No No OUTPUT
data_o[13:10] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[15:14] No No No OUTPUT
data_o[17:16] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[18] No No No OUTPUT
data_o[19] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[20] No No No OUTPUT
data_o[21] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[23:22] No No No OUTPUT
data_o[24] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[25] No No No OUTPUT
data_o[28:26] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[29] No No No OUTPUT
data_o[30] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[31] No No No OUTPUT
data_o[34:32] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[35] No No No OUTPUT
data_o[39:36] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[40] No No No OUTPUT
data_o[41] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[42] No No No OUTPUT
data_o[44:43] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[45] No No No OUTPUT
data_o[46] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[47] No No No OUTPUT
data_o[49:48] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[50] No No No OUTPUT
data_o[56:51] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[58:57] No No No OUTPUT
data_o[60:59] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[62:61] No No No OUTPUT
data_o[63] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 188 69.12
Total Bits 0->1 136 94 69.12
Total Bits 1->0 136 94 69.12

Ports 2 0 0.00
Port Bits 272 188 69.12
Port Bits 0->1 136 94 69.12
Port Bits 1->0 136 94 69.12

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[2] No No No INPUT
data_i[3] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[4] No No No INPUT
data_i[7:5] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[8] No No No INPUT
data_i[11:9] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[12] No No No INPUT
data_i[14:13] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[15] No No No INPUT
data_i[16] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[17] No No No INPUT
data_i[19:18] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[20] No No No INPUT
data_i[25:21] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[26] No No No INPUT
data_i[28:27] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[29] No No No INPUT
data_i[31:30] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[32] No No No INPUT
data_i[35:33] Yes Yes T6,T7,T17 Yes T6,T7,T17 INPUT
data_i[36] No No No INPUT
data_i[41:37] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[46:42] No No No INPUT
data_i[47] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[48] No No No INPUT
data_i[50:49] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[53:51] No No No INPUT
data_i[56:54] Yes Yes T6,T7,T17 Yes T6,T7,T17 INPUT
data_i[57] No No No INPUT
data_i[71:58] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_o[1:0] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[2] No No No OUTPUT
data_o[3] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[4] No No No OUTPUT
data_o[7:5] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[8] No No No OUTPUT
data_o[11:9] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[12] No No No OUTPUT
data_o[14:13] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[15] No No No OUTPUT
data_o[16] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[17] No No No OUTPUT
data_o[19:18] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[20] No No No OUTPUT
data_o[25:21] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[26] No No No OUTPUT
data_o[28:27] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[29] No No No OUTPUT
data_o[31:30] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[32] No No No OUTPUT
data_o[35:33] Yes Yes T6,T7,T17 Yes T6,T7,T17 OUTPUT
data_o[36] No No No OUTPUT
data_o[41:37] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[46:42] No No No OUTPUT
data_o[47] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[48] No No No OUTPUT
data_o[50:49] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[53:51] No No No OUTPUT
data_o[56:54] Yes Yes T6,T7,T17 Yes T6,T7,T17 OUTPUT
data_o[57] No No No OUTPUT
data_o[63:58] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 188 69.12
Total Bits 0->1 136 94 69.12
Total Bits 1->0 136 94 69.12

Ports 2 0 0.00
Port Bits 272 188 69.12
Port Bits 0->1 136 94 69.12
Port Bits 1->0 136 94 69.12

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T6,*T7,*T17 Yes T6,T7,T17 INPUT
data_i[1] No No No INPUT
data_i[3:2] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[4] No No No INPUT
data_i[7:5] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[8] No No No INPUT
data_i[11:9] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[12] No No No INPUT
data_i[16:13] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[17] No No No INPUT
data_i[18] Yes Yes *T6,*T7,*T93 Yes T6,T7,T17 INPUT
data_i[19] No No No INPUT
data_i[21:20] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[26:22] No No No INPUT
data_i[35:27] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[36] No No No INPUT
data_i[38:37] Yes Yes T6,T7,T93 Yes T6,T7,T17 INPUT
data_i[40:39] No No No INPUT
data_i[41] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[42] No No No INPUT
data_i[44:43] Yes Yes T6,T7,T93 Yes T6,T7,T17 INPUT
data_i[46:45] No No No INPUT
data_i[50:47] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[51] No No No INPUT
data_i[54:52] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[55] No No No INPUT
data_i[56] Yes Yes *T6,*T7,*T93 Yes T6,T7,T17 INPUT
data_i[57] No No No INPUT
data_i[62:58] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[63] No No No INPUT
data_i[71:64] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_o[0] Yes Yes *T6,*T7,*T17 Yes T6,T7,T17 OUTPUT
data_o[1] No No No OUTPUT
data_o[3:2] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[4] No No No OUTPUT
data_o[7:5] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[8] No No No OUTPUT
data_o[11:9] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[12] No No No OUTPUT
data_o[16:13] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[17] No No No OUTPUT
data_o[18] Yes Yes *T6,*T7,*T93 Yes T6,T7,T17 OUTPUT
data_o[19] No No No OUTPUT
data_o[21:20] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[26:22] No No No OUTPUT
data_o[35:27] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[36] No No No OUTPUT
data_o[38:37] Yes Yes T6,T7,T93 Yes T6,T7,T17 OUTPUT
data_o[40:39] No No No OUTPUT
data_o[41] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[42] No No No OUTPUT
data_o[44:43] Yes Yes T6,T7,T93 Yes T6,T7,T17 OUTPUT
data_o[46:45] No No No OUTPUT
data_o[50:47] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[51] No No No OUTPUT
data_o[54:52] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[55] No No No OUTPUT
data_o[56] Yes Yes *T6,*T7,*T93 Yes T6,T7,T17 OUTPUT
data_o[57] No No No OUTPUT
data_o[62:58] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 194 71.32
Total Bits 0->1 136 97 71.32
Total Bits 1->0 136 97 71.32

Ports 2 0 0.00
Port Bits 272 194 71.32
Port Bits 0->1 136 97 71.32
Port Bits 1->0 136 97 71.32

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[2:0] Yes Yes T6,T7,T93 Yes T6,T7,T17 INPUT
data_i[3] No No No INPUT
data_i[6:4] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[7] No No No INPUT
data_i[11:8] Yes Yes T6,T7,T93 Yes T6,T7,T17 INPUT
data_i[12] No No No INPUT
data_i[13] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[14] No No No INPUT
data_i[16:15] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[17] No No No INPUT
data_i[22:18] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[23] No No No INPUT
data_i[25:24] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[26] No No No INPUT
data_i[30:27] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[31] No No No INPUT
data_i[32] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[33] No No No INPUT
data_i[35:34] Yes Yes T6,T129,T18 Yes T6,T17,T129 INPUT
data_i[36] No No No INPUT
data_i[41:37] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[42] No No No INPUT
data_i[43] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[44] No No No INPUT
data_i[45] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[46] No No No INPUT
data_i[49:47] Yes Yes T6,T129,T18 Yes T6,T17,T129 INPUT
data_i[51:50] No No No INPUT
data_i[52] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[53] No No No INPUT
data_i[56:54] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[57] No No No INPUT
data_i[58] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[59] No No No INPUT
data_i[62:60] Yes Yes T6,T129,T18 Yes T6,T17,T129 INPUT
data_i[63] No No No INPUT
data_i[65:64] Yes Yes T6,T7,T93 Yes T6,T7,T17 INPUT
data_i[66] No No No INPUT
data_i[71:67] Yes Yes T6,T7,T17 Yes T6,T7,T93 INPUT
data_o[2:0] Yes Yes T6,T7,T93 Yes T6,T7,T17 OUTPUT
data_o[3] No No No OUTPUT
data_o[6:4] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[7] No No No OUTPUT
data_o[11:8] Yes Yes T6,T7,T93 Yes T6,T7,T17 OUTPUT
data_o[12] No No No OUTPUT
data_o[13] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[14] No No No OUTPUT
data_o[16:15] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[17] No No No OUTPUT
data_o[22:18] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[23] No No No OUTPUT
data_o[25:24] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[26] No No No OUTPUT
data_o[30:27] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[31] No No No OUTPUT
data_o[32] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[33] No No No OUTPUT
data_o[35:34] Yes Yes T6,T129,T18 Yes T6,T17,T129 OUTPUT
data_o[36] No No No OUTPUT
data_o[41:37] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[42] No No No OUTPUT
data_o[43] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[44] No No No OUTPUT
data_o[45] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[46] No No No OUTPUT
data_o[49:47] Yes Yes T6,T129,T18 Yes T6,T17,T129 OUTPUT
data_o[51:50] No No No OUTPUT
data_o[52] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[53] No No No OUTPUT
data_o[56:54] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[57] No No No OUTPUT
data_o[58] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[59] No No No OUTPUT
data_o[62:60] Yes Yes T6,T129,T18 Yes T6,T17,T129 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 204 75.00
Total Bits 0->1 136 102 75.00
Total Bits 1->0 136 102 75.00

Ports 2 0 0.00
Port Bits 272 204 75.00
Port Bits 0->1 136 102 75.00
Port Bits 1->0 136 102 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[2:1] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[3] No No No INPUT
data_i[6:4] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[7] No No No INPUT
data_i[9:8] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[10] No No No INPUT
data_i[16:11] Yes Yes T125,T92,*T19 Yes T17,T125,T92 INPUT
data_i[17] No No No INPUT
data_i[18] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[19] No No No INPUT
data_i[23:20] Yes Yes T125,T92,T19 Yes T125,T92,T19 INPUT
data_i[25:24] No No No INPUT
data_i[28:26] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[29] No No No INPUT
data_i[36:30] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[37] No No No INPUT
data_i[40:38] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[41] No No No INPUT
data_i[42] Yes Yes *T125,*T92,*T19 Yes T125,T92,T19 INPUT
data_i[43] No No No INPUT
data_i[48:44] Yes Yes T125,T92,*T19 Yes T125,T92,T19 INPUT
data_i[50:49] No No No INPUT
data_i[51] Yes Yes *T125,*T92,*T19 Yes T125,T92,T19 INPUT
data_i[52] No No No INPUT
data_i[56:53] Yes Yes T125,T92,*T19 Yes T125,T92,T19 INPUT
data_i[57] No No No INPUT
data_i[62:58] Yes Yes T125,T92,*T19 Yes T125,T92,T19 INPUT
data_i[63] No No No INPUT
data_i[71:64] Yes Yes T125,T92,T19 Yes T17,T125,T92 INPUT
data_o[0] No No No OUTPUT
data_o[2:1] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[3] No No No OUTPUT
data_o[6:4] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[7] No No No OUTPUT
data_o[9:8] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[10] No No No OUTPUT
data_o[16:11] Yes Yes T125,T92,*T19 Yes T17,T125,T92 OUTPUT
data_o[17] No No No OUTPUT
data_o[18] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[19] No No No OUTPUT
data_o[23:20] Yes Yes T125,T92,T19 Yes T125,T92,T19 OUTPUT
data_o[25:24] No No No OUTPUT
data_o[28:26] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[29] No No No OUTPUT
data_o[36:30] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[37] No No No OUTPUT
data_o[40:38] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[41] No No No OUTPUT
data_o[42] Yes Yes *T125,*T92,*T19 Yes T125,T92,T19 OUTPUT
data_o[43] No No No OUTPUT
data_o[48:44] Yes Yes T125,T92,*T19 Yes T125,T92,T19 OUTPUT
data_o[50:49] No No No OUTPUT
data_o[51] Yes Yes *T125,*T92,*T19 Yes T125,T92,T19 OUTPUT
data_o[52] No No No OUTPUT
data_o[56:53] Yes Yes T125,T92,*T19 Yes T125,T92,T19 OUTPUT
data_o[57] No No No OUTPUT
data_o[62:58] Yes Yes T125,T92,*T19 Yes T125,T92,T19 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 208 76.47
Total Bits 0->1 136 104 76.47
Total Bits 1->0 136 104 76.47

Ports 2 0 0.00
Port Bits 272 208 76.47
Port Bits 0->1 136 104 76.47
Port Bits 1->0 136 104 76.47

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[2:0] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[3] No No No INPUT
data_i[5:4] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[6] No No No INPUT
data_i[8:7] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[9] No No No INPUT
data_i[15:10] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[16] No No No INPUT
data_i[27:17] Yes Yes T6,T7,T129 Yes T6,T7,T17 INPUT
data_i[28] No No No INPUT
data_i[29] Yes Yes *T6,*T7,*T129 Yes T6,T7,T17 INPUT
data_i[33:30] No No No INPUT
data_i[42:34] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[43] No No No INPUT
data_i[47:44] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[50:48] No No No INPUT
data_i[56:51] Yes Yes T6,T7,T129 Yes T6,T7,T17 INPUT
data_i[57] No No No INPUT
data_i[59:58] Yes Yes T6,T7,T129 Yes T6,T7,T17 INPUT
data_i[60] No No No INPUT
data_i[61] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[62] No No No INPUT
data_i[71:63] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_o[2:0] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[3] No No No OUTPUT
data_o[5:4] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[6] No No No OUTPUT
data_o[8:7] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[9] No No No OUTPUT
data_o[15:10] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[16] No No No OUTPUT
data_o[27:17] Yes Yes T6,T7,T129 Yes T6,T7,T17 OUTPUT
data_o[28] No No No OUTPUT
data_o[29] Yes Yes *T6,*T7,*T129 Yes T6,T7,T17 OUTPUT
data_o[33:30] No No No OUTPUT
data_o[42:34] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[43] No No No OUTPUT
data_o[47:44] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[50:48] No No No OUTPUT
data_o[56:51] Yes Yes T6,T7,T129 Yes T6,T7,T17 OUTPUT
data_o[57] No No No OUTPUT
data_o[59:58] Yes Yes T6,T7,T129 Yes T6,T7,T17 OUTPUT
data_o[60] No No No OUTPUT
data_o[61] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[62] No No No OUTPUT
data_o[63] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 220 80.88
Total Bits 0->1 136 110 80.88
Total Bits 1->0 136 110 80.88

Ports 2 0 0.00
Port Bits 272 220 80.88
Port Bits 0->1 136 110 80.88
Port Bits 1->0 136 110 80.88

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T6,*T129,*T18 Yes T6,T17,T129 INPUT
data_i[3:1] No No No INPUT
data_i[9:4] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[10] No No No INPUT
data_i[19:11] Yes Yes T6,T129,T18 Yes T6,T17,T129 INPUT
data_i[20] No No No INPUT
data_i[21] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[22] No No No INPUT
data_i[24:23] Yes Yes T6,T129,T18 Yes T6,T17,T129 INPUT
data_i[25] No No No INPUT
data_i[27:26] Yes Yes *T26,*T6,*T7 Yes T26,T6,T7 INPUT
data_i[28] No No No INPUT
data_i[35:29] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[36] No No No INPUT
data_i[39:37] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[41:40] No No No INPUT
data_i[51:42] Yes Yes *T6,*T129,*T18 Yes T6,T17,T129 INPUT
data_i[52] No No No INPUT
data_i[53] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[54] No No No INPUT
data_i[71:55] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_o[0] Yes Yes *T6,*T129,*T18 Yes T6,T17,T129 OUTPUT
data_o[3:1] No No No OUTPUT
data_o[9:4] Yes Yes T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[10] No No No OUTPUT
data_o[19:11] Yes Yes T6,T129,T18 Yes T6,T17,T129 OUTPUT
data_o[20] No No No OUTPUT
data_o[21] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[22] No No No OUTPUT
data_o[24:23] Yes Yes T6,T129,T18 Yes T6,T17,T129 OUTPUT
data_o[25] No No No OUTPUT
data_o[27:26] Yes Yes *T26,*T6,*T7 Yes T26,T6,T7 OUTPUT
data_o[28] No No No OUTPUT
data_o[35:29] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[36] No No No OUTPUT
data_o[39:37] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[41:40] No No No OUTPUT
data_o[51:42] Yes Yes *T6,*T129,*T18 Yes T6,T17,T129 OUTPUT
data_o[52] No No No OUTPUT
data_o[53] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[54] No No No OUTPUT
data_o[63:55] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 228 83.82
Total Bits 0->1 136 114 83.82
Total Bits 1->0 136 114 83.82

Ports 2 0 0.00
Port Bits 272 228 83.82
Port Bits 0->1 136 114 83.82
Port Bits 1->0 136 114 83.82

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[2:1] No No No INPUT
data_i[6:3] Yes Yes T6,T7,T13 Yes T6,T7,T13 INPUT
data_i[7] No No No INPUT
data_i[18:8] Yes Yes *T293,*T6,*T7 Yes T293,T6,T7 INPUT
data_i[19] No No No INPUT
data_i[21:20] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[22] No No No INPUT
data_i[31:23] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[32] No No No INPUT
data_i[33] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[35:34] No No No INPUT
data_i[37:36] Yes Yes T6,T7,T17 Yes T6,T7,T17 INPUT
data_i[38] No No No INPUT
data_i[54:39] Yes Yes *T6,*T7,*T17 Yes T6,T7,T17 INPUT
data_i[56:55] No No No INPUT
data_i[71:57] Yes Yes T82,T293,T6 Yes T82,T293,T6 INPUT
data_o[0] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[2:1] No No No OUTPUT
data_o[6:3] Yes Yes T6,T7,T13 Yes T6,T7,T13 OUTPUT
data_o[7] No No No OUTPUT
data_o[18:8] Yes Yes *T293,*T6,*T7 Yes T293,T6,T7 OUTPUT
data_o[19] No No No OUTPUT
data_o[21:20] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[22] No No No OUTPUT
data_o[31:23] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[32] No No No OUTPUT
data_o[33] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[35:34] No No No OUTPUT
data_o[37:36] Yes Yes T6,T7,T17 Yes T6,T7,T17 OUTPUT
data_o[38] No No No OUTPUT
data_o[54:39] Yes Yes *T6,*T7,*T17 Yes T6,T7,T17 OUTPUT
data_o[56:55] No No No OUTPUT
data_o[63:57] Yes Yes T82,T293,T6 Yes T82,T293,T6 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 248 91.18
Total Bits 0->1 136 124 91.18
Total Bits 1->0 136 124 91.18

Ports 2 0 0.00
Port Bits 272 248 91.18
Port Bits 0->1 136 124 91.18
Port Bits 1->0 136 124 91.18

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[3:0] Yes Yes *T110,*T6,*T7 Yes T110,T6,T7 INPUT
data_i[4] No No No INPUT
data_i[6:5] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[7] No No No INPUT
data_i[33:8] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 INPUT
data_i[34] No No No INPUT
data_i[43:35] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[44] No No No INPUT
data_i[53:45] Yes Yes T6,T7,T17 Yes T6,T7,T17 INPUT
data_i[54] No No No INPUT
data_i[60:55] Yes Yes T6,T7,*T13 Yes T6,T7,T13 INPUT
data_i[61] No No No INPUT
data_i[71:62] Yes Yes T6,T7,T17 Yes T6,T7,T17 INPUT
data_o[3:0] Yes Yes *T110,*T6,*T7 Yes T110,T6,T7 OUTPUT
data_o[4] No No No OUTPUT
data_o[6:5] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[7] No No No OUTPUT
data_o[33:8] Yes Yes *T6,*T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[34] No No No OUTPUT
data_o[43:35] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[44] No No No OUTPUT
data_o[53:45] Yes Yes T6,T7,T17 Yes T6,T7,T17 OUTPUT
data_o[54] No No No OUTPUT
data_o[60:55] Yes Yes T6,T7,*T13 Yes T6,T7,T13 OUTPUT
data_o[61] No No No OUTPUT
data_o[63:62] Yes Yes T6,T7,T17 Yes T6,T7,T17 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T6,T17,T129 Yes T6,T12,T17 INPUT
data_o[63:0] Yes Yes T6,T17,T129 Yes T6,T12,T17 OUTPUT
syndrome_o[2:0] Yes Yes T109,T179,T180 Yes T109,T179,T180 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T109,*T179,*T180 Yes T109,T179,T180 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T17,T99,T101 Yes T17,T99,T101 INPUT
data_o[63:0] Yes Yes T17,T99,T101 Yes T17,T99,T101 OUTPUT
syndrome_o[2:0] Yes Yes T109,T180,T187 Yes T109,T180,T187 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T109,*T180,*T187 Yes T109,T180,T187 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T17,T19,T111 Yes T12,T17,T19 INPUT
data_o[63:0] Yes Yes T17,T19,T111 Yes T12,T17,T19 OUTPUT
syndrome_o[2:0] Yes Yes T107,T109,T180 Yes T107,T109,T180 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T107,*T109,*T180 Yes T107,T109,T180 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T92,T19,T111 Yes T92,T19,T111 INPUT
data_o[63:0] Yes Yes T92,T19,T111 Yes T92,T19,T111 OUTPUT
syndrome_o[2:0] Yes Yes T179,T198,T187 Yes T179,T198,T187 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T179,*T198,*T187 Yes T179,T198,T187 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T7,T125,T92 Yes T7,T125,T92 INPUT
data_o[63:0] Yes Yes T7,T125,T92 Yes T7,T125,T92 OUTPUT
syndrome_o[2:0] Yes Yes T109,T179,T198 Yes T109,T179,T198 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T109,*T179,*T198 Yes T109,T179,T198 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T60,T77,T294 Yes T60,T77,T294 INPUT
data_o[63:0] Yes Yes T60,T77,T294 Yes T60,T77,T294 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T13,T92,T145 Yes T13,T92,T145 INPUT
data_o[63:0] Yes Yes T13,T92,T145 Yes T13,T92,T145 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T112,T239,T256 Yes T112,T295,T239 INPUT
data_o[63:0] Yes Yes T112,T239,T256 Yes T112,T295,T239 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T92,T115,T122 Yes T92,T115,T122 INPUT
data_o[63:0] Yes Yes T92,T115,T122 Yes T92,T115,T122 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T129,T92 Yes T2,T129,T92 INPUT
data_o[63:0] Yes Yes T2,T129,T92 Yes T2,T129,T92 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T117,T118 Yes T2,T117,T118 INPUT
data_o[63:0] Yes Yes T2,T117,T118 Yes T2,T117,T118 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T127,T106,T176 Yes T127,T106,T176 INPUT
data_o[63:0] Yes Yes T127,T106,T176 Yes T127,T106,T176 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T259,T74 Yes T2,T12,T259 INPUT
data_o[63:0] Yes Yes T2,T259,T74 Yes T2,T12,T259 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
data_o[63:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T2,T3,T6 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T2,T3,T6 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T93,T129,T130 Yes T12,T94,T93 INPUT
data_o[63:0] Yes Yes T93,T129,T130 Yes T12,T94,T93 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T18,T126,T92 Yes T12,T18,T126 INPUT
data_o[63:0] Yes Yes T18,T126,T92 Yes T12,T18,T126 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T130,T114 Yes T2,T130,T114 INPUT
data_o[63:0] Yes Yes T2,T130,T114 Yes T2,T130,T114 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T130,T111 Yes T3,T130,T111 INPUT
data_o[63:0] Yes Yes T3,T130,T111 Yes T3,T130,T111 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T129 Yes T2,T3,T129 INPUT
data_o[63:0] Yes Yes T2,T3,T129 Yes T2,T3,T129 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T129,T18,T106 Yes T129,T18,T106 INPUT
data_o[63:0] Yes Yes T129,T18,T106 Yes T129,T18,T106 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T18,T127 Yes T3,T12,T18 INPUT
data_o[63:0] Yes Yes T3,T18,T127 Yes T3,T12,T18 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T92,T101 Yes T2,T12,T92 INPUT
data_o[63:0] Yes Yes T2,T92,T101 Yes T2,T12,T92 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T176,T96,T202 Yes T176,T96,T202 INPUT
data_o[63:0] Yes Yes T176,T96,T202 Yes T176,T96,T202 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T127,T176,T120 Yes T12,T127,T176 INPUT
data_o[63:0] Yes Yes T127,T176,T120 Yes T12,T127,T176 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T130,T111,T155 Yes T130,T111,T155 INPUT
data_o[63:0] Yes Yes T130,T111,T155 Yes T130,T111,T155 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T126,T145 Yes T3,T126,T145 INPUT
data_o[63:0] Yes Yes T3,T126,T145 Yes T3,T126,T145 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T92,T111,T118 Yes T92,T111,T118 INPUT
data_o[63:0] Yes Yes T92,T111,T118 Yes T92,T111,T118 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T94,T18,T92 Yes T94,T129,T18 INPUT
data_o[63:0] Yes Yes T94,T18,T92 Yes T94,T129,T18 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T93,T130,T92 Yes T93,T130,T92 INPUT
data_o[63:0] Yes Yes T93,T130,T92 Yes T93,T130,T92 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T6,T7 Yes T3,T6,T7 INPUT
data_o[63:0] Yes Yes T3,T6,T7 Yes T3,T6,T7 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T93,T116 Yes T12,T93,T116 INPUT
data_o[63:0] Yes Yes T12,T93,T116 Yes T12,T93,T116 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T94,T92,T82 Yes T94,T92,T82 INPUT
data_o[63:0] Yes Yes T94,T92,T82 Yes T94,T92,T82 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T115,T296,T295 Yes T115,T296,T295 INPUT
data_o[63:0] Yes Yes T115,T296,T295 Yes T115,T296,T295 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T130,T126,T112 Yes T130,T126,T112 INPUT
data_o[63:0] Yes Yes T130,T126,T112 Yes T130,T126,T112 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T130,T92 Yes T3,T130,T92 INPUT
data_o[63:0] Yes Yes T3,T130,T92 Yes T3,T130,T92 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T130,T92,T114 Yes T130,T92,T114 INPUT
data_o[63:0] Yes Yes T130,T92,T114 Yes T130,T92,T114 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T101,T115,T141 Yes T101,T115,T141 INPUT
data_o[63:0] Yes Yes T101,T115,T141 Yes T101,T115,T141 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T93,T112 Yes T3,T93,T130 INPUT
data_o[63:0] Yes Yes T3,T93,T112 Yes T3,T93,T130 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T94,T130,T18 Yes T94,T130,T18 INPUT
data_o[63:0] Yes Yes T94,T130,T18 Yes T94,T130,T18 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T101,T176,T120 Yes T101,T176,T120 INPUT
data_o[63:0] Yes Yes T101,T176,T120 Yes T101,T176,T120 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T127,T19,T111 Yes T13,T93,T127 INPUT
data_o[63:0] Yes Yes T127,T19,T111 Yes T13,T93,T127 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%