Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5257367

1

T1

12

T2

290

T3

556

full_word

2537542

1

T1

7

T2

166

T3

289

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7794609	1			T1	19		T2	456		T3	845
auto[TlIntgErrCmd]	86	1			T278	8		T279	1		T280	2
auto[TlIntgErrData]	109	1			T278	7		T279	5		T280	5
auto[TlIntgErrBoth]	105	1			T278	5		T279	4		T280	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5854481

1

T1

4

T2

275

T3

749

auto[1]

1940428

1

T1

15

T2

181

T3

96

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3884105	1			T1	4		T2	205		T3	492
auto[TlIntgErrNone]	partial	auto[1]	1372990	1			T1	8		T2	85		T3	64
auto[TlIntgErrNone]	full_word	auto[0]	1970238	1			T2	70		T3	257		T4	402
auto[TlIntgErrNone]	full_word	auto[1]	567276	1			T1	7		T2	96		T3	32
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T278	2		T280	2		T286	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T278	6		T279	1		T286	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T369	1		T367	1		T370	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T363	1		T366	2		-	-
auto[TlIntgErrData]	partial	auto[0]	52	1			T278	5		T279	1		T280	4
auto[TlIntgErrData]	partial	auto[1]	49	1			T278	1		T279	4		T280	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T363	1		T371	1		T372	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T278	1		T369	1		T373	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T278	1		T279	1		T286	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T278	3		T279	3		T280	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T278	1		T369	1		T368	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T280	1		T374	1		T372	1