Unified Coverage Report :: Module :: prim_secded_inv_72_64_dec

Module : prim_secded_inv_72_64_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	72.06			72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	72.06			72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	72.79			72.79
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	73.53			73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	74.26			74.26
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	75.74			75.74
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	76.47			76.47
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	76.47			76.47
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	77.21			77.21
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	83.82			83.82
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	89.71			89.71
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.79			72.79

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.79			72.79

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.26			74.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.26			74.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.74			75.74

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.74			75.74

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.47			76.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.47			76.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.47			76.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.47			76.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.21			77.21

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.21			77.21

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.82			83.82

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.82			83.82

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.71			89.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.71			89.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T4,T12,T13	Yes	T4,T12,T13	INPUT
data_o[63:0]	Yes	Yes	T4,T12,T13	Yes	T4,T12,T13	OUTPUT
syndrome_o[2:0]	Yes	Yes	T109,T110,T164	Yes	T109,T110,T164	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T109,*T110,*T164	Yes	T109,T110,T164	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	196	72.06
Total Bits 0->1	136	98	72.06
Total Bits 1->0	136	98	72.06

Ports	2	0	0.00
Port Bits	272	196	72.06
Port Bits 0->1	136	98	72.06
Port Bits 1->0	136	98	72.06

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	No	No		No		INPUT
data_i[3:2]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[4]	No	No		No		INPUT
data_i[6:5]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[9]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[10]	No	No		No		INPUT
data_i[16:11]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[17]	No	No		No		INPUT
data_i[18]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[19]	No	No		No		INPUT
data_i[21:20]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[23:22]	No	No		No		INPUT
data_i[25:24]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[26]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[29]	No	No		No		INPUT
data_i[34:30]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[35]	No	No		No		INPUT
data_i[40:36]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[41]	No	No		No		INPUT
data_i[42]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[43]	No	No		No		INPUT
data_i[45:44]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[46]	No	No		No		INPUT
data_i[52:47]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[53]	No	No		No		INPUT
data_i[57:54]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[58]	No	No		No		INPUT
data_i[59]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[60]	No	No		No		INPUT
data_i[71:61]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_o[1:0]	No	No		No		OUTPUT
data_o[3:2]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[6:5]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[9]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[16:11]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[18]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[21:20]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[23:22]	No	No		No		OUTPUT
data_o[25:24]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[34:30]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[40:36]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[42]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[45:44]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[52:47]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[57:54]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[59]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[63:61]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	196	72.06
Total Bits 0->1	136	98	72.06
Total Bits 1->0	136	98	72.06

Ports	2	0	0.00
Port Bits	272	196	72.06
Port Bits 0->1	136	98	72.06
Port Bits 1->0	136	98	72.06

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	Yes	Yes	*T271,*T12,*T13	Yes	T271,T12,T13	INPUT
data_i[3:2]	No	No		No		INPUT
data_i[5:4]	Yes	Yes	*T113,*T12,*T17	Yes	T113,T12,T17	INPUT
data_i[6]	No	No		No		INPUT
data_i[11:7]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[12]	No	No		No		INPUT
data_i[13]	Yes	Yes	*T113	Yes	T113	INPUT
data_i[14]	No	No		No		INPUT
data_i[16:15]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[17]	No	No		No		INPUT
data_i[18]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[19]	No	No		No		INPUT
data_i[21:20]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_i[25:22]	No	No		No		INPUT
data_i[28:26]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[31]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	INPUT
data_i[32]	No	No		No		INPUT
data_i[37:33]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[39:38]	No	No		No		INPUT
data_i[42:40]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_i[43]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_i[47]	No	No		No		INPUT
data_i[60:48]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_o[1:0]	Yes	Yes	*T271,*T12,*T13	Yes	T271,T12,T13	OUTPUT
data_o[3:2]	No	No		No		OUTPUT
data_o[5:4]	Yes	Yes	*T113,*T12,*T17	Yes	T113,T12,T17	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[11:7]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[12]	No	No		No		OUTPUT
data_o[13]	Yes	Yes	*T113	Yes	T113	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[16:15]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[18]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[21:20]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
data_o[25:22]	No	No		No		OUTPUT
data_o[28:26]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[31]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[37:33]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[39:38]	No	No		No		OUTPUT
data_o[42:40]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[60:48]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	198	72.79
Total Bits 0->1	136	99	72.79
Total Bits 1->0	136	99	72.79

Ports	2	0	0.00
Port Bits	272	198	72.79
Port Bits 0->1	136	99	72.79
Port Bits 1->0	136	99	72.79

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[3:1]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[4]	No	No		No		INPUT
data_i[5]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[7:6]	No	No		No		INPUT
data_i[15:8]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[17:16]	No	No		No		INPUT
data_i[21:18]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[23:22]	No	No		No		INPUT
data_i[27:24]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[28]	No	No		No		INPUT
data_i[38:29]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[40:39]	No	No		No		INPUT
data_i[44:41]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[45]	No	No		No		INPUT
data_i[50:46]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_i[51]	No	No		No		INPUT
data_i[52]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[54:53]	No	No		No		INPUT
data_i[55]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[56]	No	No		No		INPUT
data_i[57]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	INPUT
data_i[58]	No	No		No		INPUT
data_i[61:59]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_i[62]	No	No		No		INPUT
data_i[69:63]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[70]	No	No		No		INPUT
data_i[71]	Yes	Yes	T12,T17,T97	Yes	T12,T17,T98	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[3:1]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[5]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[7:6]	No	No		No		OUTPUT
data_o[15:8]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[17:16]	No	No		No		OUTPUT
data_o[21:18]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[23:22]	No	No		No		OUTPUT
data_o[27:24]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[38:29]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[40:39]	No	No		No		OUTPUT
data_o[44:41]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[45]	No	No		No		OUTPUT
data_o[50:46]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
data_o[51]	No	No		No		OUTPUT
data_o[52]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[54:53]	No	No		No		OUTPUT
data_o[55]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[57]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[61:59]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
data_o[62]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	200	73.53
Total Bits 0->1	136	100	73.53
Total Bits 1->0	136	100	73.53

Ports	2	0	0.00
Port Bits	272	200	73.53
Port Bits 0->1	136	100	73.53
Port Bits 1->0	136	100	73.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[7:1]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	INPUT
data_i[8]	No	No		No		INPUT
data_i[12:9]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[13]	No	No		No		INPUT
data_i[18:14]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[19]	No	No		No		INPUT
data_i[21:20]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[22]	No	No		No		INPUT
data_i[24:23]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[25]	No	No		No		INPUT
data_i[27:26]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_i[29:28]	No	No		No		INPUT
data_i[32:30]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[33]	No	No		No		INPUT
data_i[34]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	INPUT
data_i[35]	No	No		No		INPUT
data_i[45:36]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_i[47:46]	No	No		No		INPUT
data_i[49:48]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[50]	No	No		No		INPUT
data_i[51]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[53:52]	No	No		No		INPUT
data_i[56:54]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[59:57]	No	No		No		INPUT
data_i[71:60]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[7:1]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[12:9]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[18:14]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[21:20]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[24:23]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[27:26]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
data_o[29:28]	No	No		No		OUTPUT
data_o[32:30]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[34]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[45:36]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
data_o[47:46]	No	No		No		OUTPUT
data_o[49:48]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[51]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[53:52]	No	No		No		OUTPUT
data_o[56:54]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[59:57]	No	No		No		OUTPUT
data_o[63:60]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	202	74.26
Total Bits 0->1	136	101	74.26
Total Bits 1->0	136	101	74.26

Ports	2	0	0.00
Port Bits	272	202	74.26
Port Bits 0->1	136	101	74.26
Port Bits 1->0	136	101	74.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[1]	No	No		No		INPUT
data_i[3:2]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[4]	No	No		No		INPUT
data_i[5]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T98	INPUT
data_i[6]	No	No		No		INPUT
data_i[13:7]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[14]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[16]	No	No		No		INPUT
data_i[17]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T98	INPUT
data_i[18]	No	No		No		INPUT
data_i[20:19]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[22:21]	No	No		No		INPUT
data_i[26:23]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T98	INPUT
data_i[27]	No	No		No		INPUT
data_i[29:28]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[30]	No	No		No		INPUT
data_i[36:31]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[39:37]	No	No		No		INPUT
data_i[47:40]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[49:48]	No	No		No		INPUT
data_i[58:50]	Yes	Yes	*T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[60:59]	No	No		No		INPUT
data_i[65:61]	Yes	Yes	*T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[66]	No	No		No		INPUT
data_i[71:67]	Yes	Yes	T13,T17,T97	Yes	T13,T17,T98	INPUT
data_o[0]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[3:2]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[5]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T98	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[13:7]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[17]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T98	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[20:19]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[22:21]	No	No		No		OUTPUT
data_o[26:23]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T98	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[29:28]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[36:31]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[39:37]	No	No		No		OUTPUT
data_o[47:40]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[49:48]	No	No		No		OUTPUT
data_o[58:50]	Yes	Yes	*T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[60:59]	No	No		No		OUTPUT
data_o[63:61]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	206	75.74
Total Bits 0->1	136	103	75.74
Total Bits 1->0	136	103	75.74

Ports	2	0	0.00
Port Bits	272	206	75.74
Port Bits 0->1	136	103	75.74
Port Bits 1->0	136	103	75.74

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[6:0]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_i[7]	No	No		No		INPUT
data_i[13:8]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[15:14]	No	No		No		INPUT
data_i[22:16]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[24:23]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[26]	No	No		No		INPUT
data_i[27]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	INPUT
data_i[28]	No	No		No		INPUT
data_i[29]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[30]	No	No		No		INPUT
data_i[34:31]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[35]	No	No		No		INPUT
data_i[36]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	INPUT
data_i[37]	No	No		No		INPUT
data_i[39:38]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_i[40]	No	No		No		INPUT
data_i[46:41]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[47]	No	No		No		INPUT
data_i[53:48]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[54]	No	No		No		INPUT
data_i[55]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[56]	No	No		No		INPUT
data_i[61:57]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_i[63:62]	No	No		No		INPUT
data_i[67:64]	Yes	Yes	*T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[68]	No	No		No		INPUT
data_i[71:69]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_o[6:0]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[13:8]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[15:14]	No	No		No		OUTPUT
data_o[22:16]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[24:23]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[27]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[29]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[34:31]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[36]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[39:38]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[46:41]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[53:48]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[55]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[61:57]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
data_o[63:62]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	208	76.47
Total Bits 0->1	136	104	76.47
Total Bits 1->0	136	104	76.47

Ports	2	0	0.00
Port Bits	272	208	76.47
Port Bits 0->1	136	104	76.47
Port Bits 1->0	136	104	76.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[4:1]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[5]	No	No		No		INPUT
data_i[7:6]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[8]	No	No		No		INPUT
data_i[9]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[10]	No	No		No		INPUT
data_i[12:11]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[13]	No	No		No		INPUT
data_i[14]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[15]	No	No		No		INPUT
data_i[25:16]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[28:26]	No	No		No		INPUT
data_i[32:29]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[34:33]	No	No		No		INPUT
data_i[37:35]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[38]	No	No		No		INPUT
data_i[43:39]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[45:44]	No	No		No		INPUT
data_i[51:46]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[52]	No	No		No		INPUT
data_i[58:53]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[59]	No	No		No		INPUT
data_i[71:60]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[4:1]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[7:6]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[9]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[12:11]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[14]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[25:16]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[28:26]	No	No		No		OUTPUT
data_o[32:29]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[34:33]	No	No		No		OUTPUT
data_o[37:35]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[43:39]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[45:44]	No	No		No		OUTPUT
data_o[51:46]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[58:53]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[59]	No	No		No		OUTPUT
data_o[63:60]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	208	76.47
Total Bits 0->1	136	104	76.47
Total Bits 1->0	136	104	76.47

Ports	2	0	0.00
Port Bits	272	208	76.47
Port Bits 0->1	136	104	76.47
Port Bits 1->0	136	104	76.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[5:0]	Yes	Yes	T12,T13,*T17	Yes	T12,T13,T17	INPUT
data_i[6]	No	No		No		INPUT
data_i[9:7]	Yes	Yes	T12,T13,*T17	Yes	T12,T13,T17	INPUT
data_i[10]	No	No		No		INPUT
data_i[14:11]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[15]	No	No		No		INPUT
data_i[16]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[19:17]	No	No		No		INPUT
data_i[21:20]	Yes	Yes	T12,T13,T93	Yes	T12,T13,T93	INPUT
data_i[22]	No	No		No		INPUT
data_i[24:23]	Yes	Yes	T12,T13,T93	Yes	T12,T13,T93	INPUT
data_i[25]	No	No		No		INPUT
data_i[32:26]	Yes	Yes	T12,T13,T93	Yes	T12,T13,T93	INPUT
data_i[33]	No	No		No		INPUT
data_i[37:34]	Yes	Yes	T12,T13,T93	Yes	T12,T13,T93	INPUT
data_i[38]	No	No		No		INPUT
data_i[40:39]	Yes	Yes	T12,T13,T93	Yes	T12,T13,T93	INPUT
data_i[41]	No	No		No		INPUT
data_i[46:42]	Yes	Yes	T12,T13,*T17	Yes	T12,T13,T17	INPUT
data_i[47]	No	No		No		INPUT
data_i[56:48]	Yes	Yes	T12,T13,*T17	Yes	T12,T13,T17	INPUT
data_i[58:57]	No	No		No		INPUT
data_i[59]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[61:60]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T12,T13,T93	Yes	T12,T13,T93	INPUT
data_o[5:0]	Yes	Yes	T12,T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[9:7]	Yes	Yes	T12,T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[14:11]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[16]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[19:17]	No	No		No		OUTPUT
data_o[21:20]	Yes	Yes	T12,T13,T93	Yes	T12,T13,T93	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[24:23]	Yes	Yes	T12,T13,T93	Yes	T12,T13,T93	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[32:26]	Yes	Yes	T12,T13,T93	Yes	T12,T13,T93	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[37:34]	Yes	Yes	T12,T13,T93	Yes	T12,T13,T93	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[40:39]	Yes	Yes	T12,T13,T93	Yes	T12,T13,T93	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[46:42]	Yes	Yes	T12,T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[56:48]	Yes	Yes	T12,T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[58:57]	No	No		No		OUTPUT
data_o[59]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[61:60]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T12,T13,T93	Yes	T12,T13,T93	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	210	77.21
Total Bits 0->1	136	105	77.21
Total Bits 1->0	136	105	77.21

Ports	2	0	0.00
Port Bits	272	210	77.21
Port Bits 0->1	136	105	77.21
Port Bits 1->0	136	105	77.21

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[1]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	INPUT
data_i[2]	No	No		No		INPUT
data_i[4:3]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[5]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[7]	No	No		No		INPUT
data_i[8]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[9]	No	No		No		INPUT
data_i[13:10]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_i[14]	No	No		No		INPUT
data_i[18:15]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	INPUT
data_i[19]	No	No		No		INPUT
data_i[21:20]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[22]	No	No		No		INPUT
data_i[31:23]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_i[32]	No	No		No		INPUT
data_i[46:33]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_i[49:47]	No	No		No		INPUT
data_i[53:50]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_i[54]	No	No		No		INPUT
data_i[55]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	INPUT
data_i[56]	No	No		No		INPUT
data_i[57]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[58]	No	No		No		INPUT
data_i[68:59]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	INPUT
data_i[69]	No	No		No		INPUT
data_i[71:70]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[1]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[4:3]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[8]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[13:10]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[18:15]	Yes	Yes	T12,*T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[21:20]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[31:23]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[46:33]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
data_o[49:47]	No	No		No		OUTPUT
data_o[53:50]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[55]	Yes	Yes	*T12,*T17,*T98	Yes	T12,T17,T97	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[57]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[63:59]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T97	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	228	83.82
Total Bits 0->1	136	114	83.82
Total Bits 1->0	136	114	83.82

Ports	2	0	0.00
Port Bits	272	228	83.82
Port Bits 0->1	136	114	83.82
Port Bits 1->0	136	114	83.82

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[2:1]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[3]	No	No		No		INPUT
data_i[6:4]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[7]	No	No		No		INPUT
data_i[24:8]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[25]	No	No		No		INPUT
data_i[30:26]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[31]	No	No		No		INPUT
data_i[34:32]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[35]	No	No		No		INPUT
data_i[39:36]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[42:40]	No	No		No		INPUT
data_i[49:43]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[50]	No	No		No		INPUT
data_i[55:51]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[56]	No	No		No		INPUT
data_i[71:57]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[2:1]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[6:4]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[24:8]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[30:26]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[34:32]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[39:36]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[42:40]	No	No		No		OUTPUT
data_o[49:43]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[55:51]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[63:57]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	244	89.71
Total Bits 0->1	136	122	89.71
Total Bits 1->0	136	122	89.71

Ports	2	0	0.00
Port Bits	272	244	89.71
Port Bits 0->1	136	122	89.71
Port Bits 1->0	136	122	89.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[2]	No	No		No		INPUT
data_i[3]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[4]	No	No		No		INPUT
data_i[8:5]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[9]	No	No		No		INPUT
data_i[11:10]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[12]	No	No		No		INPUT
data_i[17:13]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	INPUT
data_i[18]	No	No		No		INPUT
data_i[47:19]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[48]	No	No		No		INPUT
data_i[58:49]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	INPUT
data_i[59]	No	No		No		INPUT
data_i[71:60]	Yes	Yes	T272,T12,T13	Yes	T272,T12,T13	INPUT
data_o[1:0]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[3]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[8:5]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[11:10]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[12]	No	No		No		OUTPUT
data_o[17:13]	Yes	Yes	T12,T13,T17	Yes	T12,T13,T17	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[47:19]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[58:49]	Yes	Yes	*T12,*T13,*T17	Yes	T12,T13,T17	OUTPUT
data_o[59]	No	No		No		OUTPUT
data_o[63:60]	Yes	Yes	T272,T12,T13	Yes	T272,T12,T13	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T98	INPUT
data_o[63:0]	Yes	Yes	T12,T17,T98	Yes	T12,T17,T98	OUTPUT
syndrome_o[2:0]	Yes	Yes	T109,T152	Yes	T109,T152	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T109,*T152	Yes	T109,T152	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T4,T17,T93	Yes	T4,T17,T93	INPUT
data_o[63:0]	Yes	Yes	T4,T17,T93	Yes	T4,T17,T93	OUTPUT
syndrome_o[2:0]	Yes	Yes	T109,T110	Yes	T109,T110	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T109,*T110	Yes	T109,T110	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T13,T93,T102	Yes	T13,T93,T102	INPUT
data_o[63:0]	Yes	Yes	T13,T93,T102	Yes	T13,T93,T102	OUTPUT
syndrome_o[2:0]	Yes	Yes	T109,T164,T152	Yes	T109,T164,T152	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T109,*T164,*T152	Yes	T109,T164,T152	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T4,T17,T102	Yes	T4,T17,T102	INPUT
data_o[63:0]	Yes	Yes	T4,T17,T102	Yes	T4,T17,T102	OUTPUT
syndrome_o[2:0]	Yes	Yes	T109	Yes	T109	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T109	Yes	T109	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T19,T120,T125	Yes	T19,T120,T125	INPUT
data_o[63:0]	Yes	Yes	T19,T120,T125	Yes	T19,T120,T125	OUTPUT
syndrome_o[2:0]	Yes	Yes	T109,T164	Yes	T109,T164	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T109,*T164	Yes	T109,T164	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T93,T123,T125	Yes	T93,T123,T125	INPUT
data_o[63:0]	Yes	Yes	T93,T123,T125	Yes	T93,T123,T125	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T122,T149,T99	Yes	T122,T273,T149	INPUT
data_o[63:0]	Yes	Yes	T122,T149,T99	Yes	T122,T273,T149	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T122,T123,T33	Yes	T122,T123,T33	INPUT
data_o[63:0]	Yes	Yes	T122,T123,T33	Yes	T122,T123,T33	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T123,T99,T192	Yes	T123,T99,T192	INPUT
data_o[63:0]	Yes	Yes	T123,T99,T192	Yes	T123,T99,T192	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T40,T52,T192	Yes	T40,T52,T192	INPUT
data_o[63:0]	Yes	Yes	T40,T52,T192	Yes	T40,T52,T192	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T192,T34,T246	Yes	T192,T34,T246	INPUT
data_o[63:0]	Yes	Yes	T192,T34,T246	Yes	T192,T34,T246	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T123,T100,T243	Yes	T123,T100,T243	INPUT
data_o[63:0]	Yes	Yes	T123,T100,T243	Yes	T123,T100,T243	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T123,T192,T274	Yes	T123,T151,T275	INPUT
data_o[63:0]	Yes	Yes	T123,T192,T274	Yes	T123,T151,T275	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T93,T120,T122	Yes	T93,T102,T120	INPUT
data_o[63:0]	Yes	Yes	T93,T120,T122	Yes	T93,T102,T120	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T4,T97,T128	Yes	T4,T6,T97	INPUT
data_o[63:0]	Yes	Yes	T4,T97,T128	Yes	T4,T6,T97	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T17,T97	Yes	T3,T17,T97	INPUT
data_o[63:0]	Yes	Yes	T3,T17,T97	Yes	T3,T17,T97	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T116,T120,T125	Yes	T116,T120,T125	INPUT
data_o[63:0]	Yes	Yes	T116,T120,T125	Yes	T116,T120,T125	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T6,T13,T97	Yes	T6,T13,T97	INPUT
data_o[63:0]	Yes	Yes	T6,T13,T97	Yes	T6,T13,T97	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T13,T19,T120	Yes	T13,T19,T120	INPUT
data_o[63:0]	Yes	Yes	T13,T19,T120	Yes	T13,T19,T120	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T6,T12	Yes	T3,T6,T12	INPUT
data_o[63:0]	Yes	Yes	T3,T6,T12	Yes	T3,T6,T12	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T12,T17,T97	Yes	T6,T12,T17	INPUT
data_o[63:0]	Yes	Yes	T12,T17,T97	Yes	T6,T12,T17	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T37,T126	Yes	T3,T37,T126	INPUT
data_o[63:0]	Yes	Yes	T3,T37,T126	Yes	T3,T37,T126	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T13,T242,T133	Yes	T13,T242,T133	INPUT
data_o[63:0]	Yes	Yes	T13,T242,T133	Yes	T13,T242,T133	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T12,T201,T20	Yes	T6,T12,T98	INPUT
data_o[63:0]	Yes	Yes	T12,T201,T20	Yes	T6,T12,T98	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T91,T132	Yes	T3,T91,T132	INPUT
data_o[63:0]	Yes	Yes	T3,T91,T132	Yes	T3,T91,T132	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T12,T119,T120	Yes	T12,T119,T120	INPUT
data_o[63:0]	Yes	Yes	T12,T119,T120	Yes	T12,T119,T120	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T12,T97,T120	Yes	T12,T97,T120	INPUT
data_o[63:0]	Yes	Yes	T12,T97,T120	Yes	T12,T97,T120	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T125,T243,T276	Yes	T125,T135,T243	INPUT
data_o[63:0]	Yes	Yes	T125,T243,T276	Yes	T125,T135,T243	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T97,T120,T149	Yes	T97,T120,T149	INPUT
data_o[63:0]	Yes	Yes	T97,T120,T149	Yes	T97,T120,T149	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T12,T19,T120	Yes	T12,T37,T19	INPUT
data_o[63:0]	Yes	Yes	T12,T19,T120	Yes	T12,T37,T19	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T12,T201	Yes	T3,T6,T12	INPUT
data_o[63:0]	Yes	Yes	T3,T12,T201	Yes	T3,T6,T12	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T19,T120	Yes	T3,T19,T120	INPUT
data_o[63:0]	Yes	Yes	T3,T19,T120	Yes	T3,T19,T120	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T13,T122,T124	Yes	T13,T98,T37	INPUT
data_o[63:0]	Yes	Yes	T13,T122,T124	Yes	T13,T98,T37	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR