Unified Coverage Report :: Module :: prim_secded_inv_72_64_dec

Module : prim_secded_inv_72_64_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	64.71			64.71
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	69.85			69.85
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	71.32			71.32
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	72.06			72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	72.79			72.79
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	73.53			73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	73.53			73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	74.26			74.26
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	75.00			75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	76.47			76.47
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	94.12			94.12
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	97.14			97.14
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.71			64.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.71			64.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.85			69.85

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.85			69.85

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.32			71.32

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.32			71.32

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.79			72.79

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.79			72.79

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.26			74.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.26			74.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.47			76.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.47			76.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12			94.12

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12			94.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T4,T11,T18	Yes	T4,T11,T12	INPUT
data_o[63:0]	Yes	Yes	T4,T11,T18	Yes	T4,T11,T12	OUTPUT
syndrome_o[2:0]	Yes	Yes	T97,T154,T155	Yes	T97,T154,T155	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T97,*T154,*T155	Yes	T97,T154,T155	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	176	64.71
Total Bits 0->1	136	88	64.71
Total Bits 1->0	136	88	64.71

Ports	2	0	0.00
Port Bits	272	176	64.71
Port Bits 0->1	136	88	64.71
Port Bits 1->0	136	88	64.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T4,*T13,*T18	Yes	T2,T4,T11	INPUT
data_i[1]	No	No		No		INPUT
data_i[4:2]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[5]	No	No		No		INPUT
data_i[7:6]	Yes	Yes	T4,T13,T18	Yes	T2,T4,T11	INPUT
data_i[8]	No	No		No		INPUT
data_i[12:9]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	INPUT
data_i[14:13]	No	No		No		INPUT
data_i[17:15]	Yes	Yes	T4,T13,T18	Yes	T2,T4,T11	INPUT
data_i[19:18]	No	No		No		INPUT
data_i[24:20]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	INPUT
data_i[26:25]	No	No		No		INPUT
data_i[27]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[29:28]	No	No		No		INPUT
data_i[33:30]	Yes	Yes	T4,T13,T18	Yes	T2,T4,T11	INPUT
data_i[37:34]	No	No		No		INPUT
data_i[42:38]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	INPUT
data_i[43]	No	No		No		INPUT
data_i[44]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[48:45]	No	No		No		INPUT
data_i[54:49]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	INPUT
data_i[56:55]	No	No		No		INPUT
data_i[58:57]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[60:59]	No	No		No		INPUT
data_i[71:61]	Yes	Yes	T4,T13,T18	Yes	T2,T4,T11	INPUT
data_o[0]	Yes	Yes	*T4,*T13,*T18	Yes	T2,T4,T11	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[4:2]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[7:6]	Yes	Yes	T4,T13,T18	Yes	T2,T4,T11	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[12:9]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[14:13]	No	No		No		OUTPUT
data_o[17:15]	Yes	Yes	T4,T13,T18	Yes	T2,T4,T11	OUTPUT
data_o[19:18]	No	No		No		OUTPUT
data_o[24:20]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[26:25]	No	No		No		OUTPUT
data_o[27]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[29:28]	No	No		No		OUTPUT
data_o[33:30]	Yes	Yes	T4,T13,T18	Yes	T2,T4,T11	OUTPUT
data_o[37:34]	No	No		No		OUTPUT
data_o[42:38]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[44]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[48:45]	No	No		No		OUTPUT
data_o[54:49]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[56:55]	No	No		No		OUTPUT
data_o[58:57]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[60:59]	No	No		No		OUTPUT
data_o[63:61]	Yes	Yes	T4,T13,T18	Yes	T2,T4,T11	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	190	69.85
Total Bits 0->1	136	95	69.85
Total Bits 1->0	136	95	69.85

Ports	2	0	0.00
Port Bits	272	190	69.85
Port Bits 0->1	136	95	69.85
Port Bits 1->0	136	95	69.85

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	INPUT
data_i[2]	No	No		No		INPUT
data_i[3]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[4]	No	No		No		INPUT
data_i[9:5]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	INPUT
data_i[11:10]	No	No		No		INPUT
data_i[13:12]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	INPUT
data_i[14]	No	No		No		INPUT
data_i[21:15]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	INPUT
data_i[22]	No	No		No		INPUT
data_i[23]	Yes	Yes	*T4,*T11,*T13	Yes	T2,T4,T11	INPUT
data_i[26:24]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[29]	No	No		No		INPUT
data_i[30]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[31]	No	No		No		INPUT
data_i[34:32]	Yes	Yes	T4,T13,T18	Yes	T2,T4,T11	INPUT
data_i[35]	No	No		No		INPUT
data_i[40:36]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	INPUT
data_i[41]	No	No		No		INPUT
data_i[42]	Yes	Yes	*T4,*T13,*T18	Yes	T2,T4,T11	INPUT
data_i[43]	No	No		No		INPUT
data_i[44]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[45]	No	No		No		INPUT
data_i[48:46]	Yes	Yes	T4,T13,T18	Yes	T2,T4,T11	INPUT
data_i[50:49]	No	No		No		INPUT
data_i[51]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[52]	No	No		No		INPUT
data_i[54:53]	Yes	Yes	T4,T13,T18	Yes	T2,T4,T11	INPUT
data_i[55]	No	No		No		INPUT
data_i[57:56]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	INPUT
data_i[58]	No	No		No		INPUT
data_i[64:59]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	INPUT
data_i[65]	No	No		No		INPUT
data_i[71:66]	Yes	Yes	T2,T5,T11	Yes	T2,T5,T11	INPUT
data_o[1:0]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[3]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[9:5]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	OUTPUT
data_o[11:10]	No	No		No		OUTPUT
data_o[13:12]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[21:15]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[23]	Yes	Yes	*T4,*T11,*T13	Yes	T2,T4,T11	OUTPUT
data_o[26:24]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[30]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[34:32]	Yes	Yes	T4,T13,T18	Yes	T2,T4,T11	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[40:36]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[42]	Yes	Yes	*T4,*T13,*T18	Yes	T2,T4,T11	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[44]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[45]	No	No		No		OUTPUT
data_o[48:46]	Yes	Yes	T4,T13,T18	Yes	T2,T4,T11	OUTPUT
data_o[50:49]	No	No		No		OUTPUT
data_o[51]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[54:53]	Yes	Yes	T4,T13,T18	Yes	T2,T4,T11	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[57:56]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[63:59]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	194	71.32
Total Bits 0->1	136	97	71.32
Total Bits 1->0	136	97	71.32

Ports	2	0	0.00
Port Bits	272	194	71.32
Port Bits 0->1	136	97	71.32
Port Bits 1->0	136	97	71.32

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[3]	No	No		No		INPUT
data_i[4]	Yes	Yes	*T5,*T13,*T102	Yes	T2,T5,T13	INPUT
data_i[6:5]	No	No		No		INPUT
data_i[7]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[8]	No	No		No		INPUT
data_i[19:9]	Yes	Yes	*T2,*T4,T5	Yes	T2,T4,T5	INPUT
data_i[23:20]	No	No		No		INPUT
data_i[30:24]	Yes	Yes	*T2,*T4,T5	Yes	T2,T4,T5	INPUT
data_i[31]	No	No		No		INPUT
data_i[32]	Yes	Yes	*T5,*T13,*T102	Yes	T2,T5,T13	INPUT
data_i[33]	No	No		No		INPUT
data_i[38:34]	Yes	Yes	*T2,*T4,T5	Yes	T2,T4,T5	INPUT
data_i[39]	No	No		No		INPUT
data_i[41:40]	Yes	Yes	T5,T13,T102	Yes	T2,T5,T13	INPUT
data_i[44:42]	No	No		No		INPUT
data_i[50:45]	Yes	Yes	T5,T13,T102	Yes	T2,T5,T13	INPUT
data_i[51]	No	No		No		INPUT
data_i[52]	Yes	Yes	*T5,*T13,*T102	Yes	T2,T5,T13	INPUT
data_i[53]	No	No		No		INPUT
data_i[54]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[55]	No	No		No		INPUT
data_i[58:56]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[59]	No	No		No		INPUT
data_i[62:60]	Yes	Yes	T5,T13,T102	Yes	T2,T5,T13	INPUT
data_i[63]	No	No		No		INPUT
data_i[69:64]	Yes	Yes	*T5,T13,*T102	Yes	T2,T5,T13	INPUT
data_i[70]	No	No		No		INPUT
data_i[71]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_o[2:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[4]	Yes	Yes	*T5,*T13,*T102	Yes	T2,T5,T13	OUTPUT
data_o[6:5]	No	No		No		OUTPUT
data_o[7]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[19:9]	Yes	Yes	*T2,*T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[23:20]	No	No		No		OUTPUT
data_o[30:24]	Yes	Yes	*T2,*T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[32]	Yes	Yes	*T5,*T13,*T102	Yes	T2,T5,T13	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[38:34]	Yes	Yes	*T2,*T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[41:40]	Yes	Yes	T5,T13,T102	Yes	T2,T5,T13	OUTPUT
data_o[44:42]	No	No		No		OUTPUT
data_o[50:45]	Yes	Yes	T5,T13,T102	Yes	T2,T5,T13	OUTPUT
data_o[51]	No	No		No		OUTPUT
data_o[52]	Yes	Yes	*T5,*T13,*T102	Yes	T2,T5,T13	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[54]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[58:56]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[59]	No	No		No		OUTPUT
data_o[62:60]	Yes	Yes	T5,T13,T102	Yes	T2,T5,T13	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	196	72.06
Total Bits 0->1	136	98	72.06
Total Bits 1->0	136	98	72.06

Ports	2	0	0.00
Port Bits	272	196	72.06
Port Bits 0->1	136	98	72.06
Port Bits 1->0	136	98	72.06

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[2]	No	No		No		INPUT
data_i[10:3]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	INPUT
data_i[11]	No	No		No		INPUT
data_i[17:12]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[18]	No	No		No		INPUT
data_i[20:19]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[21]	No	No		No		INPUT
data_i[22]	Yes	Yes	*T13,*T18,*T103	Yes	T2,T13,T18	INPUT
data_i[24:23]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[26]	No	No		No		INPUT
data_i[27]	Yes	Yes	*T13,*T18,*T103	Yes	T2,T13,T18	INPUT
data_i[29:28]	No	No		No		INPUT
data_i[32:30]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[34:33]	No	No		No		INPUT
data_i[44:35]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[47:45]	No	No		No		INPUT
data_i[49:48]	Yes	Yes	T13,T20,T91	Yes	T13,T20,T91	INPUT
data_i[50]	No	No		No		INPUT
data_i[56:51]	Yes	Yes	T13,*T20,*T91	Yes	T13,T20,T91	INPUT
data_i[57]	No	No		No		INPUT
data_i[58]	Yes	Yes	*T13,*T20,*T91	Yes	T13,T20,T91	INPUT
data_i[61:59]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_o[1:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[10:3]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[17:12]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[20:19]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[21]	No	No		No		OUTPUT
data_o[22]	Yes	Yes	*T13,*T18,*T103	Yes	T2,T13,T18	OUTPUT
data_o[24:23]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[27]	Yes	Yes	*T13,*T18,*T103	Yes	T2,T13,T18	OUTPUT
data_o[29:28]	No	No		No		OUTPUT
data_o[32:30]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[34:33]	No	No		No		OUTPUT
data_o[44:35]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[47:45]	No	No		No		OUTPUT
data_o[49:48]	Yes	Yes	T13,T20,T91	Yes	T13,T20,T91	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[56:51]	Yes	Yes	T13,*T20,*T91	Yes	T13,T20,T91	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[58]	Yes	Yes	*T13,*T20,*T91	Yes	T13,T20,T91	OUTPUT
data_o[61:59]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	198	72.79
Total Bits 0->1	136	99	72.79
Total Bits 1->0	136	99	72.79

Ports	2	0	0.00
Port Bits	272	198	72.79
Port Bits 0->1	136	99	72.79
Port Bits 1->0	136	99	72.79

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[6:0]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	INPUT
data_i[11:7]	No	No		No		INPUT
data_i[18:12]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	INPUT
data_i[19]	No	No		No		INPUT
data_i[22:20]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	INPUT
data_i[23]	No	No		No		INPUT
data_i[24]	Yes	Yes	*T4,*T11,*T13	Yes	T2,T4,T11	INPUT
data_i[25]	No	No		No		INPUT
data_i[27:26]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[28]	No	No		No		INPUT
data_i[29]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[30]	No	No		No		INPUT
data_i[32:31]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	INPUT
data_i[35:33]	No	No		No		INPUT
data_i[36]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[37]	No	No		No		INPUT
data_i[41:38]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	INPUT
data_i[42]	No	No		No		INPUT
data_i[47:43]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	INPUT
data_i[48]	No	No		No		INPUT
data_i[50:49]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	INPUT
data_i[51]	No	No		No		INPUT
data_i[54:52]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	INPUT
data_i[55]	No	No		No		INPUT
data_i[68:56]	Yes	Yes	*T4,*T11,*T13	Yes	T2,T4,T11	INPUT
data_i[69]	No	No		No		INPUT
data_i[71:70]	Yes	Yes	T2,T5,T102	Yes	T2,T5,T102	INPUT
data_o[6:0]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[11:7]	No	No		No		OUTPUT
data_o[18:12]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[22:20]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[24]	Yes	Yes	*T4,*T11,*T13	Yes	T2,T4,T11	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[27:26]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[29]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[32:31]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	OUTPUT
data_o[35:33]	No	No		No		OUTPUT
data_o[36]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[41:38]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[47:43]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[50:49]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[51]	No	No		No		OUTPUT
data_o[54:52]	Yes	Yes	*T2,T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[63:56]	Yes	Yes	T4,T11,T13	Yes	T2,T4,T11	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	200	73.53
Total Bits 0->1	136	100	73.53
Total Bits 1->0	136	100	73.53

Ports	2	0	0.00
Port Bits	272	200	73.53
Port Bits 0->1	136	100	73.53
Port Bits 1->0	136	100	73.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[3]	No	No		No		INPUT
data_i[4]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[5]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[7]	No	No		No		INPUT
data_i[8]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[10:9]	No	No		No		INPUT
data_i[19:11]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[20]	No	No		No		INPUT
data_i[21]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[23:22]	No	No		No		INPUT
data_i[28:24]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[41:31]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[44:42]	No	No		No		INPUT
data_i[46:45]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[47]	No	No		No		INPUT
data_i[48]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[49]	No	No		No		INPUT
data_i[56:50]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[58:57]	No	No		No		INPUT
data_i[61:59]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[62]	No	No		No		INPUT
data_i[71:63]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_o[2:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[4]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[8]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[10:9]	No	No		No		OUTPUT
data_o[19:11]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[21]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[23:22]	No	No		No		OUTPUT
data_o[28:24]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[41:31]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[44:42]	No	No		No		OUTPUT
data_o[46:45]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[48]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[56:50]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[58:57]	No	No		No		OUTPUT
data_o[61:59]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[62]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	200	73.53
Total Bits 0->1	136	100	73.53
Total Bits 1->0	136	100	73.53

Ports	2	0	0.00
Port Bits	272	200	73.53
Port Bits 0->1	136	100	73.53
Port Bits 1->0	136	100	73.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[2:1]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[3]	No	No		No		INPUT
data_i[10:4]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[13:11]	No	No		No		INPUT
data_i[14]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[15]	No	No		No		INPUT
data_i[21:16]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[22]	No	No		No		INPUT
data_i[23]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[24]	No	No		No		INPUT
data_i[27:25]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[28]	No	No		No		INPUT
data_i[29]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[30]	No	No		No		INPUT
data_i[35:31]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[36]	No	No		No		INPUT
data_i[38:37]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[41:39]	No	No		No		INPUT
data_i[43:42]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[45:44]	No	No		No		INPUT
data_i[55:46]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[56]	No	No		No		INPUT
data_i[58:57]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[59]	No	No		No		INPUT
data_i[71:60]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[2:1]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[10:4]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[13:11]	No	No		No		OUTPUT
data_o[14]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[21:16]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[23]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[27:25]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[29]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[35:31]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[36]	No	No		No		OUTPUT
data_o[38:37]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[41:39]	No	No		No		OUTPUT
data_o[43:42]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[45:44]	No	No		No		OUTPUT
data_o[55:46]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[58:57]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[59]	No	No		No		OUTPUT
data_o[63:60]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	202	74.26
Total Bits 0->1	136	101	74.26
Total Bits 1->0	136	101	74.26

Ports	2	0	0.00
Port Bits	272	202	74.26
Port Bits 0->1	136	101	74.26
Port Bits 1->0	136	101	74.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[7:0]	Yes	Yes	T2,T5,T11	Yes	T2,T5,T11	INPUT
data_i[9:8]	No	No		No		INPUT
data_i[13:10]	Yes	Yes	T2,*T4,T5	Yes	T2,T4,T5	INPUT
data_i[14]	No	No		No		INPUT
data_i[16:15]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[17]	No	No		No		INPUT
data_i[20:18]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[21]	No	No		No		INPUT
data_i[22]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[23]	No	No		No		INPUT
data_i[28:24]	Yes	Yes	T5,T11,T13	Yes	T2,T5,T11	INPUT
data_i[29]	No	No		No		INPUT
data_i[32:30]	Yes	Yes	*T2,*T4,T5	Yes	T2,T4,T5	INPUT
data_i[33]	No	No		No		INPUT
data_i[36:34]	Yes	Yes	T5,T11,T13	Yes	T2,T5,T11	INPUT
data_i[37]	No	No		No		INPUT
data_i[41:38]	Yes	Yes	*T2,*T4,T5	Yes	T2,T4,T5	INPUT
data_i[42]	No	No		No		INPUT
data_i[43]	Yes	Yes	*T5,*T11,*T13	Yes	T2,T5,T11	INPUT
data_i[44]	No	No		No		INPUT
data_i[45]	Yes	Yes	*T5,*T11,*T13	Yes	T2,T5,T11	INPUT
data_i[48:46]	No	No		No		INPUT
data_i[50:49]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[52:51]	No	No		No		INPUT
data_i[61:53]	Yes	Yes	*T2,*T4,T5	Yes	T2,T4,T5	INPUT
data_i[62]	No	No		No		INPUT
data_i[69:63]	Yes	Yes	*T5,*T13,*T102	Yes	T2,T5,T11	INPUT
data_i[70]	No	No		No		INPUT
data_i[71]	Yes	Yes	T20,T254,T32	Yes	T20,T254,T200	INPUT
data_o[7:0]	Yes	Yes	T2,T5,T11	Yes	T2,T5,T11	OUTPUT
data_o[9:8]	No	No		No		OUTPUT
data_o[13:10]	Yes	Yes	T2,*T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[16:15]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[20:18]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[21]	No	No		No		OUTPUT
data_o[22]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[28:24]	Yes	Yes	T5,T11,T13	Yes	T2,T5,T11	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[32:30]	Yes	Yes	*T2,*T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[36:34]	Yes	Yes	T5,T11,T13	Yes	T2,T5,T11	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[41:38]	Yes	Yes	*T2,*T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[43]	Yes	Yes	*T5,*T11,*T13	Yes	T2,T5,T11	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[45]	Yes	Yes	*T5,*T11,*T13	Yes	T2,T5,T11	OUTPUT
data_o[48:46]	No	No		No		OUTPUT
data_o[50:49]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[52:51]	No	No		No		OUTPUT
data_o[61:53]	Yes	Yes	*T2,*T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[62]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T5,T13,T102	Yes	T2,T5,T11	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	204	75.00
Total Bits 0->1	136	102	75.00
Total Bits 1->0	136	102	75.00

Ports	2	0	0.00
Port Bits	272	204	75.00
Port Bits 0->1	136	102	75.00
Port Bits 1->0	136	102	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[1]	No	No		No		INPUT
data_i[6:2]	Yes	Yes	T4,T5,T11	Yes	T2,T4,T5	INPUT
data_i[7]	No	No		No		INPUT
data_i[11:8]	Yes	Yes	T4,T5,T11	Yes	T2,T4,T5	INPUT
data_i[12]	No	No		No		INPUT
data_i[18:13]	Yes	Yes	T4,T5,T11	Yes	T2,T4,T5	INPUT
data_i[20:19]	No	No		No		INPUT
data_i[27:21]	Yes	Yes	*T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[28]	No	No		No		INPUT
data_i[30:29]	Yes	Yes	*T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[31]	No	No		No		INPUT
data_i[32]	Yes	Yes	*T4,*T5,*T11	Yes	T2,T4,T5	INPUT
data_i[33]	No	No		No		INPUT
data_i[34]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[35]	No	No		No		INPUT
data_i[36]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[37]	No	No		No		INPUT
data_i[40:38]	Yes	Yes	*T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[41]	No	No		No		INPUT
data_i[43:42]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[44]	No	No		No		INPUT
data_i[46:45]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[47]	No	No		No		INPUT
data_i[51:48]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[52]	No	No		No		INPUT
data_i[53]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[55:54]	No	No		No		INPUT
data_i[56]	Yes	Yes	*T4,*T5,*T11	Yes	T2,T4,T5	INPUT
data_i[57]	No	No		No		INPUT
data_i[71:58]	Yes	Yes	T4,T5,T11	Yes	T2,T4,T5	INPUT
data_o[0]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[6:2]	Yes	Yes	T4,T5,T11	Yes	T2,T4,T5	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[11:8]	Yes	Yes	T4,T5,T11	Yes	T2,T4,T5	OUTPUT
data_o[12]	No	No		No		OUTPUT
data_o[18:13]	Yes	Yes	T4,T5,T11	Yes	T2,T4,T5	OUTPUT
data_o[20:19]	No	No		No		OUTPUT
data_o[27:21]	Yes	Yes	*T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[30:29]	Yes	Yes	*T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[32]	Yes	Yes	*T4,*T5,*T11	Yes	T2,T4,T5	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[34]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[36]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[40:38]	Yes	Yes	*T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[43:42]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[46:45]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[51:48]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[53]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[55:54]	No	No		No		OUTPUT
data_o[56]	Yes	Yes	*T4,*T5,*T11	Yes	T2,T4,T5	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[63:58]	Yes	Yes	T4,T5,T11	Yes	T2,T4,T5	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	208	76.47
Total Bits 0->1	136	104	76.47
Total Bits 1->0	136	104	76.47

Ports	2	0	0.00
Port Bits	272	208	76.47
Port Bits 0->1	136	104	76.47
Port Bits 1->0	136	104	76.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[5:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[6]	No	No		No		INPUT
data_i[8:7]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[9]	No	No		No		INPUT
data_i[12:10]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[14:13]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[16]	No	No		No		INPUT
data_i[17]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[18]	No	No		No		INPUT
data_i[23:19]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[24]	No	No		No		INPUT
data_i[27:25]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[29:28]	No	No		No		INPUT
data_i[31:30]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[32]	No	No		No		INPUT
data_i[35:33]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[36]	No	No		No		INPUT
data_i[40:37]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[41]	No	No		No		INPUT
data_i[42]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[43]	No	No		No		INPUT
data_i[45:44]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[46]	No	No		No		INPUT
data_i[47]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[48]	No	No		No		INPUT
data_i[62:49]	Yes	Yes	*T2,*T5,*T11	Yes	T2,T5,T11	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_o[5:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[8:7]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[12:10]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[14:13]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[17]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[23:19]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[27:25]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[29:28]	No	No		No		OUTPUT
data_o[31:30]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[35:33]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[36]	No	No		No		OUTPUT
data_o[40:37]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[42]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[45:44]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[47]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[62:49]	Yes	Yes	*T2,*T5,*T11	Yes	T2,T5,T11	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	256	94.12
Total Bits 0->1	136	128	94.12
Total Bits 1->0	136	128	94.12

Ports	2	0	0.00
Port Bits	272	256	94.12
Port Bits 0->1	136	128	94.12
Port Bits 1->0	136	128	94.12

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[5:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[7:6]	No	No		No		INPUT
data_i[23:8]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
data_i[25:24]	No	No		No		INPUT
data_i[71:26]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_o[5:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[7:6]	No	No		No		OUTPUT
data_o[23:8]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
data_o[25:24]	No	No		No		OUTPUT
data_o[63:26]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	280	272	97.14
Total Bits 0->1	140	136	97.14
Total Bits 1->0	140	136	97.14

Ports	4	2	50.00
Port Bits	280	272	97.14
Port Bits 0->1	140	136	97.14
Port Bits 1->0	140	136	97.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T93,T124,T61	Yes	T12,T93,T124	INPUT
data_o[63:0]	Yes	Yes	T93,T124,T61	Yes	T12,T93,T124	OUTPUT
syndrome_o[2:0]	No	No		No		OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	No	No		No		OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T4,T93,T106	Yes	T4,T93,T106	INPUT
data_o[63:0]	Yes	Yes	T4,T93,T106	Yes	T4,T93,T106	OUTPUT
syndrome_o[2:0]	Yes	Yes	T97,T154,T155	Yes	T97,T154,T155	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T97,*T154,*T155	Yes	T97,T154,T155	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T11,T18,T93	Yes	T11,T12,T18	INPUT
data_o[63:0]	Yes	Yes	T11,T18,T93	Yes	T11,T12,T18	OUTPUT
syndrome_o[2:0]	Yes	Yes	T97,T155	Yes	T97,T155	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T97,*T155	Yes	T97,T155	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T106,T97,T91	Yes	T106,T97,T91	INPUT
data_o[63:0]	Yes	Yes	T106,T91,T125	Yes	T106,T91,T125	OUTPUT
syndrome_o[2:0]	Yes	Yes	T97,T155	Yes	T97,T155	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T97,*T155	Yes	T97,T155	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T4,T11,T107	Yes	T4,T11,T107	INPUT
data_o[63:0]	Yes	Yes	T4,T11,T107	Yes	T4,T11,T107	OUTPUT
syndrome_o[2:0]	Yes	Yes	T97,T154	Yes	T97,T154	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T97,*T154	Yes	T97,T154	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T103,T113	Yes	T3,T103,T113	INPUT
data_o[63:0]	Yes	Yes	T3,T103,T113	Yes	T3,T103,T113	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T107,T113,T255	Yes	T104,T107,T113	INPUT
data_o[63:0]	Yes	Yes	T107,T113,T255	Yes	T104,T107,T113	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T29,T109,T119	Yes	T29,T109,T119	INPUT
data_o[63:0]	Yes	Yes	T29,T109,T119	Yes	T29,T109,T119	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T18,T125,T94	Yes	T18,T104,T125	INPUT
data_o[63:0]	Yes	Yes	T18,T125,T94	Yes	T18,T104,T125	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T18,T196	Yes	T5,T18,T196	INPUT
data_o[63:0]	Yes	Yes	T5,T18,T196	Yes	T5,T18,T196	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T105,T162,T135	Yes	T105,T162,T135	INPUT
data_o[63:0]	Yes	Yes	T105,T162,T135	Yes	T105,T162,T135	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T111,T108,T222	Yes	T111,T108,T222	INPUT
data_o[63:0]	Yes	Yes	T111,T108,T222	Yes	T111,T108,T222	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T105,T108,T125	Yes	T2,T105,T108	INPUT
data_o[63:0]	Yes	Yes	T105,T108,T125	Yes	T2,T105,T108	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T11,T18,T93	Yes	T2,T11,T18	INPUT
data_o[63:0]	Yes	Yes	T11,T18,T93	Yes	T2,T11,T18	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T29,T93	Yes	T2,T5,T29	INPUT
data_o[63:0]	Yes	Yes	T5,T29,T93	Yes	T2,T5,T29	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T29,T93	Yes	T3,T29,T93	INPUT
data_o[63:0]	Yes	Yes	T3,T29,T93	Yes	T3,T29,T93	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T105,T111,T108	Yes	T2,T105,T111	INPUT
data_o[63:0]	Yes	Yes	T105,T111,T108	Yes	T2,T105,T111	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T13,T18,T103	Yes	T13,T18,T103	INPUT
data_o[63:0]	Yes	Yes	T13,T18,T103	Yes	T13,T18,T103	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T187,T109	Yes	T5,T104,T187	INPUT
data_o[63:0]	Yes	Yes	T5,T187,T109	Yes	T5,T104,T187	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T11,T13	Yes	T5,T11,T13	INPUT
data_o[63:0]	Yes	Yes	T5,T11,T13	Yes	T5,T11,T13	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T13,T105	Yes	T2,T13,T105	INPUT
data_o[63:0]	Yes	Yes	T2,T13,T105	Yes	T2,T13,T105	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_o[63:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR