Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	103474757	397614	0	0
check_regwen_rd_A	103474757	2037	0	0
check_timeout_rd_A	103474757	1368	0	0
check_trigger_regwen_rd_A	103474757	2133	0	0
consistency_check_period_rd_A	103474757	2062	0	0
creator_sw_cfg_read_lock_rd_A	103474757	1322	0	0
direct_access_address_rd_A	103474757	649	0	0
direct_access_wdata_0_rd_A	103474757	107	0	0
direct_access_wdata_1_rd_A	103474757	131	0	0
integrity_check_period_rd_A	103474757	1917	0	0
intr_enable_rd_A	103474757	2935	0	0
owner_sw_cfg_read_lock_rd_A	103474757	1278	0	0
rot_creator_auth_codesign_read_lock_rd_A	103474757	1163	0	0
rot_creator_auth_state_read_lock_rd_A	103474757	1275	0	0
vendor_test_read_lock_rd_A	103474757	1229	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103474757	397614	0	0
T14	303793	6339	0	0
T15	155295	3068	0	0
T16	0	7695	0	0
T21	0	8280	0	0
T24	0	7606	0	0
T90	0	12752	0	0
T91	0	4033	0	0
T95	0	10510	0	0
T98	0	6707	0	0
T132	9624	0	0	0
T241	158044	0	0	0
T246	24668	0	0	0
T293	0	6637	0	0
T294	37388	0	0	0
T295	28637	0	0	0
T296	15394	0	0	0
T297	53451	0	0	0
T298	66656	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103474757	2037	0	0
T14	303793	10	0	0
T15	155295	12	0	0
T16	0	43	0	0
T21	0	30	0	0
T24	0	33	0	0
T90	0	39	0	0
T132	9624	0	0	0
T241	158044	0	0	0
T242	0	49	0	0
T246	24668	0	0	0
T294	37388	0	0	0
T295	28637	0	0	0
T296	15394	0	0	0
T297	53451	0	0	0
T298	66656	0	0	0
T333	0	31	0	0
T334	0	15	0	0
T335	0	21	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103474757	1368	0	0
T14	303793	28	0	0
T15	155295	23	0	0
T16	0	55	0	0
T21	0	33	0	0
T24	0	14	0	0
T90	0	50	0	0
T132	9624	0	0	0
T241	158044	0	0	0
T242	0	31	0	0
T246	24668	0	0	0
T294	37388	0	0	0
T295	28637	0	0	0
T296	15394	0	0	0
T297	53451	0	0	0
T298	66656	0	0	0
T333	0	35	0	0
T334	0	24	0	0
T335	0	6	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103474757	2133	0	0
T14	303793	35	0	0
T15	155295	22	0	0
T16	0	54	0	0
T21	0	48	0	0
T24	0	18	0	0
T90	0	64	0	0
T132	9624	0	0	0
T241	158044	0	0	0
T242	0	37	0	0
T246	24668	0	0	0
T294	37388	0	0	0
T295	28637	0	0	0
T296	15394	0	0	0
T297	53451	0	0	0
T298	66656	0	0	0
T333	0	19	0	0
T334	0	23	0	0
T335	0	33	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103474757	2062	0	0
T14	303793	31	0	0
T15	155295	24	0	0
T16	0	43	0	0
T21	0	48	0	0
T24	0	26	0	0
T90	0	48	0	0
T132	9624	0	0	0
T241	158044	0	0	0
T242	0	40	0	0
T246	24668	0	0	0
T294	37388	0	0	0
T295	28637	0	0	0
T296	15394	0	0	0
T297	53451	0	0	0
T298	66656	0	0	0
T333	0	18	0	0
T334	0	23	0	0
T335	0	27	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103474757	1322	0	0
T14	303793	29	0	0
T15	155295	22	0	0
T16	0	31	0	0
T21	0	74	0	0
T24	0	42	0	0
T90	0	32	0	0
T132	9624	0	0	0
T241	158044	0	0	0
T242	0	20	0	0
T246	24668	0	0	0
T294	37388	0	0	0
T295	28637	0	0	0
T296	15394	0	0	0
T297	53451	0	0	0
T298	66656	0	0	0
T333	0	35	0	0
T334	0	14	0	0
T335	0	30	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103474757	649	0	0
T14	303793	35	0	0
T15	155295	11	0	0
T16	0	31	0	0
T21	0	54	0	0
T24	0	29	0	0
T90	0	60	0	0
T132	9624	0	0	0
T241	158044	0	0	0
T242	0	36	0	0
T246	24668	0	0	0
T294	37388	0	0	0
T295	28637	0	0	0
T296	15394	0	0	0
T297	53451	0	0	0
T298	66656	0	0	0
T333	0	5	0	0
T334	0	33	0	0
T335	0	29	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103474757	107	0	0
T14	303793	5	0	0
T15	155295	0	0	0
T16	0	2	0	0
T24	0	20	0	0
T90	0	8	0	0
T132	9624	0	0	0
T241	158044	0	0	0
T242	0	38	0	0
T246	24668	0	0	0
T294	37388	0	0	0
T295	28637	0	0	0
T296	15394	0	0	0
T297	53451	0	0	0
T298	66656	0	0	0
T335	0	4	0	0
T336	0	2	0	0
T337	0	5	0	0
T338	0	6	0	0
T339	0	6	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103474757	131	0	0
T15	155295	5	0	0
T16	0	23	0	0
T24	0	4	0	0
T90	0	13	0	0
T132	9624	0	0	0
T223	90941	0	0	0
T241	158044	0	0	0
T242	0	10	0	0
T246	24668	0	0	0
T294	37388	0	0	0
T295	28637	0	0	0
T296	15394	0	0	0
T297	53451	0	0	0
T298	66656	0	0	0
T333	0	3	0	0
T334	0	6	0	0
T337	0	6	0	0
T338	0	9	0	0
T340	0	15	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103474757	1917	0	0
T14	303793	28	0	0
T15	155295	32	0	0
T16	0	40	0	0
T21	0	41	0	0
T24	0	28	0	0
T90	0	59	0	0
T132	9624	0	0	0
T241	158044	0	0	0
T242	0	41	0	0
T246	24668	0	0	0
T294	37388	0	0	0
T295	28637	0	0	0
T296	15394	0	0	0
T297	53451	0	0	0
T298	66656	0	0	0
T333	0	12	0	0
T334	0	14	0	0
T335	0	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103474757	2935	0	0
T14	303793	51	0	0
T15	155295	23	0	0
T16	0	98	0	0
T21	0	56	0	0
T24	0	26	0	0
T90	0	68	0	0
T132	9624	0	0	0
T157	0	5	0	0
T241	158044	0	0	0
T242	0	57	0	0
T246	24668	0	0	0
T294	37388	0	0	0
T295	28637	0	0	0
T296	15394	0	0	0
T297	53451	0	0	0
T298	66656	0	0	0
T341	0	14	0	0
T342	0	15	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103474757	1278	0	0
T14	303793	16	0	0
T15	155295	27	0	0
T16	0	42	0	0
T21	0	37	0	0
T24	0	40	0	0
T90	0	54	0	0
T132	9624	0	0	0
T241	158044	0	0	0
T242	0	50	0	0
T246	24668	0	0	0
T294	37388	0	0	0
T295	28637	0	0	0
T296	15394	0	0	0
T297	53451	0	0	0
T298	66656	0	0	0
T333	0	12	0	0
T334	0	16	0	0
T335	0	17	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103474757	1163	0	0
T14	303793	24	0	0
T15	155295	16	0	0
T16	0	45	0	0
T21	0	35	0	0
T24	0	19	0	0
T90	0	41	0	0
T132	9624	0	0	0
T241	158044	0	0	0
T242	0	59	0	0
T246	24668	0	0	0
T294	37388	0	0	0
T295	28637	0	0	0
T296	15394	0	0	0
T297	53451	0	0	0
T298	66656	0	0	0
T333	0	13	0	0
T334	0	16	0	0
T335	0	19	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103474757	1275	0	0
T14	303793	28	0	0
T15	155295	20	0	0
T16	0	58	0	0
T21	0	42	0	0
T24	0	22	0	0
T90	0	21	0	0
T132	9624	0	0	0
T241	158044	0	0	0
T242	0	54	0	0
T246	24668	0	0	0
T294	37388	0	0	0
T295	28637	0	0	0
T296	15394	0	0	0
T297	53451	0	0	0
T298	66656	0	0	0
T333	0	27	0	0
T334	0	25	0	0
T335	0	16	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103474757	1229	0	0
T14	303793	20	0	0
T15	155295	22	0	0
T16	0	43	0	0
T21	0	44	0	0
T24	0	27	0	0
T90	0	37	0	0
T132	9624	0	0	0
T241	158044	0	0	0
T242	0	46	0	0
T246	24668	0	0	0
T294	37388	0	0	0
T295	28637	0	0	0
T296	15394	0	0	0
T297	53451	0	0	0
T298	66656	0	0	0
T333	0	7	0	0
T334	0	20	0	0
T335	0	24	0	0