Module Definition
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Module : prim_secded_inv_72_64_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 70.59 70.59
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 70.59 70.59
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 72.06 72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 72.06 72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 75.00 75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 75.00 75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 75.74 75.74
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 76.47 76.47
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 78.68 78.68
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 80.88 80.88
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 82.35 82.35
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.59 70.59


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.59 70.59


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.59 70.59


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.59 70.59


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.06 72.06


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.06 72.06


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.06 72.06


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.06 72.06


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.74 75.74


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.74 75.74


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.68 78.68


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.68 78.68


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.88 80.88


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.88 80.88


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.35 82.35


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.35 82.35


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T6,T36,T94 Yes T6,T36,T94 INPUT
data_o[63:0] Yes Yes T6,T36,T94 Yes T6,T36,T94 OUTPUT
syndrome_o[2:0] Yes Yes T109,T110,T173 Yes T109,T110,T173 OUTPUT
syndrome_o[7:3] No No No OUTPUT
err_o[0] Yes Yes *T109,*T110,*T173 Yes T109,T110,T173 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 192 70.59
Total Bits 0->1 136 96 70.59
Total Bits 1->0 136 96 70.59

Ports 2 0 0.00
Port Bits 272 192 70.59
Port Bits 0->1 136 96 70.59
Port Bits 1->0 136 96 70.59

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[3:1] Yes Yes T13,T36,T94 Yes T13,T36,T94 INPUT
data_i[4] No No No INPUT
data_i[9:5] Yes Yes *T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[11:10] No No No INPUT
data_i[17:12] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 INPUT
data_i[18] No No No INPUT
data_i[22:19] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 INPUT
data_i[23] No No No INPUT
data_i[25:24] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 INPUT
data_i[26] No No No INPUT
data_i[28:27] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 INPUT
data_i[29] No No No INPUT
data_i[30] Yes Yes *T36,*T94,*T92 Yes T36,T94,T92 INPUT
data_i[32:31] No No No INPUT
data_i[37:33] Yes Yes *T85,*T6,*T13 Yes T85,T6,T13 INPUT
data_i[38] No No No INPUT
data_i[42:39] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 INPUT
data_i[43] No No No INPUT
data_i[44] Yes Yes *T85 Yes T85 INPUT
data_i[46:45] No No No INPUT
data_i[47] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[49:48] No No No INPUT
data_i[55:50] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 INPUT
data_i[56] No No No INPUT
data_i[57] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[59:58] No No No INPUT
data_i[61:60] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[62] No No No INPUT
data_i[71:63] Yes Yes T36,T94,T92 Yes T36,T94,T92 INPUT
data_o[0] No No No OUTPUT
data_o[3:1] Yes Yes T13,T36,T94 Yes T13,T36,T94 OUTPUT
data_o[4] No No No OUTPUT
data_o[9:5] Yes Yes *T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[11:10] No No No OUTPUT
data_o[17:12] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 OUTPUT
data_o[18] No No No OUTPUT
data_o[22:19] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 OUTPUT
data_o[23] No No No OUTPUT
data_o[25:24] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 OUTPUT
data_o[26] No No No OUTPUT
data_o[28:27] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 OUTPUT
data_o[29] No No No OUTPUT
data_o[30] Yes Yes *T36,*T94,*T92 Yes T36,T94,T92 OUTPUT
data_o[32:31] No No No OUTPUT
data_o[37:33] Yes Yes *T85,*T6,*T13 Yes T85,T6,T13 OUTPUT
data_o[38] No No No OUTPUT
data_o[42:39] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 OUTPUT
data_o[43] No No No OUTPUT
data_o[44] Yes Yes *T85 Yes T85 OUTPUT
data_o[46:45] No No No OUTPUT
data_o[47] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[49:48] No No No OUTPUT
data_o[55:50] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 OUTPUT
data_o[56] No No No OUTPUT
data_o[57] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[59:58] No No No OUTPUT
data_o[61:60] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[62] No No No OUTPUT
data_o[63] Yes Yes T36,T94,T92 Yes T36,T94,T92 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 192 70.59
Total Bits 0->1 136 96 70.59
Total Bits 1->0 136 96 70.59

Ports 2 0 0.00
Port Bits 272 192 70.59
Port Bits 0->1 136 96 70.59
Port Bits 1->0 136 96 70.59

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[2:1] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[4:3] No No No INPUT
data_i[9:5] Yes Yes T94,T93,T18 Yes T94,T92,T93 INPUT
data_i[10] No No No INPUT
data_i[20:11] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[21] No No No INPUT
data_i[22] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[23] No No No INPUT
data_i[27:24] Yes Yes T94,T93,T18 Yes T94,T92,T93 INPUT
data_i[28] No No No INPUT
data_i[31:29] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[32] No No No INPUT
data_i[33] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[34] No No No INPUT
data_i[40:35] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[41] No No No INPUT
data_i[42] Yes Yes *T18,*T96,*T19 Yes T92,T93,T18 INPUT
data_i[43] No No No INPUT
data_i[44] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[45] No No No INPUT
data_i[47:46] Yes Yes T18,T96,T19 Yes T92,T93,T18 INPUT
data_i[50:48] No No No INPUT
data_i[51] Yes Yes *T18,*T96,*T20 Yes T92,T18,T96 INPUT
data_i[52] No No No INPUT
data_i[53] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[55:54] No No No INPUT
data_i[59:56] Yes Yes T18,*T96,*T20 Yes T92,T18,T96 INPUT
data_i[60] No No No INPUT
data_i[61] Yes Yes *T18,*T96,*T20 Yes T92,T18,T96 INPUT
data_i[62] No No No INPUT
data_i[71:63] Yes Yes T18,T96,T20 Yes T92,T18,T96 INPUT
data_o[0] No No No OUTPUT
data_o[2:1] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[4:3] No No No OUTPUT
data_o[9:5] Yes Yes T94,T93,T18 Yes T94,T92,T93 OUTPUT
data_o[10] No No No OUTPUT
data_o[20:11] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[21] No No No OUTPUT
data_o[22] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[23] No No No OUTPUT
data_o[27:24] Yes Yes T94,T93,T18 Yes T94,T92,T93 OUTPUT
data_o[28] No No No OUTPUT
data_o[31:29] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[32] No No No OUTPUT
data_o[33] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[34] No No No OUTPUT
data_o[40:35] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[41] No No No OUTPUT
data_o[42] Yes Yes *T18,*T96,*T19 Yes T92,T93,T18 OUTPUT
data_o[43] No No No OUTPUT
data_o[44] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[45] No No No OUTPUT
data_o[47:46] Yes Yes T18,T96,T19 Yes T92,T93,T18 OUTPUT
data_o[50:48] No No No OUTPUT
data_o[51] Yes Yes *T18,*T96,*T20 Yes T92,T18,T96 OUTPUT
data_o[52] No No No OUTPUT
data_o[53] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[55:54] No No No OUTPUT
data_o[59:56] Yes Yes T18,*T96,*T20 Yes T92,T18,T96 OUTPUT
data_o[60] No No No OUTPUT
data_o[61] Yes Yes *T18,*T96,*T20 Yes T92,T18,T96 OUTPUT
data_o[62] No No No OUTPUT
data_o[63] Yes Yes T18,T96,T20 Yes T92,T18,T96 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 196 72.06
Total Bits 0->1 136 98 72.06
Total Bits 1->0 136 98 72.06

Ports 2 0 0.00
Port Bits 272 196 72.06
Port Bits 0->1 136 98 72.06
Port Bits 1->0 136 98 72.06

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[4:0] Yes Yes T36,T94,T92 Yes T36,T94,T92 INPUT
data_i[5] No No No INPUT
data_i[7:6] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[8] No No No INPUT
data_i[14:9] Yes Yes T36,T94,T92 Yes T36,T94,T92 INPUT
data_i[15] No No No INPUT
data_i[16] Yes Yes *T36,*T94,*T92 Yes T36,T94,T92 INPUT
data_i[17] No No No INPUT
data_i[22:18] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 INPUT
data_i[23] No No No INPUT
data_i[24] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[25] No No No INPUT
data_i[26] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[27] No No No INPUT
data_i[30:28] Yes Yes T36,T94,T92 Yes T36,T94,T92 INPUT
data_i[32:31] No No No INPUT
data_i[33] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[35:34] No No No INPUT
data_i[38:36] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[39] No No No INPUT
data_i[40] Yes Yes *T36,*T94,*T92 Yes T36,T94,T92 INPUT
data_i[41] No No No INPUT
data_i[47:42] Yes Yes T36,T94,T92 Yes T36,T94,T92 INPUT
data_i[48] No No No INPUT
data_i[50:49] Yes Yes T36,T94,T93 Yes T36,T94,T92 INPUT
data_i[51] No No No INPUT
data_i[52] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[53] No No No INPUT
data_i[54] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[55] No No No INPUT
data_i[58:56] Yes Yes T36,T94,T93 Yes T36,T94,T92 INPUT
data_i[60:59] No No No INPUT
data_i[71:61] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_o[4:0] Yes Yes T36,T94,T92 Yes T36,T94,T92 OUTPUT
data_o[5] No No No OUTPUT
data_o[7:6] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[8] No No No OUTPUT
data_o[14:9] Yes Yes T36,T94,T92 Yes T36,T94,T92 OUTPUT
data_o[15] No No No OUTPUT
data_o[16] Yes Yes *T36,*T94,*T92 Yes T36,T94,T92 OUTPUT
data_o[17] No No No OUTPUT
data_o[22:18] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 OUTPUT
data_o[23] No No No OUTPUT
data_o[24] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[25] No No No OUTPUT
data_o[26] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[27] No No No OUTPUT
data_o[30:28] Yes Yes T36,T94,T92 Yes T36,T94,T92 OUTPUT
data_o[32:31] No No No OUTPUT
data_o[33] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[35:34] No No No OUTPUT
data_o[38:36] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[39] No No No OUTPUT
data_o[40] Yes Yes *T36,*T94,*T92 Yes T36,T94,T92 OUTPUT
data_o[41] No No No OUTPUT
data_o[47:42] Yes Yes T36,T94,T92 Yes T36,T94,T92 OUTPUT
data_o[48] No No No OUTPUT
data_o[50:49] Yes Yes T36,T94,T93 Yes T36,T94,T92 OUTPUT
data_o[51] No No No OUTPUT
data_o[52] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[53] No No No OUTPUT
data_o[54] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[55] No No No OUTPUT
data_o[58:56] Yes Yes T36,T94,T93 Yes T36,T94,T92 OUTPUT
data_o[60:59] No No No OUTPUT
data_o[63:61] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 196 72.06
Total Bits 0->1 136 98 72.06
Total Bits 1->0 136 98 72.06

Ports 2 0 0.00
Port Bits 272 196 72.06
Port Bits 0->1 136 98 72.06
Port Bits 1->0 136 98 72.06

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[2:1] No No No INPUT
data_i[6:3] Yes Yes T6,T94,T92 Yes T6,T94,T92 INPUT
data_i[7] No No No INPUT
data_i[15:8] Yes Yes T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[17:16] No No No INPUT
data_i[20:18] Yes Yes T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[21] No No No INPUT
data_i[22] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[23] No No No INPUT
data_i[28:24] Yes Yes T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[30:29] No No No INPUT
data_i[33:31] Yes Yes T6,T94,T92 Yes T6,T94,T92 INPUT
data_i[34] No No No INPUT
data_i[36:35] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[38:37] No No No INPUT
data_i[43:39] Yes Yes T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[44] No No No INPUT
data_i[45] Yes Yes *T6,*T94,*T92 Yes T6,T94,T92 INPUT
data_i[46] No No No INPUT
data_i[48:47] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[50:49] No No No INPUT
data_i[57:51] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[58] No No No INPUT
data_i[59] Yes Yes *T94,*T92,*T93 Yes T94,T92,T93 INPUT
data_i[60] No No No INPUT
data_i[62:61] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[63] No No No INPUT
data_i[71:64] Yes Yes T94,T92,T93 Yes T94,T92,T93 INPUT
data_o[0] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[2:1] No No No OUTPUT
data_o[6:3] Yes Yes T6,T94,T92 Yes T6,T94,T92 OUTPUT
data_o[7] No No No OUTPUT
data_o[15:8] Yes Yes T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[17:16] No No No OUTPUT
data_o[20:18] Yes Yes T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[21] No No No OUTPUT
data_o[22] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[23] No No No OUTPUT
data_o[28:24] Yes Yes T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[30:29] No No No OUTPUT
data_o[33:31] Yes Yes T6,T94,T92 Yes T6,T94,T92 OUTPUT
data_o[34] No No No OUTPUT
data_o[36:35] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[38:37] No No No OUTPUT
data_o[43:39] Yes Yes T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[44] No No No OUTPUT
data_o[45] Yes Yes *T6,*T94,*T92 Yes T6,T94,T92 OUTPUT
data_o[46] No No No OUTPUT
data_o[48:47] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[50:49] No No No OUTPUT
data_o[57:51] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[58] No No No OUTPUT
data_o[59] Yes Yes *T94,*T92,*T93 Yes T94,T92,T93 OUTPUT
data_o[60] No No No OUTPUT
data_o[62:61] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 204 75.00
Total Bits 0->1 136 102 75.00
Total Bits 1->0 136 102 75.00

Ports 2 0 0.00
Port Bits 272 204 75.00
Port Bits 0->1 136 102 75.00
Port Bits 1->0 136 102 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[2:1] No No No INPUT
data_i[3] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[4] No No No INPUT
data_i[9:5] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[10] No No No INPUT
data_i[16:11] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[17] No No No INPUT
data_i[18] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[19] No No No INPUT
data_i[20] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[21] No No No INPUT
data_i[24:22] Yes Yes T6,T13,T94 Yes T6,T13,T94 INPUT
data_i[25] No No No INPUT
data_i[27:26] Yes Yes T6,T13,T94 Yes T6,T13,T94 INPUT
data_i[28] No No No INPUT
data_i[30:29] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[31] No No No INPUT
data_i[33:32] Yes Yes T6,T13,T94 Yes T6,T13,T94 INPUT
data_i[35:34] No No No INPUT
data_i[40:36] Yes Yes *T6,*T13,*T94 Yes T6,T13,T94 INPUT
data_i[41] No No No INPUT
data_i[48:42] Yes Yes T6,T13,*T36 Yes T6,T13,T36 INPUT
data_i[49] No No No INPUT
data_i[52:50] Yes Yes T6,T13,T94 Yes T6,T13,T94 INPUT
data_i[53] No No No INPUT
data_i[55:54] Yes Yes T6,T13,T94 Yes T6,T13,T94 INPUT
data_i[56] No No No INPUT
data_i[57] Yes Yes *T6,*T13,*T94 Yes T6,T13,T94 INPUT
data_i[58] No No No INPUT
data_i[71:59] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_o[0] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[2:1] No No No OUTPUT
data_o[3] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[4] No No No OUTPUT
data_o[9:5] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[10] No No No OUTPUT
data_o[16:11] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[17] No No No OUTPUT
data_o[18] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[19] No No No OUTPUT
data_o[20] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[21] No No No OUTPUT
data_o[24:22] Yes Yes T6,T13,T94 Yes T6,T13,T94 OUTPUT
data_o[25] No No No OUTPUT
data_o[27:26] Yes Yes T6,T13,T94 Yes T6,T13,T94 OUTPUT
data_o[28] No No No OUTPUT
data_o[30:29] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[31] No No No OUTPUT
data_o[33:32] Yes Yes T6,T13,T94 Yes T6,T13,T94 OUTPUT
data_o[35:34] No No No OUTPUT
data_o[40:36] Yes Yes *T6,*T13,*T94 Yes T6,T13,T94 OUTPUT
data_o[41] No No No OUTPUT
data_o[48:42] Yes Yes T6,T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[49] No No No OUTPUT
data_o[52:50] Yes Yes T6,T13,T94 Yes T6,T13,T94 OUTPUT
data_o[53] No No No OUTPUT
data_o[55:54] Yes Yes T6,T13,T94 Yes T6,T13,T94 OUTPUT
data_o[56] No No No OUTPUT
data_o[57] Yes Yes *T6,*T13,*T94 Yes T6,T13,T94 OUTPUT
data_o[58] No No No OUTPUT
data_o[63:59] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 204 75.00
Total Bits 0->1 136 102 75.00
Total Bits 1->0 136 102 75.00

Ports 2 0 0.00
Port Bits 272 204 75.00
Port Bits 0->1 136 102 75.00
Port Bits 1->0 136 102 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[2:0] No No No INPUT
data_i[11:3] Yes Yes T6,T13,*T36 Yes T6,T13,T36 INPUT
data_i[13:12] No No No INPUT
data_i[26:14] Yes Yes T6,T13,*T36 Yes T6,T13,T36 INPUT
data_i[27] No No No INPUT
data_i[28] Yes Yes *T6,*T13,*T94 Yes T6,T13,T94 INPUT
data_i[29] No No No INPUT
data_i[30] Yes Yes *T6,*T13,*T94 Yes T6,T13,T94 INPUT
data_i[31] No No No INPUT
data_i[41:32] Yes Yes T6,T13,T94 Yes T6,T13,T94 INPUT
data_i[44:42] No No No INPUT
data_i[46:45] Yes Yes T6,T13,T94 Yes T6,T13,T94 INPUT
data_i[48:47] No No No INPUT
data_i[53:49] Yes Yes T6,T94,T92 Yes T6,T94,T92 INPUT
data_i[55:54] No No No INPUT
data_i[59:56] Yes Yes T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[61:60] No No No INPUT
data_i[71:62] Yes Yes T6,T94,T92 Yes T6,T94,T92 INPUT
data_o[2:0] No No No OUTPUT
data_o[11:3] Yes Yes T6,T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[13:12] No No No OUTPUT
data_o[26:14] Yes Yes T6,T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[27] No No No OUTPUT
data_o[28] Yes Yes *T6,*T13,*T94 Yes T6,T13,T94 OUTPUT
data_o[29] No No No OUTPUT
data_o[30] Yes Yes *T6,*T13,*T94 Yes T6,T13,T94 OUTPUT
data_o[31] No No No OUTPUT
data_o[41:32] Yes Yes T6,T13,T94 Yes T6,T13,T94 OUTPUT
data_o[44:42] No No No OUTPUT
data_o[46:45] Yes Yes T6,T13,T94 Yes T6,T13,T94 OUTPUT
data_o[48:47] No No No OUTPUT
data_o[53:49] Yes Yes T6,T94,T92 Yes T6,T94,T92 OUTPUT
data_o[55:54] No No No OUTPUT
data_o[59:56] Yes Yes T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[61:60] No No No OUTPUT
data_o[63:62] Yes Yes T6,T94,T92 Yes T6,T94,T92 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 206 75.74
Total Bits 0->1 136 103 75.74
Total Bits 1->0 136 103 75.74

Ports 2 0 0.00
Port Bits 272 206 75.74
Port Bits 0->1 136 103 75.74
Port Bits 1->0 136 103 75.74

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[1] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[2] No No No INPUT
data_i[4:3] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[5] No No No INPUT
data_i[6] Yes Yes *T94,*T92,*T93 Yes T94,T92,T93 INPUT
data_i[7] No No No INPUT
data_i[16:8] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[17] No No No INPUT
data_i[18] Yes Yes *T94,*T92,*T93 Yes T94,T92,T93 INPUT
data_i[19] No No No INPUT
data_i[29:20] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[31:30] No No No INPUT
data_i[34:32] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[35] No No No INPUT
data_i[39:36] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[40] No No No INPUT
data_i[43:41] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[44] No No No INPUT
data_i[49:45] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[50] No No No INPUT
data_i[52:51] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[53] No No No INPUT
data_i[56:54] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[57] No No No INPUT
data_i[59:58] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[61:60] No No No INPUT
data_i[65:62] Yes Yes *T94,*T93,*T18 Yes T94,T92,T93 INPUT
data_i[66] No No No INPUT
data_i[71:67] Yes Yes T94,T92,T93 Yes T94,T92,T93 INPUT
data_o[0] No No No OUTPUT
data_o[1] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[2] No No No OUTPUT
data_o[4:3] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[5] No No No OUTPUT
data_o[6] Yes Yes *T94,*T92,*T93 Yes T94,T92,T93 OUTPUT
data_o[7] No No No OUTPUT
data_o[16:8] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[17] No No No OUTPUT
data_o[18] Yes Yes *T94,*T92,*T93 Yes T94,T92,T93 OUTPUT
data_o[19] No No No OUTPUT
data_o[29:20] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[31:30] No No No OUTPUT
data_o[34:32] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[35] No No No OUTPUT
data_o[39:36] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[40] No No No OUTPUT
data_o[43:41] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[44] No No No OUTPUT
data_o[49:45] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[50] No No No OUTPUT
data_o[52:51] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[53] No No No OUTPUT
data_o[56:54] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[57] No No No OUTPUT
data_o[59:58] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[61:60] No No No OUTPUT
data_o[63:62] Yes Yes T94,T93,T18 Yes T94,T92,T93 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 208 76.47
Total Bits 0->1 136 104 76.47
Total Bits 1->0 136 104 76.47

Ports 2 0 0.00
Port Bits 272 208 76.47
Port Bits 0->1 136 104 76.47
Port Bits 1->0 136 104 76.47

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[3:2] No No No INPUT
data_i[14:4] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[16:15] No No No INPUT
data_i[22:17] Yes Yes *T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[23] No No No INPUT
data_i[25:24] Yes Yes T13,T36,T94 Yes T13,T36,T94 INPUT
data_i[26] No No No INPUT
data_i[30:27] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[31] No No No INPUT
data_i[32] Yes Yes *T13,*T36,*T94 Yes T13,T36,T94 INPUT
data_i[33] No No No INPUT
data_i[36:34] Yes Yes *T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[37] No No No INPUT
data_i[40:38] Yes Yes *T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[41] No No No INPUT
data_i[45:42] Yes Yes T13,T36,T94 Yes T13,T36,T94 INPUT
data_i[46] No No No INPUT
data_i[49:47] Yes Yes *T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[50] No No No INPUT
data_i[51] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[52] No No No INPUT
data_i[55:53] Yes Yes T13,T36,T94 Yes T13,T36,T94 INPUT
data_i[58:56] No No No INPUT
data_i[71:59] Yes Yes T13,T36,T94 Yes T13,T36,T94 INPUT
data_o[1:0] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[3:2] No No No OUTPUT
data_o[14:4] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[16:15] No No No OUTPUT
data_o[22:17] Yes Yes *T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[23] No No No OUTPUT
data_o[25:24] Yes Yes T13,T36,T94 Yes T13,T36,T94 OUTPUT
data_o[26] No No No OUTPUT
data_o[30:27] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[31] No No No OUTPUT
data_o[32] Yes Yes *T13,*T36,*T94 Yes T13,T36,T94 OUTPUT
data_o[33] No No No OUTPUT
data_o[36:34] Yes Yes *T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[37] No No No OUTPUT
data_o[40:38] Yes Yes *T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[41] No No No OUTPUT
data_o[45:42] Yes Yes T13,T36,T94 Yes T13,T36,T94 OUTPUT
data_o[46] No No No OUTPUT
data_o[49:47] Yes Yes *T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[50] No No No OUTPUT
data_o[51] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[52] No No No OUTPUT
data_o[55:53] Yes Yes T13,T36,T94 Yes T13,T36,T94 OUTPUT
data_o[58:56] No No No OUTPUT
data_o[63:59] Yes Yes T13,T36,T94 Yes T13,T36,T94 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 214 78.68
Total Bits 0->1 136 107 78.68
Total Bits 1->0 136 107 78.68

Ports 2 0 0.00
Port Bits 272 214 78.68
Port Bits 0->1 136 107 78.68
Port Bits 1->0 136 107 78.68

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[3:0] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[4] No No No INPUT
data_i[13:5] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 INPUT
data_i[16:14] No No No INPUT
data_i[18:17] Yes Yes T36,T94,T99 Yes T36,T94,T92 INPUT
data_i[20:19] No No No INPUT
data_i[32:21] Yes Yes T36,T94,T99 Yes T36,T94,T92 INPUT
data_i[33] No No No INPUT
data_i[37:34] Yes Yes T36,T94,T99 Yes T36,T94,T92 INPUT
data_i[38] No No No INPUT
data_i[46:39] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 INPUT
data_i[47] No No No INPUT
data_i[50:48] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 INPUT
data_i[51] No No No INPUT
data_i[52] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[54:53] No No No INPUT
data_i[57:55] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 INPUT
data_i[58] No No No INPUT
data_i[59] Yes Yes *T36,*T94,*T99 Yes T36,T94,T92 INPUT
data_i[60] No No No INPUT
data_i[68:61] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[69] No No No INPUT
data_i[71:70] Yes Yes T6,T13,T92 Yes T6,T13,T92 INPUT
data_o[3:0] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[4] No No No OUTPUT
data_o[13:5] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 OUTPUT
data_o[16:14] No No No OUTPUT
data_o[18:17] Yes Yes T36,T94,T99 Yes T36,T94,T92 OUTPUT
data_o[20:19] No No No OUTPUT
data_o[32:21] Yes Yes T36,T94,T99 Yes T36,T94,T92 OUTPUT
data_o[33] No No No OUTPUT
data_o[37:34] Yes Yes T36,T94,T99 Yes T36,T94,T92 OUTPUT
data_o[38] No No No OUTPUT
data_o[46:39] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 OUTPUT
data_o[47] No No No OUTPUT
data_o[50:48] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 OUTPUT
data_o[51] No No No OUTPUT
data_o[52] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[54:53] No No No OUTPUT
data_o[57:55] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 OUTPUT
data_o[58] No No No OUTPUT
data_o[59] Yes Yes *T36,*T94,*T99 Yes T36,T94,T92 OUTPUT
data_o[60] No No No OUTPUT
data_o[63:61] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 220 80.88
Total Bits 0->1 136 110 80.88
Total Bits 1->0 136 110 80.88

Ports 2 0 0.00
Port Bits 272 220 80.88
Port Bits 0->1 136 110 80.88
Port Bits 1->0 136 110 80.88

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[1] No No No INPUT
data_i[6:2] Yes Yes T6,T13,*T36 Yes T6,T13,T36 INPUT
data_i[7] No No No INPUT
data_i[8] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[10:9] No No No INPUT
data_i[18:11] Yes Yes T6,T13,T94 Yes T6,T13,T94 INPUT
data_i[19] No No No INPUT
data_i[23:20] Yes Yes T6,T13,*T36 Yes T6,T13,T36 INPUT
data_i[24] No No No INPUT
data_i[25] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[27:26] No No No INPUT
data_i[30:28] Yes Yes T6,T13,T94 Yes T6,T13,T94 INPUT
data_i[31] No No No INPUT
data_i[36:32] Yes Yes T6,T13,*T36 Yes T6,T13,T36 INPUT
data_i[37] No No No INPUT
data_i[40:38] Yes Yes T6,T13,*T36 Yes T6,T13,T36 INPUT
data_i[42:41] No No No INPUT
data_i[60:43] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[61] No No No INPUT
data_i[71:62] Yes Yes T114,T6,T13 Yes T114,T6,T13 INPUT
data_o[0] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[1] No No No OUTPUT
data_o[6:2] Yes Yes T6,T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[7] No No No OUTPUT
data_o[8] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[10:9] No No No OUTPUT
data_o[18:11] Yes Yes T6,T13,T94 Yes T6,T13,T94 OUTPUT
data_o[19] No No No OUTPUT
data_o[23:20] Yes Yes T6,T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[24] No No No OUTPUT
data_o[25] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[27:26] No No No OUTPUT
data_o[30:28] Yes Yes T6,T13,T94 Yes T6,T13,T94 OUTPUT
data_o[31] No No No OUTPUT
data_o[36:32] Yes Yes T6,T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[37] No No No OUTPUT
data_o[40:38] Yes Yes T6,T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[42:41] No No No OUTPUT
data_o[60:43] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[61] No No No OUTPUT
data_o[63:62] Yes Yes T114 Yes T114 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 224 82.35
Total Bits 0->1 136 112 82.35
Total Bits 1->0 136 112 82.35

Ports 2 0 0.00
Port Bits 272 224 82.35
Port Bits 0->1 136 112 82.35
Port Bits 1->0 136 112 82.35

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[3:0] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[5:4] No No No INPUT
data_i[9:6] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 INPUT
data_i[10] No No No INPUT
data_i[13:11] Yes Yes *T44,*T86,*T36 Yes T44,T86,T36 INPUT
data_i[14] No No No INPUT
data_i[16:15] Yes Yes T36,T94,T93 Yes T36,T94,T92 INPUT
data_i[17] No No No INPUT
data_i[19:18] Yes Yes T36,T94,T93 Yes T36,T94,T92 INPUT
data_i[20] No No No INPUT
data_i[21] Yes Yes *T36,*T94,*T93 Yes T36,T94,T92 INPUT
data_i[22] No No No INPUT
data_i[27:23] Yes Yes T36,T94,T93 Yes T36,T94,T92 INPUT
data_i[28] No No No INPUT
data_i[32:29] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[33] No No No INPUT
data_i[35:34] Yes Yes T6,T13,T36 Yes T6,T13,T36 INPUT
data_i[36] No No No INPUT
data_i[44:37] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 INPUT
data_i[45] No No No INPUT
data_i[52:46] Yes Yes *T36,*T94,*T93 Yes T36,T94,T92 INPUT
data_i[53] No No No INPUT
data_i[71:54] Yes Yes T36,T94,T99 Yes T36,T94,T92 INPUT
data_o[3:0] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[5:4] No No No OUTPUT
data_o[9:6] Yes Yes *T6,*T13,T36 Yes T6,T13,T36 OUTPUT
data_o[10] No No No OUTPUT
data_o[13:11] Yes Yes *T44,*T86,*T36 Yes T44,T86,T36 OUTPUT
data_o[14] No No No OUTPUT
data_o[16:15] Yes Yes T36,T94,T93 Yes T36,T94,T92 OUTPUT
data_o[17] No No No OUTPUT
data_o[19:18] Yes Yes T36,T94,T93 Yes T36,T94,T92 OUTPUT
data_o[20] No No No OUTPUT
data_o[21] Yes Yes *T36,*T94,*T93 Yes T36,T94,T92 OUTPUT
data_o[22] No No No OUTPUT
data_o[27:23] Yes Yes T36,T94,T93 Yes T36,T94,T92 OUTPUT
data_o[28] No No No OUTPUT
data_o[32:29] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[33] No No No OUTPUT
data_o[35:34] Yes Yes T6,T13,T36 Yes T6,T13,T36 OUTPUT
data_o[36] No No No OUTPUT
data_o[44:37] Yes Yes *T6,*T13,*T36 Yes T6,T13,T36 OUTPUT
data_o[45] No No No OUTPUT
data_o[52:46] Yes Yes *T36,*T94,*T93 Yes T36,T94,T92 OUTPUT
data_o[53] No No No OUTPUT
data_o[63:54] Yes Yes T36,T94,T99 Yes T36,T94,T92 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T92,T93,T99 Yes T92,T93,T99 INPUT
data_o[63:0] Yes Yes T92,T93,T99 Yes T92,T93,T99 OUTPUT
syndrome_o[2:0] Yes Yes T110,T173,T174 Yes T110,T173,T174 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T110,*T173,*T174 Yes T110,T173,T174 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T99,T104,T118 Yes T99,T104,T118 INPUT
data_o[63:0] Yes Yes T99,T104,T118 Yes T99,T104,T118 OUTPUT
syndrome_o[2:0] Yes Yes T109,T174,T183 Yes T109,T174,T183 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T109,*T174,*T183 Yes T109,T174,T183 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T6,T36,T94 Yes T6,T36,T94 INPUT
data_o[63:0] Yes Yes T6,T36,T94 Yes T6,T36,T94 OUTPUT
syndrome_o[2:0] Yes Yes T109,T110,T173 Yes T109,T110,T173 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T109,*T110,*T173 Yes T109,T110,T173 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T6,T36,T100 Yes T6,T36,T100 INPUT
data_o[63:0] Yes Yes T6,T36,T100 Yes T6,T36,T100 OUTPUT
syndrome_o[2:0] Yes Yes T173,T189,T183 Yes T173,T189,T183 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T173,*T189,*T183 Yes T173,T189,T183 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T99,T18,T100 Yes T99,T18,T100 INPUT
data_o[63:0] Yes Yes T99,T18,T100 Yes T99,T18,T100 OUTPUT
syndrome_o[2:0] Yes Yes T109,T110,T189 Yes T109,T110,T189 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T109,*T110,*T189 Yes T109,T110,T189 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T144,T194,T276 Yes T3,T210,T144 INPUT
data_o[63:0] Yes Yes T144,T194,T276 Yes T3,T210,T144 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T99,T115,T18 Yes T99,T115,T18 INPUT
data_o[63:0] Yes Yes T99,T115,T18 Yes T99,T115,T18 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T277,T278,T264 Yes T277,T215,T279 INPUT
data_o[63:0] Yes Yes T277,T278,T264 Yes T277,T215,T279 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T93,T277,T185 Yes T93,T277,T215 INPUT
data_o[63:0] Yes Yes T93,T277,T185 Yes T93,T277,T215 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T9,T128,T249 Yes T9,T128,T249 INPUT
data_o[63:0] Yes Yes T9,T128,T249 Yes T9,T128,T249 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T144,T271,T280 Yes T144,T271,T280 INPUT
data_o[63:0] Yes Yes T144,T271,T280 Yes T144,T271,T280 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T218,T194,T224 Yes T218,T194,T224 INPUT
data_o[63:0] Yes Yes T218,T194,T224 Yes T218,T194,T224 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T119,T218,T219 Yes T119,T218,T219 INPUT
data_o[63:0] Yes Yes T119,T218,T219 Yes T119,T218,T219 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T13,T94,T93 Yes T13,T94,T93 INPUT
data_o[63:0] Yes Yes T13,T94,T93 Yes T13,T94,T93 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T5,T36,T99 Yes T4,T5,T36 INPUT
data_o[63:0] Yes Yes T5,T36,T99 Yes T4,T5,T36 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T11,T13,T36 Yes T11,T13,T36 INPUT
data_o[63:0] Yes Yes T11,T13,T36 Yes T11,T13,T36 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T13,T115,T104 Yes T13,T115,T104 INPUT
data_o[63:0] Yes Yes T13,T115,T104 Yes T13,T115,T104 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T9,T106,T249 Yes T9,T106,T249 INPUT
data_o[63:0] Yes Yes T9,T106,T249 Yes T9,T106,T249 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T5,T11,T115 Yes T5,T11,T115 INPUT
data_o[63:0] Yes Yes T5,T11,T115 Yes T5,T11,T115 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T118,T119,T9 Yes T97,T118,T119 INPUT
data_o[63:0] Yes Yes T118,T119,T9 Yes T97,T118,T119 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T93,T18,T96 Yes T93,T18,T96 INPUT
data_o[63:0] Yes Yes T93,T18,T96 Yes T93,T18,T96 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T36,T94,T104 Yes T36,T94,T104 INPUT
data_o[63:0] Yes Yes T36,T94,T104 Yes T36,T94,T104 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T9,T165,T41 Yes T19,T9,T165 INPUT
data_o[63:0] Yes Yes T9,T165,T41 Yes T19,T9,T165 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T36,T126,T115 Yes T6,T36,T126 INPUT
data_o[63:0] Yes Yes T36,T126,T115 Yes T6,T36,T126 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T100,T121,T141 Yes T100,T121,T210 INPUT
data_o[63:0] Yes Yes T100,T121,T141 Yes T100,T121,T210 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T5,T99,T19 Yes T3,T5,T99 INPUT
data_o[63:0] Yes Yes T5,T99,T19 Yes T3,T5,T99 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T94,T99,T18 Yes T94,T97,T99 INPUT
data_o[63:0] Yes Yes T94,T99,T18 Yes T94,T97,T99 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T13,T36,T99 Yes T5,T13,T36 INPUT
data_o[63:0] Yes Yes T13,T36,T99 Yes T5,T13,T36 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T85,T18,T121 Yes T85,T18,T121 INPUT
data_o[63:0] Yes Yes T85,T18,T121 Yes T85,T18,T121 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T5,T92,T18 Yes T5,T92,T18 INPUT
data_o[63:0] Yes Yes T5,T92,T18 Yes T5,T92,T18 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T97,T92,T117 Yes T4,T97,T92 INPUT
data_o[63:0] Yes Yes T97,T92,T117 Yes T4,T97,T92 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T92,T18,T144 Yes T92,T18,T144 INPUT
data_o[63:0] Yes Yes T92,T18,T144 Yes T92,T18,T144 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T94,T115,T18 Yes T94,T115,T18 INPUT
data_o[63:0] Yes Yes T94,T115,T18 Yes T94,T115,T18 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T118,T20,T120 Yes T118,T20,T120 INPUT
data_o[63:0] Yes Yes T118,T20,T120 Yes T118,T20,T120 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T5,T9,T219 Yes T5,T9,T219 INPUT
data_o[63:0] Yes Yes T5,T9,T219 Yes T5,T9,T219 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T210,T213,T279 Yes T210,T194,T213 INPUT
data_o[63:0] Yes Yes T210,T213,T279 Yes T210,T194,T213 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T115,T19,T146 Yes T115,T19,T146 INPUT
data_o[63:0] Yes Yes T115,T19,T146 Yes T115,T19,T146 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T5,T18,T218 Yes T5,T18,T117 INPUT
data_o[63:0] Yes Yes T5,T18,T218 Yes T5,T18,T117 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T36,T93,T115 Yes T36,T97,T93 INPUT
data_o[63:0] Yes Yes T36,T93,T115 Yes T36,T97,T93 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%