Unified Coverage Report :: Module :: otp_ctrl_lci

Module : otp_ctrl_lci

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lci	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_otp_ctrl_lci

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	94.16	95.24	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : otp_ctrl_lci

	Line No.	Total	Covered	Percent
TOTAL		52	52	100.00
CONT_ASSIGN	114	1	1	100.00
ALWAYS	117	41	41	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
ALWAYS	274	3	3	100.00
ALWAYS	277	3	3	100.00

113                       // Output LCI errors
114        1/1            assign error_o = error_q;
           Tests:       T1 T2 T3 
115                     
116                       always_comb begin : p_fsm
117        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
118                     
119                         // Counter
120        1/1              cnt_en   = 1'b0;
           Tests:       T1 T2 T3 
121        1/1              cnt_clr  = 1'b0;
           Tests:       T1 T2 T3 
122                     
123                         // Idle status
124        1/1              lci_prog_idle_o = 1'b1;
           Tests:       T1 T2 T3 
125                     
126                         // OTP signals
127        1/1              otp_req_o = 1'b0;
           Tests:       T1 T2 T3 
128        1/1              otp_cmd_o = prim_otp_pkg::Read;
           Tests:       T1 T2 T3 
129                     
130                         // Response to LC controller
131        1/1              lc_err_o = 1'b0;
           Tests:       T1 T2 T3 
132        1/1              lc_ack_o = 1'b0;
           Tests:       T1 T2 T3 
133                     
134                         // Error Register
135        1/1              error_d = error_q;
           Tests:       T1 T2 T3 
136        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
137                     
138        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
139                           ///////////////////////////////////////////////////////////////////
140                           // State right after reset. Wait here until LCI gets enabled.
141                           ResetSt: begin
142        1/1                  lci_prog_idle_o = 1'b0;
           Tests:       T1 T2 T3 
143        1/1                  if (lci_en_i) begin
           Tests:       T1 T2 T3 
144        1/1                    state_d = IdleSt;
           Tests:       T1 T2 T3 
145                             end
                        MISSING_ELSE
146                           end
147                           ///////////////////////////////////////////////////////////////////
148                           // Wait for a request from the life cycle controller
149                           IdleSt: begin
150        1/1                  if (lc_req_i) begin
           Tests:       T1 T2 T3 
151        1/1                    state_d = WriteSt;
           Tests:       T3 T5 T10 
152        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T5 T10 
153                             end
                        MISSING_ELSE
154                           end
155                           ///////////////////////////////////////////////////////////////////
156                           // Loop through the lifecycle sate and burn in all words.
157                           // If the write data contains a 0 bit in a position where a bit has already been
158                           // programmed to 1 before, the OTP errors out.
159                           WriteSt: begin
160        1/1                  otp_req_o = 1'b1;
           Tests:       T3 T5 T10 
161        1/1                  otp_cmd_o = prim_otp_pkg::Write;
           Tests:       T3 T5 T10 
162        1/1                  lci_prog_idle_o = 1'b0;
           Tests:       T3 T5 T10 
163        1/1                  if (otp_gnt_i) begin
           Tests:       T3 T5 T10 
164        1/1                    state_d = WriteWaitSt;
           Tests:       T3 T5 T10 
165                             end
                        MISSING_ELSE
166                           end
167                           ///////////////////////////////////////////////////////////////////
168                           // Wait for OTP response, and check whether there are more words to burn in.
169                           // In case an OTP transaction fails, latch the OTP error code, and jump to
170                           // terminal error state.
171                           WriteWaitSt: begin
172        1/1                  lci_prog_idle_o = 1'b0;
           Tests:       T3 T5 T10 
173        1/1                  if (otp_rvalid_i) begin
           Tests:       T3 T5 T10 
174                               // Check OTP return code.
175                               // Note that if errors occur, we aggregate the error code
176                               // but still attempt to program all remaining words.
177                               // This is done to ensure that a life cycle state with
178                               // ECC correctable errors in some words can still be scrapped.
179        1/1                    if (otp_err_e'(otp_err_i) != NoError) begin
           Tests:       T3 T5 T10 
180        1/1                      error_d = otp_err_e'(otp_err_i);
           Tests:       T236 T259 T167 
181                               end
                        MISSING_ELSE
182                     
183                               // Check whether we programmed all OTP words.
184                               // If yes, we are done and can go back to idle.
185        1/1                    if (cnt == LastLcOtpWord) begin
           Tests:       T3 T5 T10 
186        1/1                      state_d = IdleSt;
           Tests:       T3 T5 T10 
187        1/1                      lc_ack_o = 1'b1;
           Tests:       T3 T5 T10 
188                                 // If in any of the words a programming error has occurred,
189                                 // we signal that accordingly and go to the error state.
190        1/1                      if (error_d != NoError) begin
           Tests:       T3 T5 T10 
191        1/1                        lc_err_o = 1'b1;
           Tests:       T236 T259 T167 
192        1/1                        state_d = ErrorSt;
           Tests:       T236 T259 T167 
193                                 end
                        MISSING_ELSE
194                               // Otherwise we increase the OTP word counter.
195                               end else begin
196        1/1                      state_d = WriteSt;
           Tests:       T3 T5 T10 
197        1/1                      cnt_en = 1'b1;
           Tests:       T3 T5 T10 
198                               end
199                             end
                        MISSING_ELSE
200                           end
201                           ///////////////////////////////////////////////////////////////////
202                           // Terminal Error State. This locks access to the partition.
203                           // Make sure the partition signals an error state if no error
204                           // code has been latched so far, and lock the buffer regs down.
205                           ErrorSt: begin
206        1/1                  if (error_q == NoError) begin
           Tests:       T2 T4 T44 
207        1/1                    error_d = FsmStateError;
           Tests:       T25 T26 T27 
208                             end
                        MISSING_ELSE
209                           end
210                           ///////////////////////////////////////////////////////////////////
211                           // We should never get here. If we do (e.g. via a malicious
212                           // glitch), error out immediately.
213                           default: begin
214                             state_d = ErrorSt;
215                             fsm_err_o = 1'b1;
216                           end
217                           ///////////////////////////////////////////////////////////////////
218                         endcase // state_q
219                     
220                         // Unconditionally jump into the terminal error state in case of escalation.
221                         // SEC_CM: LCI.FSM.LOCAL_ESC, LCI.FSM.GLOBAL_ESC
222        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err) begin
           Tests:       T1 T2 T3 
223        1/1                state_d = ErrorSt;
           Tests:       T2 T4 T44 
224        1/1                fsm_err_o = 1'b1;
           Tests:       T2 T4 T44 
225        1/1                if (error_q == NoError) begin
           Tests:       T2 T4 T44 
226        1/1                  error_d = FsmStateError;
           Tests:       T2 T4 T44 
227                           end
                        MISSING_ELSE
228                         end
                        MISSING_ELSE
229                     
230                       end
231                     
232                       //////////////////////////////
233                       // Counter and address calc //
234                       //////////////////////////////
235                     
236                       // Native OTP word counter
237                       // SEC_CM: LCI.CTR.REDUN
238                       prim_count #(
239                         .Width(CntWidth)
240                       ) u_prim_count (
241                         .clk_i,
242                         .rst_ni,
243                         .clr_i(cnt_clr),
244                         .set_i(1'b0),
245                         .set_cnt_i('0),
246                         .incr_en_i(cnt_en),
247                         .decr_en_i(1'b0),
248                         .step_i(CntWidth'(1)),
249                         .commit_i(1'b1),
250                         .cnt_o(cnt),
251                         .cnt_after_commit_o(),
252                         .err_o(cnt_err)
253                       );
254                     
255                       // The output address is "offset + count", but we have to convert Info.offset from a byte address
256                       // to a halfword (16-bit) address by discarding the bottom OtpAddrShift bits. We also make the
257                       // zero-extension of cnt explicit (to avoid width mismatch warnings).
258        1/1            assign otp_addr_o = Info.offset[OtpByteAddrWidth-1:OtpAddrShift] + OtpAddrWidth'(cnt);
           Tests:       T1 T2 T3 
259                     
260                       // Always transfer 16bit blocks.
261                       assign otp_size_o = '0;
262                     
263                       logic [NumLcOtpWords-1:0][OtpWidth-1:0] data;
264        1/1            assign data        = lc_data_i;
           Tests:       T3 T5 T10 
265        1/1            assign otp_wdata_o = (otp_req_o) ? OtpIfWidth'(data[cnt]) : '0;
           Tests:       T1 T2 T3 
266                     
267                       logic unused_rdata;
268        1/1            assign unused_rdata = ^otp_rdata_i;
           Tests:       T1 T2 T3 
269                     
270                       ///////////////
271                       // Registers //
272                       ///////////////
273                     
274        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
274.1                   `ifdef SIMULATION                                   
274.2                       prim_sparse_fsm_flop #(                           
274.3                         .StateEnumT(state_e),                            
274.4                         .Width($bits(state_e)),                          
274.5                         .ResetValue($bits(state_e)'(ResetSt)),          
274.6                         .EnableAlertTriggerSVA(1), 
274.7                         .CustomForceName("state_q")          
274.8                       ) u_state_regs (                                        
274.9                         .clk_i   ( clk_i   ),                           
274.10                        .rst_ni  ( rst_ni ),                           
274.11                        .state_i ( state_d     ),                           
274.12                        .state_o (         )                            
274.13                      );                                                
274.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
274.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
274.16     1/1                state_q <= ResetSt;                                
           Tests:       T1 T2 T3 
274.17                      end else begin                                    
274.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
274.19                      end                                               
274.20                    end  
274.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
274.22                      else begin                                                                           
274.23                        `ifdef UVM                                                                               
274.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
274.25                                              "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv", 274, "", 1);                                
274.26                  `else                                                                                    
274.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
274.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
274.29                  `endif                                                              
274.30                      end 
274.31                    `else                                               
274.32                      prim_sparse_fsm_flop #(                           
274.33                        .StateEnumT(state_e),                            
274.34                        .Width($bits(state_e)),                          
274.35                        .ResetValue($bits(state_e)'(ResetSt)),          
274.36                        .EnableAlertTriggerSVA(1)  
274.37                      ) u_state_regs (                                        
274.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
274.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
274.40                        .state_i ( state_d     ),                           
274.41                        .state_o ( state_q     )                            
274.42                      );                                                
274.43                    `endif275                     
276                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
277        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
278        1/1                error_q <= NoError;
           Tests:       T1 T2 T3 
279                         end else begin
280        1/1                error_q <= error_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : otp_ctrl_lci

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       179
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T3,T5,T10
1	Covered	T236,T259,T167

 LINE       185
 EXPRESSION (cnt == LastLcOtpWord)
            -----------1----------

-1-	Status	Tests
0	Covered	T3,T5,T10
1	Covered	T3,T5,T10

 LINE       190
 EXPRESSION (error_d != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T10
1	Covered	T236,T259,T167

 LINE       206
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T44
1	Covered	T25,T26,T27

 LINE       225
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T44
1	Covered	T2,T4,T44

 LINE       265
 EXPRESSION (otp_req_o ? (64'(data[cnt])) : '0)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T10

---

FSM Coverage for Module : otp_ctrl_lci

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	9	9	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	192	Covered	T2,T4,T44
IdleSt	144	Covered	T1,T2,T3
ResetSt	141	Covered	T1,T2,T3
WriteSt	151	Covered	T3,T5,T10
WriteWaitSt	164	Covered	T3,T5,T10

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	223	Covered	T4,T34,T134
IdleSt->WriteSt	151	Covered	T3,T5,T10
ResetSt->ErrorSt	223	Covered	T2,T44,T31
ResetSt->IdleSt	144	Covered	T1,T2,T3
WriteSt->ErrorSt	223	Covered	T164,T350,T351
WriteSt->WriteWaitSt	164	Covered	T3,T5,T10
WriteWaitSt->ErrorSt	192	Covered	T9,T14,T236
WriteWaitSt->IdleSt	186	Covered	T3,T5,T10
WriteWaitSt->WriteSt	196	Covered	T3,T5,T10

---

Branch Coverage for Module : otp_ctrl_lci

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	265	2	2	100.00
CASE	138	15	15	100.00
IF	222	3	3	100.00
IF	274	2	2	100.00
IF	277	2	2	100.00

265          assign otp_wdata_o = (otp_req_o) ? OtpIfWidth'(data[cnt]) : '0;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T10
0	Covered	T1,T2,T3

138            unique case (state_q)
                      -1-  
139              ///////////////////////////////////////////////////////////////////
140              // State right after reset. Wait here until LCI gets enabled.
141              ResetSt: begin
142                lci_prog_idle_o = 1'b0;
143                if (lci_en_i) begin
                   -2-  
144                  state_d = IdleSt;
                     ==>
145                end
                   MISSING_ELSE
                   ==>
146              end
147              ///////////////////////////////////////////////////////////////////
148              // Wait for a request from the life cycle controller
149              IdleSt: begin
150                if (lc_req_i) begin
                   -3-  
151                  state_d = WriteSt;
                     ==>
152                  cnt_clr = 1'b1;
153                end
                   MISSING_ELSE
                   ==>
154              end
155              ///////////////////////////////////////////////////////////////////
156              // Loop through the lifecycle sate and burn in all words.
157              // If the write data contains a 0 bit in a position where a bit has already been
158              // programmed to 1 before, the OTP errors out.
159              WriteSt: begin
160                otp_req_o = 1'b1;
161                otp_cmd_o = prim_otp_pkg::Write;
162                lci_prog_idle_o = 1'b0;
163                if (otp_gnt_i) begin
                   -4-  
164                  state_d = WriteWaitSt;
                     ==>
165                end
                   MISSING_ELSE
                   ==>
166              end
167              ///////////////////////////////////////////////////////////////////
168              // Wait for OTP response, and check whether there are more words to burn in.
169              // In case an OTP transaction fails, latch the OTP error code, and jump to
170              // terminal error state.
171              WriteWaitSt: begin
172                lci_prog_idle_o = 1'b0;
173                if (otp_rvalid_i) begin
                   -5-  
174                  // Check OTP return code.
175                  // Note that if errors occur, we aggregate the error code
176                  // but still attempt to program all remaining words.
177                  // This is done to ensure that a life cycle state with
178                  // ECC correctable errors in some words can still be scrapped.
179                  if (otp_err_e'(otp_err_i) != NoError) begin
                     -6-  
180                    error_d = otp_err_e'(otp_err_i);
                       ==>
181                  end
                     MISSING_ELSE
                     ==>
182        
183                  // Check whether we programmed all OTP words.
184                  // If yes, we are done and can go back to idle.
185                  if (cnt == LastLcOtpWord) begin
                     -7-  
186                    state_d = IdleSt;
187                    lc_ack_o = 1'b1;
188                    // If in any of the words a programming error has occurred,
189                    // we signal that accordingly and go to the error state.
190                    if (error_d != NoError) begin
                       -8-  
191                      lc_err_o = 1'b1;
                         ==>
192                      state_d = ErrorSt;
193                    end
                       MISSING_ELSE
                       ==>
194                  // Otherwise we increase the OTP word counter.
195                  end else begin
196                    state_d = WriteSt;
                       ==>
197                    cnt_en = 1'b1;
198                  end
199                end
                   MISSING_ELSE
                   ==>
200              end
201              ///////////////////////////////////////////////////////////////////
202              // Terminal Error State. This locks access to the partition.
203              // Make sure the partition signals an error state if no error
204              // code has been latched so far, and lock the buffer regs down.
205              ErrorSt: begin
206                if (error_q == NoError) begin
                   -9-  
207                  error_d = FsmStateError;
                     ==>
208                end
                   MISSING_ELSE
                   ==>
209              end
210              ///////////////////////////////////////////////////////////////////
211              // We should never get here. If we do (e.g. via a malicious
212              // glitch), error out immediately.
213              default: begin
214                state_d = ErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	1	-	-	-	-	-	-	Covered	T3,T5,T10
IdleSt	-	0	-	-	-	-	-	-	Covered	T1,T2,T3
WriteSt	-	-	1	-	-	-	-	-	Covered	T3,T5,T10
WriteSt	-	-	0	-	-	-	-	-	Covered	T10,T135,T92
WriteWaitSt	-	-	-	1	1	-	-	-	Covered	T236,T259,T167
WriteWaitSt	-	-	-	1	0	-	-	-	Covered	T3,T5,T10
WriteWaitSt	-	-	-	1	-	1	1	-	Covered	T236,T259,T167
WriteWaitSt	-	-	-	1	-	1	0	-	Covered	T3,T5,T10
WriteWaitSt	-	-	-	1	-	0	-	-	Covered	T3,T5,T10
WriteWaitSt	-	-	-	0	-	-	-	-	Covered	T3,T5,T10
ErrorSt	-	-	-	-	-	-	-	1	Covered	T25,T26,T27
ErrorSt	-	-	-	-	-	-	-	0	Covered	T2,T4,T44
default	-	-	-	-	-	-	-	-	Covered	T25,T26,T27

222            if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err) begin
               -1-  
223              state_d = ErrorSt;
224              fsm_err_o = 1'b1;
225              if (error_q == NoError) begin
                 -2-  
226                error_d = FsmStateError;
                   ==>
227              end
                 MISSING_ELSE
                 ==>
228            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T4,T44
1	0	Covered	T2,T4,T44
0	-	Covered	T1,T2,T3

274          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

277            if (!rst_ni) begin
               -1-  
278              error_q <= NoError;
                 ==>
279            end else begin
280              error_q <= error_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_lci

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorKnown_A	89726523	88857865	0	0
LcAckKnown_A	89726523	88857865	0	0
LcErrKnown_A	89726523	88857865	0	0
LcValueMustBeWiderThanNativeOtpWidth_A	1125	1125	0	0
LciIdleKnown_A	89726523	88857865	0	0
OtpAddrKnown_A	89726523	88857865	0	0
OtpCmdKnown_A	89726523	88857865	0	0
OtpReqKnown_A	89726523	88857865	0	0
OtpSizeKnown_A	89726523	88857865	0	0
OtpWdataKnown_A	89726523	88857865	0	0
u_state_regs_A	89726523	88857865	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89726523	88857865	0	0
T1	5293	5240	0	0
T2	13907	13652	0	0
T3	29717	29128	0	0
T4	11256	11009	0	0
T5	10792	10585	0	0
T6	11064	10876	0	0
T10	9933	9573	0	0
T11	5474	5411	0	0
T12	37955	37880	0	0
T13	5678	5601	0	0

LcAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89726523	88857865	0	0
T1	5293	5240	0	0
T2	13907	13652	0	0
T3	29717	29128	0	0
T4	11256	11009	0	0
T5	10792	10585	0	0
T6	11064	10876	0	0
T10	9933	9573	0	0
T11	5474	5411	0	0
T12	37955	37880	0	0
T13	5678	5601	0	0

LcErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89726523	88857865	0	0
T1	5293	5240	0	0
T2	13907	13652	0	0
T3	29717	29128	0	0
T4	11256	11009	0	0
T5	10792	10585	0	0
T6	11064	10876	0	0
T10	9933	9573	0	0
T11	5474	5411	0	0
T12	37955	37880	0	0
T13	5678	5601	0	0

LcValueMustBeWiderThanNativeOtpWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1125	1125	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

LciIdleKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89726523	88857865	0	0
T1	5293	5240	0	0
T2	13907	13652	0	0
T3	29717	29128	0	0
T4	11256	11009	0	0
T5	10792	10585	0	0
T6	11064	10876	0	0
T10	9933	9573	0	0
T11	5474	5411	0	0
T12	37955	37880	0	0
T13	5678	5601	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89726523	88857865	0	0
T1	5293	5240	0	0
T2	13907	13652	0	0
T3	29717	29128	0	0
T4	11256	11009	0	0
T5	10792	10585	0	0
T6	11064	10876	0	0
T10	9933	9573	0	0
T11	5474	5411	0	0
T12	37955	37880	0	0
T13	5678	5601	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89726523	88857865	0	0
T1	5293	5240	0	0
T2	13907	13652	0	0
T3	29717	29128	0	0
T4	11256	11009	0	0
T5	10792	10585	0	0
T6	11064	10876	0	0
T10	9933	9573	0	0
T11	5474	5411	0	0
T12	37955	37880	0	0
T13	5678	5601	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89726523	88857865	0	0
T1	5293	5240	0	0
T2	13907	13652	0	0
T3	29717	29128	0	0
T4	11256	11009	0	0
T5	10792	10585	0	0
T6	11064	10876	0	0
T10	9933	9573	0	0
T11	5474	5411	0	0
T12	37955	37880	0	0
T13	5678	5601	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89726523	88857865	0	0
T1	5293	5240	0	0
T2	13907	13652	0	0
T3	29717	29128	0	0
T4	11256	11009	0	0
T5	10792	10585	0	0
T6	11064	10876	0	0
T10	9933	9573	0	0
T11	5474	5411	0	0
T12	37955	37880	0	0
T13	5678	5601	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89726523	88857865	0	0
T1	5293	5240	0	0
T2	13907	13652	0	0
T3	29717	29128	0	0
T4	11256	11009	0	0
T5	10792	10585	0	0
T6	11064	10876	0	0
T10	9933	9573	0	0
T11	5474	5411	0	0
T12	37955	37880	0	0
T13	5678	5601	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89726523	88857865	0	0
T1	5293	5240	0	0
T2	13907	13652	0	0
T3	29717	29128	0	0
T4	11256	11009	0	0
T5	10792	10585	0	0
T6	11064	10876	0	0
T10	9933	9573	0	0
T11	5474	5411	0	0
T12	37955	37880	0	0
T13	5678	5601	0	0