Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	94.16	95.24	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	92880410	361018	0	0
check_regwen_rd_A	92880410	1597	0	0
check_timeout_rd_A	92880410	826	0	0
check_trigger_regwen_rd_A	92880410	1788	0	0
consistency_check_period_rd_A	92880410	1563	0	0
creator_sw_cfg_read_lock_rd_A	92880410	855	0	0
direct_access_address_rd_A	92880410	189	0	0
direct_access_wdata_0_rd_A	92880410	20	0	0
direct_access_wdata_1_rd_A	92880410	30	0	0
integrity_check_period_rd_A	92880410	1615	0	0
intr_enable_rd_A	92880410	2227	0	0
owner_sw_cfg_read_lock_rd_A	92880410	923	0	0
rot_creator_auth_codesign_read_lock_rd_A	92880410	843	0	0
rot_creator_auth_state_read_lock_rd_A	92880410	825	0	0
vendor_test_read_lock_rd_A	92880410	823	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92880410	361018	0	0
T9	162911	4073	0	0
T14	0	4356	0	0
T15	0	2270	0	0
T20	0	3979	0	0
T21	0	4527	0	0
T22	0	2309	0	0
T42	13361	0	0	0
T60	13988	0	0	0
T70	156017	0	0	0
T93	0	2347	0	0
T96	0	5824	0	0
T148	43195	0	0	0
T184	59796	0	0	0
T233	6360	0	0	0
T244	80757	0	0	0
T271	0	4038	0	0
T287	31442	0	0	0
T314	0	2817	0	0
T315	15589	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92880410	1597	0	0
T97	218622	24	0	0
T173	0	24	0	0
T247	10417	0	0	0
T284	44090	0	0	0
T323	0	8	0	0
T330	0	240	0	0
T348	0	100	0	0
T352	0	19	0	0
T353	0	31	0	0
T354	0	29	0	0
T355	0	20	0	0
T356	0	17	0	0
T357	13141	0	0	0
T358	13812	0	0	0
T359	4690	0	0	0
T360	13383	0	0	0
T361	11948	0	0	0
T362	70342	0	0	0
T363	108661	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92880410	826	0	0
T97	218622	26	0	0
T98	0	15	0	0
T173	0	16	0	0
T247	10417	0	0	0
T284	44090	0	0	0
T330	0	241	0	0
T352	0	17	0	0
T353	0	15	0	0
T354	0	33	0	0
T355	0	5	0	0
T356	0	11	0	0
T357	13141	0	0	0
T358	13812	0	0	0
T359	4690	0	0	0
T360	13383	0	0	0
T361	11948	0	0	0
T362	70342	0	0	0
T363	108661	0	0	0
T364	0	7	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92880410	1788	0	0
T97	218622	24	0	0
T98	0	7	0	0
T173	0	16	0	0
T247	10417	0	0	0
T284	44090	0	0	0
T306	0	3	0	0
T348	0	147	0	0
T352	0	30	0	0
T353	0	25	0	0
T354	0	48	0	0
T355	0	26	0	0
T356	0	7	0	0
T357	13141	0	0	0
T358	13812	0	0	0
T359	4690	0	0	0
T360	13383	0	0	0
T361	11948	0	0	0
T362	70342	0	0	0
T363	108661	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92880410	1563	0	0
T97	218622	8	0	0
T98	0	1	0	0
T173	0	20	0	0
T247	10417	0	0	0
T284	44090	0	0	0
T306	0	1	0	0
T348	0	111	0	0
T352	0	13	0	0
T353	0	23	0	0
T354	0	34	0	0
T355	0	21	0	0
T356	0	10	0	0
T357	13141	0	0	0
T358	13812	0	0	0
T359	4690	0	0	0
T360	13383	0	0	0
T361	11948	0	0	0
T362	70342	0	0	0
T363	108661	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92880410	855	0	0
T97	218622	34	0	0
T98	0	12	0	0
T173	0	16	0	0
T247	10417	0	0	0
T284	44090	0	0	0
T306	0	6	0	0
T330	0	174	0	0
T352	0	15	0	0
T353	0	23	0	0
T354	0	21	0	0
T355	0	33	0	0
T356	0	3	0	0
T357	13141	0	0	0
T358	13812	0	0	0
T359	4690	0	0	0
T360	13383	0	0	0
T361	11948	0	0	0
T362	70342	0	0	0
T363	108661	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92880410	189	0	0
T97	218622	15	0	0
T98	0	15	0	0
T173	0	10	0	0
T247	10417	0	0	0
T284	44090	0	0	0
T306	0	5	0	0
T352	0	36	0	0
T353	0	28	0	0
T354	0	21	0	0
T355	0	27	0	0
T356	0	5	0	0
T357	13141	0	0	0
T358	13812	0	0	0
T359	4690	0	0	0
T360	13383	0	0	0
T361	11948	0	0	0
T362	70342	0	0	0
T363	108661	0	0	0
T364	0	2	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92880410	20	0	0
T74	16760	0	0	0
T353	395428	6	0	0
T354	0	6	0	0
T355	0	5	0	0
T365	0	3	0	0
T366	36500	0	0	0
T367	26210	0	0	0
T368	9709	0	0	0
T369	13668	0	0	0
T370	12039	0	0	0
T371	10912	0	0	0
T372	10789	0	0	0
T373	11243	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92880410	30	0	0
T97	218622	7	0	0
T98	0	6	0	0
T173	0	5	0	0
T247	10417	0	0	0
T284	44090	0	0	0
T353	0	5	0	0
T355	0	3	0	0
T357	13141	0	0	0
T358	13812	0	0	0
T359	4690	0	0	0
T360	13383	0	0	0
T361	11948	0	0	0
T362	70342	0	0	0
T363	108661	0	0	0
T374	0	4	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92880410	1615	0	0
T97	218622	16	0	0
T98	0	16	0	0
T173	0	3	0	0
T247	10417	0	0	0
T284	44090	0	0	0
T323	0	7	0	0
T348	0	125	0	0
T352	0	9	0	0
T353	0	40	0	0
T354	0	25	0	0
T355	0	34	0	0
T356	0	14	0	0
T357	13141	0	0	0
T358	13812	0	0	0
T359	4690	0	0	0
T360	13383	0	0	0
T361	11948	0	0	0
T362	70342	0	0	0
T363	108661	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92880410	2227	0	0
T97	0	17	0	0
T98	0	19	0	0
T225	11748	0	0	0
T261	0	34	0	0
T276	0	41	0	0
T375	233839	11	0	0
T376	0	9	0	0
T377	0	29	0	0
T378	0	46	0	0
T379	0	33	0	0
T380	0	21	0	0
T381	37442	0	0	0
T382	12910	0	0	0
T383	7399	0	0	0
T384	19773	0	0	0
T385	71702	0	0	0
T386	78008	0	0	0
T387	25258	0	0	0
T388	83405	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92880410	923	0	0
T97	218622	45	0	0
T98	0	11	0	0
T173	0	11	0	0
T247	10417	0	0	0
T284	44090	0	0	0
T306	0	5	0	0
T330	0	211	0	0
T352	0	15	0	0
T353	0	38	0	0
T354	0	45	0	0
T355	0	23	0	0
T356	0	10	0	0
T357	13141	0	0	0
T358	13812	0	0	0
T359	4690	0	0	0
T360	13383	0	0	0
T361	11948	0	0	0
T362	70342	0	0	0
T363	108661	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92880410	843	0	0
T97	218622	37	0	0
T98	0	12	0	0
T173	0	2	0	0
T247	10417	0	0	0
T284	44090	0	0	0
T330	0	241	0	0
T352	0	16	0	0
T353	0	34	0	0
T354	0	26	0	0
T355	0	13	0	0
T356	0	5	0	0
T357	13141	0	0	0
T358	13812	0	0	0
T359	4690	0	0	0
T360	13383	0	0	0
T361	11948	0	0	0
T362	70342	0	0	0
T363	108661	0	0	0
T364	0	4	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92880410	825	0	0
T97	218622	24	0	0
T98	0	24	0	0
T173	0	9	0	0
T247	10417	0	0	0
T284	44090	0	0	0
T330	0	222	0	0
T352	0	6	0	0
T353	0	30	0	0
T354	0	21	0	0
T355	0	40	0	0
T356	0	9	0	0
T357	13141	0	0	0
T358	13812	0	0	0
T359	4690	0	0	0
T360	13383	0	0	0
T361	11948	0	0	0
T362	70342	0	0	0
T363	108661	0	0	0
T364	0	4	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92880410	823	0	0
T97	218622	13	0	0
T98	0	6	0	0
T173	0	15	0	0
T247	10417	0	0	0
T284	44090	0	0	0
T330	0	141	0	0
T352	0	19	0	0
T353	0	23	0	0
T354	0	14	0	0
T355	0	36	0	0
T356	0	12	0	0
T357	13141	0	0	0
T358	13812	0	0	0
T359	4690	0	0	0
T360	13383	0	0	0
T361	11948	0	0	0
T362	70342	0	0	0
T363	108661	0	0	0
T389	0	9	0	0