Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_secded_inv_72_64_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 69.12 69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 72.06 72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 72.06 72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 72.06 72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 73.53 73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 73.53 73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 73.53 73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 73.53 73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 75.00 75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 76.47 76.47
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 76.47 76.47
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.06 72.06


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.06 72.06


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.06 72.06


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.06 72.06


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.06 72.06


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.06 72.06


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.53 73.53


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.53 73.53


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.53 73.53


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.53 73.53


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.53 73.53


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.53 73.53


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.53 73.53


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.53 73.53


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T135,T92,T18 Yes T135,T92,T18 INPUT
data_o[63:0] Yes Yes T135,T92,T18 Yes T135,T92,T18 OUTPUT
syndrome_o[2:0] Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
syndrome_o[7:3] No No No OUTPUT
err_o[0] Yes Yes *T107,*T108,*T109 Yes T107,T108,T109 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 188 69.12
Total Bits 0->1 136 94 69.12
Total Bits 1->0 136 94 69.12

Ports 2 0 0.00
Port Bits 272 188 69.12
Port Bits 0->1 136 94 69.12
Port Bits 1->0 136 94 69.12

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[2:0] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[5:3] No No No INPUT
data_i[8:6] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[9] No No No INPUT
data_i[11:10] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[12] No No No INPUT
data_i[14:13] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[15] No No No INPUT
data_i[16] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 INPUT
data_i[17] No No No INPUT
data_i[23:18] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[25:24] No No No INPUT
data_i[27:26] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[28] No No No INPUT
data_i[29] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 INPUT
data_i[30] No No No INPUT
data_i[31] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 INPUT
data_i[32] No No No INPUT
data_i[37:33] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[38] No No No INPUT
data_i[41:39] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[43:42] No No No INPUT
data_i[44] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 INPUT
data_i[45] No No No INPUT
data_i[47:46] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[48] No No No INPUT
data_i[49] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 INPUT
data_i[50] No No No INPUT
data_i[52:51] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[54:53] No No No INPUT
data_i[62:55] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[63] No No No INPUT
data_i[71:64] Yes Yes T91,T17,T128 Yes T91,T136,T17 INPUT
data_o[2:0] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[5:3] No No No OUTPUT
data_o[8:6] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[9] No No No OUTPUT
data_o[11:10] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[12] No No No OUTPUT
data_o[14:13] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[15] No No No OUTPUT
data_o[16] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 OUTPUT
data_o[17] No No No OUTPUT
data_o[23:18] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[25:24] No No No OUTPUT
data_o[27:26] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[28] No No No OUTPUT
data_o[29] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 OUTPUT
data_o[30] No No No OUTPUT
data_o[31] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 OUTPUT
data_o[32] No No No OUTPUT
data_o[37:33] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[38] No No No OUTPUT
data_o[41:39] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[43:42] No No No OUTPUT
data_o[44] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 OUTPUT
data_o[45] No No No OUTPUT
data_o[47:46] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[48] No No No OUTPUT
data_o[49] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 OUTPUT
data_o[50] No No No OUTPUT
data_o[52:51] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[54:53] No No No OUTPUT
data_o[62:55] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 196 72.06
Total Bits 0->1 136 98 72.06
Total Bits 1->0 136 98 72.06

Ports 2 0 0.00
Port Bits 272 196 72.06
Port Bits 0->1 136 98 72.06
Port Bits 1->0 136 98 72.06

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] Yes Yes T3,T135,T136 Yes T3,T5,T10 INPUT
data_i[2] No No No INPUT
data_i[6:3] Yes Yes T3,T135,T136 Yes T3,T5,T10 INPUT
data_i[7] No No No INPUT
data_i[8] Yes Yes *T3,*T135,*T136 Yes T3,T5,T10 INPUT
data_i[10:9] No No No INPUT
data_i[15:11] Yes Yes T3,T135,T136 Yes T3,T5,T10 INPUT
data_i[16] No No No INPUT
data_i[17] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 INPUT
data_i[18] No No No INPUT
data_i[24:19] Yes Yes T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[27:25] No No No INPUT
data_i[29:28] Yes Yes T3,T135,T136 Yes T3,T5,T10 INPUT
data_i[30] No No No INPUT
data_i[31] Yes Yes *T3,*T135,*T136 Yes T3,T5,T10 INPUT
data_i[33:32] No No No INPUT
data_i[39:34] Yes Yes *T3,*T135,*T136 Yes T3,T5,T10 INPUT
data_i[41:40] No No No INPUT
data_i[43:42] Yes Yes T3,T135,T136 Yes T3,T5,T10 INPUT
data_i[44] No No No INPUT
data_i[46:45] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[48:47] No No No INPUT
data_i[53:49] Yes Yes T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[54] No No No INPUT
data_i[61:55] Yes Yes T3,T135,T136 Yes T3,T5,T10 INPUT
data_i[62] No No No INPUT
data_i[71:63] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_o[1:0] Yes Yes T3,T135,T136 Yes T3,T5,T10 OUTPUT
data_o[2] No No No OUTPUT
data_o[6:3] Yes Yes T3,T135,T136 Yes T3,T5,T10 OUTPUT
data_o[7] No No No OUTPUT
data_o[8] Yes Yes *T3,*T135,*T136 Yes T3,T5,T10 OUTPUT
data_o[10:9] No No No OUTPUT
data_o[15:11] Yes Yes T3,T135,T136 Yes T3,T5,T10 OUTPUT
data_o[16] No No No OUTPUT
data_o[17] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 OUTPUT
data_o[18] No No No OUTPUT
data_o[24:19] Yes Yes T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[27:25] No No No OUTPUT
data_o[29:28] Yes Yes T3,T135,T136 Yes T3,T5,T10 OUTPUT
data_o[30] No No No OUTPUT
data_o[31] Yes Yes *T3,*T135,*T136 Yes T3,T5,T10 OUTPUT
data_o[33:32] No No No OUTPUT
data_o[39:34] Yes Yes *T3,*T135,*T136 Yes T3,T5,T10 OUTPUT
data_o[41:40] No No No OUTPUT
data_o[43:42] Yes Yes T3,T135,T136 Yes T3,T5,T10 OUTPUT
data_o[44] No No No OUTPUT
data_o[46:45] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[48:47] No No No OUTPUT
data_o[53:49] Yes Yes T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[54] No No No OUTPUT
data_o[61:55] Yes Yes T3,T135,T136 Yes T3,T5,T10 OUTPUT
data_o[62] No No No OUTPUT
data_o[63] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 196 72.06
Total Bits 0->1 136 98 72.06
Total Bits 1->0 136 98 72.06

Ports 2 0 0.00
Port Bits 272 196 72.06
Port Bits 0->1 136 98 72.06
Port Bits 1->0 136 98 72.06

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[5:0] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[6] No No No INPUT
data_i[7] Yes Yes *T135,*T136,*T17 Yes T5,T10,T135 INPUT
data_i[10:8] No No No INPUT
data_i[17:11] Yes Yes T135,T136,T17 Yes T5,T10,T135 INPUT
data_i[19:18] No No No INPUT
data_i[21:20] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[22] No No No INPUT
data_i[25:23] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[26] No No No INPUT
data_i[29:27] Yes Yes T135,T136,T17 Yes T5,T10,T135 INPUT
data_i[30] No No No INPUT
data_i[32:31] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[36:33] No No No INPUT
data_i[37] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 INPUT
data_i[38] No No No INPUT
data_i[45:39] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 INPUT
data_i[46] No No No INPUT
data_i[49:47] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[50] No No No INPUT
data_i[52:51] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[53] No No No INPUT
data_i[59:54] Yes Yes T135,T92,T130 Yes T5,T10,T135 INPUT
data_i[61:60] No No No INPUT
data_i[71:62] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_o[5:0] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[6] No No No OUTPUT
data_o[7] Yes Yes *T135,*T136,*T17 Yes T5,T10,T135 OUTPUT
data_o[10:8] No No No OUTPUT
data_o[17:11] Yes Yes T135,T136,T17 Yes T5,T10,T135 OUTPUT
data_o[19:18] No No No OUTPUT
data_o[21:20] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[22] No No No OUTPUT
data_o[25:23] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[26] No No No OUTPUT
data_o[29:27] Yes Yes T135,T136,T17 Yes T5,T10,T135 OUTPUT
data_o[30] No No No OUTPUT
data_o[32:31] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[36:33] No No No OUTPUT
data_o[37] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 OUTPUT
data_o[38] No No No OUTPUT
data_o[45:39] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 OUTPUT
data_o[46] No No No OUTPUT
data_o[49:47] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[50] No No No OUTPUT
data_o[52:51] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[53] No No No OUTPUT
data_o[59:54] Yes Yes T135,T92,T130 Yes T5,T10,T135 OUTPUT
data_o[61:60] No No No OUTPUT
data_o[63:62] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 196 72.06
Total Bits 0->1 136 98 72.06
Total Bits 1->0 136 98 72.06

Ports 2 0 0.00
Port Bits 272 196 72.06
Port Bits 0->1 136 98 72.06
Port Bits 1->0 136 98 72.06

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] Yes Yes T135,T92,T124 Yes T5,T10,T135 INPUT
data_i[2] No No No INPUT
data_i[3] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 INPUT
data_i[4] No No No INPUT
data_i[8:5] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[9] No No No INPUT
data_i[11:10] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[12] No No No INPUT
data_i[15:13] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[16] No No No INPUT
data_i[17] Yes Yes *T135,*T92,*T124 Yes T10,T135,T92 INPUT
data_i[20:18] No No No INPUT
data_i[24:21] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[25] No No No INPUT
data_i[38:26] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[39] No No No INPUT
data_i[44:40] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[45] No No No INPUT
data_i[46] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 INPUT
data_i[48:47] No No No INPUT
data_i[53:49] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[54] No No No INPUT
data_i[55] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 INPUT
data_i[56] No No No INPUT
data_i[59:57] Yes Yes T135,T92,*T124 Yes T10,T135,T92 INPUT
data_i[63:60] No No No INPUT
data_i[71:64] Yes Yes T3,T91,T95 Yes T3,T5,T91 INPUT
data_o[1:0] Yes Yes T135,T92,T124 Yes T5,T10,T135 OUTPUT
data_o[2] No No No OUTPUT
data_o[3] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 OUTPUT
data_o[4] No No No OUTPUT
data_o[8:5] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[9] No No No OUTPUT
data_o[11:10] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[12] No No No OUTPUT
data_o[15:13] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[16] No No No OUTPUT
data_o[17] Yes Yes *T135,*T92,*T124 Yes T10,T135,T92 OUTPUT
data_o[20:18] No No No OUTPUT
data_o[24:21] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[25] No No No OUTPUT
data_o[38:26] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[39] No No No OUTPUT
data_o[44:40] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[45] No No No OUTPUT
data_o[46] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 OUTPUT
data_o[48:47] No No No OUTPUT
data_o[53:49] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[54] No No No OUTPUT
data_o[55] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 OUTPUT
data_o[56] No No No OUTPUT
data_o[59:57] Yes Yes T135,T92,*T124 Yes T10,T135,T92 OUTPUT
data_o[63:60] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 200 73.53
Total Bits 0->1 136 100 73.53
Total Bits 1->0 136 100 73.53

Ports 2 0 0.00
Port Bits 272 200 73.53
Port Bits 0->1 136 100 73.53
Port Bits 1->0 136 100 73.53

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[2] No No No INPUT
data_i[6:3] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[7] No No No INPUT
data_i[8] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[9] No No No INPUT
data_i[10] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[11] No No No INPUT
data_i[17:12] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[18] No No No INPUT
data_i[19] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[20] No No No INPUT
data_i[23:21] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[24] No No No INPUT
data_i[28:25] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[30:29] No No No INPUT
data_i[34:31] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[35] No No No INPUT
data_i[36] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[37] No No No INPUT
data_i[38] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[39] No No No INPUT
data_i[42:40] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[43] No No No INPUT
data_i[44] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[45] No No No INPUT
data_i[52:46] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[53] No No No INPUT
data_i[57:54] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[58] No No No INPUT
data_i[59] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[60] No No No INPUT
data_i[61] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[62] No No No INPUT
data_i[71:63] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_o[1:0] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[2] No No No OUTPUT
data_o[6:3] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[7] No No No OUTPUT
data_o[8] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[9] No No No OUTPUT
data_o[10] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[11] No No No OUTPUT
data_o[17:12] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[18] No No No OUTPUT
data_o[19] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[20] No No No OUTPUT
data_o[23:21] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[24] No No No OUTPUT
data_o[28:25] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[30:29] No No No OUTPUT
data_o[34:31] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[35] No No No OUTPUT
data_o[36] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[37] No No No OUTPUT
data_o[38] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[39] No No No OUTPUT
data_o[42:40] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[43] No No No OUTPUT
data_o[44] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[45] No No No OUTPUT
data_o[52:46] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[53] No No No OUTPUT
data_o[57:54] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[58] No No No OUTPUT
data_o[59] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[60] No No No OUTPUT
data_o[61] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[62] No No No OUTPUT
data_o[63] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 200 73.53
Total Bits 0->1 136 100 73.53
Total Bits 1->0 136 100 73.53

Ports 2 0 0.00
Port Bits 272 200 73.53
Port Bits 0->1 136 100 73.53
Port Bits 1->0 136 100 73.53

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[2] No No No INPUT
data_i[5:3] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[6] No No No INPUT
data_i[7] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[8] No No No INPUT
data_i[12:9] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[13] No No No INPUT
data_i[16:14] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[17] No No No INPUT
data_i[18] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 INPUT
data_i[20:19] No No No INPUT
data_i[22:21] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[23] No No No INPUT
data_i[24] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[25] No No No INPUT
data_i[32:26] Yes Yes T3,*T10,T91 Yes T3,T5,T10 INPUT
data_i[33] No No No INPUT
data_i[37:34] Yes Yes T3,*T10,T91 Yes T3,T5,T10 INPUT
data_i[38] No No No INPUT
data_i[42:39] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[43] No No No INPUT
data_i[45:44] Yes Yes T3,*T10,T91 Yes T3,T5,T10 INPUT
data_i[46] No No No INPUT
data_i[47] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 INPUT
data_i[48] No No No INPUT
data_i[50:49] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[51] No No No INPUT
data_i[59:52] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[62:60] No No No INPUT
data_i[71:63] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_o[1:0] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[2] No No No OUTPUT
data_o[5:3] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[6] No No No OUTPUT
data_o[7] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[8] No No No OUTPUT
data_o[12:9] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[13] No No No OUTPUT
data_o[16:14] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[17] No No No OUTPUT
data_o[18] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 OUTPUT
data_o[20:19] No No No OUTPUT
data_o[22:21] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[23] No No No OUTPUT
data_o[24] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[25] No No No OUTPUT
data_o[32:26] Yes Yes T3,*T10,T91 Yes T3,T5,T10 OUTPUT
data_o[33] No No No OUTPUT
data_o[37:34] Yes Yes T3,*T10,T91 Yes T3,T5,T10 OUTPUT
data_o[38] No No No OUTPUT
data_o[42:39] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[43] No No No OUTPUT
data_o[45:44] Yes Yes T3,*T10,T91 Yes T3,T5,T10 OUTPUT
data_o[46] No No No OUTPUT
data_o[47] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 OUTPUT
data_o[48] No No No OUTPUT
data_o[50:49] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[51] No No No OUTPUT
data_o[59:52] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[62:60] No No No OUTPUT
data_o[63] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 200 73.53
Total Bits 0->1 136 100 73.53
Total Bits 1->0 136 100 73.53

Ports 2 0 0.00
Port Bits 272 200 73.53
Port Bits 0->1 136 100 73.53
Port Bits 1->0 136 100 73.53

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[3:2] No No No INPUT
data_i[7:4] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[9:8] No No No INPUT
data_i[16:10] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[17] No No No INPUT
data_i[18] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[20:19] No No No INPUT
data_i[28:21] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[29] No No No INPUT
data_i[30] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[31] No No No INPUT
data_i[32] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[33] No No No INPUT
data_i[39:34] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[40] No No No INPUT
data_i[41] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[42] No No No INPUT
data_i[48:43] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[52:49] No No No INPUT
data_i[55:53] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[56] No No No INPUT
data_i[62:57] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[63] No No No INPUT
data_i[71:64] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_o[1:0] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[3:2] No No No OUTPUT
data_o[7:4] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[9:8] No No No OUTPUT
data_o[16:10] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[17] No No No OUTPUT
data_o[18] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[20:19] No No No OUTPUT
data_o[28:21] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[29] No No No OUTPUT
data_o[30] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[31] No No No OUTPUT
data_o[32] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[33] No No No OUTPUT
data_o[39:34] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[40] No No No OUTPUT
data_o[41] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[42] No No No OUTPUT
data_o[48:43] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[52:49] No No No OUTPUT
data_o[55:53] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[56] No No No OUTPUT
data_o[62:57] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 200 73.53
Total Bits 0->1 136 100 73.53
Total Bits 1->0 136 100 73.53

Ports 2 0 0.00
Port Bits 272 200 73.53
Port Bits 0->1 136 100 73.53
Port Bits 1->0 136 100 73.53

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[1] Yes Yes *T135,*T136,*T17 Yes T5,T10,T91 INPUT
data_i[2] No No No INPUT
data_i[5:3] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[7:6] No No No INPUT
data_i[10:8] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[12:11] No No No INPUT
data_i[22:13] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[23] No No No INPUT
data_i[24] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 INPUT
data_i[25] No No No INPUT
data_i[27:26] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[28] No No No INPUT
data_i[30:29] Yes Yes T135,T136,T17 Yes T5,T10,T135 INPUT
data_i[31] No No No INPUT
data_i[32] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 INPUT
data_i[33] No No No INPUT
data_i[36:34] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[38:37] No No No INPUT
data_i[40:39] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 INPUT
data_i[42:41] No No No INPUT
data_i[46:43] Yes Yes T135,T136,T17 Yes T5,T10,T135 INPUT
data_i[47] No No No INPUT
data_i[56:48] Yes Yes *T135,*T136,*T17 Yes T5,T10,T135 INPUT
data_i[57] No No No INPUT
data_i[58] Yes Yes *T135,*T136,*T17 Yes T5,T10,T135 INPUT
data_i[59] No No No INPUT
data_i[71:60] Yes Yes T135,T136,T17 Yes T5,T10,T135 INPUT
data_o[0] No No No OUTPUT
data_o[1] Yes Yes *T135,*T136,*T17 Yes T5,T10,T91 OUTPUT
data_o[2] No No No OUTPUT
data_o[5:3] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[7:6] No No No OUTPUT
data_o[10:8] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[12:11] No No No OUTPUT
data_o[22:13] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[23] No No No OUTPUT
data_o[24] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 OUTPUT
data_o[25] No No No OUTPUT
data_o[27:26] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[28] No No No OUTPUT
data_o[30:29] Yes Yes T135,T136,T17 Yes T5,T10,T135 OUTPUT
data_o[31] No No No OUTPUT
data_o[32] Yes Yes *T3,*T91,*T135 Yes T3,T5,T10 OUTPUT
data_o[33] No No No OUTPUT
data_o[36:34] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[38:37] No No No OUTPUT
data_o[40:39] Yes Yes *T3,*T91,T135 Yes T3,T5,T10 OUTPUT
data_o[42:41] No No No OUTPUT
data_o[46:43] Yes Yes T135,T136,T17 Yes T5,T10,T135 OUTPUT
data_o[47] No No No OUTPUT
data_o[56:48] Yes Yes *T135,*T136,*T17 Yes T5,T10,T135 OUTPUT
data_o[57] No No No OUTPUT
data_o[58] Yes Yes *T135,*T136,*T17 Yes T5,T10,T135 OUTPUT
data_o[59] No No No OUTPUT
data_o[63:60] Yes Yes T135,T136,T17 Yes T5,T10,T135 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 204 75.00
Total Bits 0->1 136 102 75.00
Total Bits 1->0 136 102 75.00

Ports 2 0 0.00
Port Bits 272 204 75.00
Port Bits 0->1 136 102 75.00
Port Bits 1->0 136 102 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[1] No No No INPUT
data_i[2] Yes Yes *T135,*T17,*T92 Yes T91,T135,T17 INPUT
data_i[4:3] No No No INPUT
data_i[5] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[6] No No No INPUT
data_i[17:7] Yes Yes *T135,*T17,*T92 Yes T91,T135,T17 INPUT
data_i[19:18] No No No INPUT
data_i[20] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[21] No No No INPUT
data_i[29:22] Yes Yes T135,T129,*T18 Yes T10,T91,T135 INPUT
data_i[33:30] No No No INPUT
data_i[36:34] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[37] No No No INPUT
data_i[41:38] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[42] No No No INPUT
data_i[43] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[44] No No No INPUT
data_i[47:45] Yes Yes T135,T17,T129 Yes T91,T135,T17 INPUT
data_i[48] No No No INPUT
data_i[54:49] Yes Yes *T83,*T135,*T17 Yes T83,T91,T135 INPUT
data_i[55] No No No INPUT
data_i[57:56] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[58] No No No INPUT
data_i[71:59] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_o[0] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[1] No No No OUTPUT
data_o[2] Yes Yes *T135,*T17,*T92 Yes T91,T135,T17 OUTPUT
data_o[4:3] No No No OUTPUT
data_o[5] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[6] No No No OUTPUT
data_o[17:7] Yes Yes *T135,*T17,*T92 Yes T91,T135,T17 OUTPUT
data_o[19:18] No No No OUTPUT
data_o[20] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[21] No No No OUTPUT
data_o[29:22] Yes Yes T135,T129,*T18 Yes T10,T91,T135 OUTPUT
data_o[33:30] No No No OUTPUT
data_o[36:34] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[37] No No No OUTPUT
data_o[41:38] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[42] No No No OUTPUT
data_o[43] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[44] No No No OUTPUT
data_o[47:45] Yes Yes T135,T17,T129 Yes T91,T135,T17 OUTPUT
data_o[48] No No No OUTPUT
data_o[54:49] Yes Yes *T83,*T135,*T17 Yes T83,T91,T135 OUTPUT
data_o[55] No No No OUTPUT
data_o[57:56] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[58] No No No OUTPUT
data_o[63:59] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 208 76.47
Total Bits 0->1 136 104 76.47
Total Bits 1->0 136 104 76.47

Ports 2 0 0.00
Port Bits 272 208 76.47
Port Bits 0->1 136 104 76.47
Port Bits 1->0 136 104 76.47

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[7:0] Yes Yes T3,T91,T135 Yes T3,T5,T10 INPUT
data_i[9:8] No No No INPUT
data_i[13:10] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[15:14] No No No INPUT
data_i[18:16] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[19] No No No INPUT
data_i[20] Yes Yes *T91,*T135,*T95 Yes T5,T10,T91 INPUT
data_i[21] No No No INPUT
data_i[23:22] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[24] No No No INPUT
data_i[26:25] Yes Yes T91,T135,T95 Yes T5,T10,T91 INPUT
data_i[27] No No No INPUT
data_i[35:28] Yes Yes T91,T135,T95 Yes T5,T10,T91 INPUT
data_i[37:36] No No No INPUT
data_i[42:38] Yes Yes *T3,*T10,T91 Yes T3,T5,T10 INPUT
data_i[43] No No No INPUT
data_i[46:44] Yes Yes T91,T135,T95 Yes T5,T10,T91 INPUT
data_i[47] No No No INPUT
data_i[53:48] Yes Yes *T3,*T10,T91 Yes T3,T5,T10 INPUT
data_i[54] No No No INPUT
data_i[57:55] Yes Yes T91,T135,T136 Yes T5,T10,T91 INPUT
data_i[59:58] No No No INPUT
data_i[62:60] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[63] No No No INPUT
data_i[71:64] Yes Yes T95,T128,T19 Yes T95,T128,T19 INPUT
data_o[7:0] Yes Yes T3,T91,T135 Yes T3,T5,T10 OUTPUT
data_o[9:8] No No No OUTPUT
data_o[13:10] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[15:14] No No No OUTPUT
data_o[18:16] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[19] No No No OUTPUT
data_o[20] Yes Yes *T91,*T135,*T95 Yes T5,T10,T91 OUTPUT
data_o[21] No No No OUTPUT
data_o[23:22] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[24] No No No OUTPUT
data_o[26:25] Yes Yes T91,T135,T95 Yes T5,T10,T91 OUTPUT
data_o[27] No No No OUTPUT
data_o[35:28] Yes Yes T91,T135,T95 Yes T5,T10,T91 OUTPUT
data_o[37:36] No No No OUTPUT
data_o[42:38] Yes Yes *T3,*T10,T91 Yes T3,T5,T10 OUTPUT
data_o[43] No No No OUTPUT
data_o[46:44] Yes Yes T91,T135,T95 Yes T5,T10,T91 OUTPUT
data_o[47] No No No OUTPUT
data_o[53:48] Yes Yes *T3,*T10,T91 Yes T3,T5,T10 OUTPUT
data_o[54] No No No OUTPUT
data_o[57:55] Yes Yes T91,T135,T136 Yes T5,T10,T91 OUTPUT
data_o[59:58] No No No OUTPUT
data_o[62:60] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 208 76.47
Total Bits 0->1 136 104 76.47
Total Bits 1->0 136 104 76.47

Ports 2 0 0.00
Port Bits 272 208 76.47
Port Bits 0->1 136 104 76.47
Port Bits 1->0 136 104 76.47

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[2:0] Yes Yes T91,T135,T136 Yes T5,T10,T91 INPUT
data_i[3] No No No INPUT
data_i[10:4] Yes Yes *T3,*T10,T91 Yes T3,T5,T10 INPUT
data_i[11] No No No INPUT
data_i[17:12] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[18] No No No INPUT
data_i[20:19] Yes Yes T91,T135,T136 Yes T5,T10,T91 INPUT
data_i[21] No No No INPUT
data_i[23:22] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[25:24] No No No INPUT
data_i[36:26] Yes Yes *T3,*T10,T91 Yes T3,T5,T10 INPUT
data_i[37] No No No INPUT
data_i[38] Yes Yes *T91,*T135,*T136 Yes T5,T10,T91 INPUT
data_i[39] No No No INPUT
data_i[40] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 INPUT
data_i[43:41] No No No INPUT
data_i[46:44] Yes Yes T3,T10,T91 Yes T3,T5,T10 INPUT
data_i[47] No No No INPUT
data_i[51:48] Yes Yes *T3,*T10,T91 Yes T3,T5,T10 INPUT
data_i[52] No No No INPUT
data_i[53] Yes Yes *T91,*T135,*T17 Yes T91,T135,T17 INPUT
data_i[54] No No No INPUT
data_i[61:55] Yes Yes *T3,*T10,T91 Yes T3,T5,T10 INPUT
data_i[63:62] No No No INPUT
data_i[71:64] Yes Yes T3,T10,T91 Yes T3,T10,T91 INPUT
data_o[2:0] Yes Yes T91,T135,T136 Yes T5,T10,T91 OUTPUT
data_o[3] No No No OUTPUT
data_o[10:4] Yes Yes *T3,*T10,T91 Yes T3,T5,T10 OUTPUT
data_o[11] No No No OUTPUT
data_o[17:12] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[18] No No No OUTPUT
data_o[20:19] Yes Yes T91,T135,T136 Yes T5,T10,T91 OUTPUT
data_o[21] No No No OUTPUT
data_o[23:22] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[25:24] No No No OUTPUT
data_o[36:26] Yes Yes *T3,*T10,T91 Yes T3,T5,T10 OUTPUT
data_o[37] No No No OUTPUT
data_o[38] Yes Yes *T91,*T135,*T136 Yes T5,T10,T91 OUTPUT
data_o[39] No No No OUTPUT
data_o[40] Yes Yes *T3,*T10,*T91 Yes T3,T5,T10 OUTPUT
data_o[43:41] No No No OUTPUT
data_o[46:44] Yes Yes T3,T10,T91 Yes T3,T5,T10 OUTPUT
data_o[47] No No No OUTPUT
data_o[51:48] Yes Yes *T3,*T10,T91 Yes T3,T5,T10 OUTPUT
data_o[52] No No No OUTPUT
data_o[53] Yes Yes *T91,*T135,*T17 Yes T91,T135,T17 OUTPUT
data_o[54] No No No OUTPUT
data_o[61:55] Yes Yes *T3,*T10,T91 Yes T3,T5,T10 OUTPUT
data_o[63:62] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T105,T154,T132 Yes T105,T154,T132 INPUT
data_o[63:0] Yes Yes T105,T154,T132 Yes T105,T154,T132 OUTPUT
syndrome_o[2:0] Yes Yes T108,T109,T185 Yes T108,T109,T185 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T108,*T109,*T185 Yes T108,T109,T185 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T135,T125,T132 Yes T135,T125,T132 INPUT
data_o[63:0] Yes Yes T135,T125,T132 Yes T135,T125,T132 OUTPUT
syndrome_o[2:0] Yes Yes T108,T109 Yes T108,T109 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T108,*T109 Yes T108,T109 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T92,T18,T105 Yes T92,T18,T105 INPUT
data_o[63:0] Yes Yes T92,T18,T105 Yes T92,T18,T105 OUTPUT
syndrome_o[2:0] Yes Yes T108,T109,T196 Yes T108,T109,T196 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T108,*T109,*T196 Yes T108,T109,T196 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T135,T17,T92 Yes T135,T17,T92 INPUT
data_o[63:0] Yes Yes T135,T17,T92 Yes T135,T17,T92 OUTPUT
syndrome_o[2:0] Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T107,*T108,*T109 Yes T107,T108,T109 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T17,T128,T146 Yes T17,T128,T146 INPUT
data_o[63:0] Yes Yes T17,T128,T146 Yes T17,T128,T146 OUTPUT
syndrome_o[7:0] Excluded Excluded T185 Excluded T185 OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded T185 Excluded T185 OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T285,T237,T291 Yes T285,T237,T291 INPUT
data_o[63:0] Yes Yes T285,T237,T291 Yes T285,T237,T291 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T91,T42,T61 Yes T91,T169,T42 INPUT
data_o[63:0] Yes Yes T91,T42,T61 Yes T91,T169,T42 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T18,T126,T146 Yes T18,T126,T146 INPUT
data_o[63:0] Yes Yes T18,T126,T146 Yes T18,T126,T146 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T133,T291,T292 Yes T133,T291,T293 INPUT
data_o[63:0] Yes Yes T133,T291,T292 Yes T133,T291,T293 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T238,T268,T294 Yes T238,T268,T294 INPUT
data_o[63:0] Yes Yes T238,T268,T294 Yes T238,T268,T294 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T136,T152 Yes T3,T136,T152 INPUT
data_o[63:0] Yes Yes T3,T136,T152 Yes T3,T136,T152 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T180,T205,T235 Yes T129,T180,T205 INPUT
data_o[63:0] Yes Yes T180,T205,T235 Yes T129,T180,T205 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T31,T41,T127 Yes T31,T41,T127 INPUT
data_o[63:0] Yes Yes T31,T41,T127 Yes T31,T41,T127 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T10 Yes T2,T3,T5 INPUT
data_o[63:0] Yes Yes T2,T3,T10 Yes T2,T3,T5 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T136,T126,T146 Yes T5,T136,T126 INPUT
data_o[63:0] Yes Yes T136,T126,T146 Yes T5,T136,T126 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T91,T135,T136 Yes T91,T135,T136 INPUT
data_o[63:0] Yes Yes T91,T135,T136 Yes T91,T135,T136 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T91,T136 Yes T2,T91,T136 INPUT
data_o[63:0] Yes Yes T2,T91,T136 Yes T2,T91,T136 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T91 Yes T2,T3,T91 INPUT
data_o[63:0] Yes Yes T2,T3,T91 Yes T2,T3,T91 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T31,T129 Yes T2,T31,T129 INPUT
data_o[63:0] Yes Yes T2,T31,T129 Yes T2,T31,T129 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T31,T91 Yes T2,T31,T91 INPUT
data_o[63:0] Yes Yes T2,T31,T91 Yes T2,T31,T91 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T124 Yes T2,T3,T124 INPUT
data_o[63:0] Yes Yes T2,T3,T124 Yes T2,T3,T124 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T91,T136,T92 Yes T5,T91,T95 INPUT
data_o[63:0] Yes Yes T91,T136,T92 Yes T5,T91,T95 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T31,T135,T41 Yes T31,T135,T136 INPUT
data_o[63:0] Yes Yes T31,T135,T41 Yes T31,T135,T136 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T4,T18 Yes T3,T4,T24 INPUT
data_o[63:0] Yes Yes T3,T4,T18 Yes T3,T4,T24 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T136,T130,T137 Yes T5,T136,T130 INPUT
data_o[63:0] Yes Yes T136,T130,T137 Yes T5,T136,T130 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T31,T136,T146 Yes T31,T136,T146 INPUT
data_o[63:0] Yes Yes T31,T136,T146 Yes T31,T136,T146 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T136,T124,T125 Yes T136,T124,T125 INPUT
data_o[63:0] Yes Yes T136,T124,T125 Yes T136,T124,T125 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T18,T235,T295 Yes T18,T235,T295 INPUT
data_o[63:0] Yes Yes T18,T235,T295 Yes T18,T235,T295 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T95,T182 Yes T3,T95,T136 INPUT
data_o[63:0] Yes Yes T3,T95,T182 Yes T3,T95,T136 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T95,T136 Yes T3,T95,T136 INPUT
data_o[63:0] Yes Yes T3,T95,T136 Yes T3,T95,T136 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T136,T127,T148 Yes T136,T127,T169 INPUT
data_o[63:0] Yes Yes T136,T127,T148 Yes T136,T127,T169 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T132,T152,T211 Yes T6,T24,T132 INPUT
data_o[63:0] Yes Yes T132,T152,T211 Yes T6,T24,T132 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T95,T92 Yes T3,T95,T92 INPUT
data_o[63:0] Yes Yes T3,T95,T92 Yes T3,T95,T92 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%