| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 94.93 | 93.69 | 96.60 | 95.68 | 91.57 | 97.47 | 96.34 | 93.14 |
| T341 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.1296331448 | Sep 04 08:38:30 AM UTC 24 | Sep 04 08:38:33 AM UTC 24 | 77584181 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.300910376 | Sep 04 08:38:09 AM UTC 24 | Sep 04 08:38:34 AM UTC 24 | 2602498770 ps | ||
| T1260 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3432639560 | Sep 04 08:38:28 AM UTC 24 | Sep 04 08:38:34 AM UTC 24 | 268655272 ps | ||
| T1261 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1562514957 | Sep 04 08:38:31 AM UTC 24 | Sep 04 08:38:35 AM UTC 24 | 129124426 ps | ||
| T1262 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1547190927 | Sep 04 08:38:31 AM UTC 24 | Sep 04 08:38:36 AM UTC 24 | 244349294 ps | ||
| T1263 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.2798101645 | Sep 04 08:38:33 AM UTC 24 | Sep 04 08:38:36 AM UTC 24 | 157234092 ps | ||
| T415 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1680427961 | Sep 04 08:38:14 AM UTC 24 | Sep 04 08:38:36 AM UTC 24 | 1306416908 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.2792373682 | Sep 04 08:38:33 AM UTC 24 | Sep 04 08:38:36 AM UTC 24 | 131182434 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1863202484 | Sep 04 08:38:33 AM UTC 24 | Sep 04 08:38:36 AM UTC 24 | 267783667 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.1323547369 | Sep 04 08:38:33 AM UTC 24 | Sep 04 08:38:37 AM UTC 24 | 551572511 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.967223745 | Sep 04 08:38:38 AM UTC 24 | Sep 04 08:38:41 AM UTC 24 | 142421079 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2153608223 | Sep 04 08:38:30 AM UTC 24 | Sep 04 08:38:37 AM UTC 24 | 145659131 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.798270406 | Sep 04 08:38:33 AM UTC 24 | Sep 04 08:38:37 AM UTC 24 | 152444980 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.830187251 | Sep 04 08:38:34 AM UTC 24 | Sep 04 08:38:37 AM UTC 24 | 52851271 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.2663904940 | Sep 04 08:38:34 AM UTC 24 | Sep 04 08:38:38 AM UTC 24 | 136032958 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1191773871 | Sep 04 08:38:24 AM UTC 24 | Sep 04 08:38:38 AM UTC 24 | 1271957291 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.1363629511 | Sep 04 08:38:34 AM UTC 24 | Sep 04 08:38:38 AM UTC 24 | 37801527 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.140072509 | Sep 04 08:38:35 AM UTC 24 | Sep 04 08:38:38 AM UTC 24 | 66416079 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.370589554 | Sep 04 08:38:34 AM UTC 24 | Sep 04 08:38:38 AM UTC 24 | 46814419 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1519813146 | Sep 04 08:38:33 AM UTC 24 | Sep 04 08:38:38 AM UTC 24 | 395775579 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.3222512009 | Sep 04 08:38:35 AM UTC 24 | Sep 04 08:38:38 AM UTC 24 | 582019854 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.2754537204 | Sep 04 08:38:36 AM UTC 24 | Sep 04 08:38:39 AM UTC 24 | 140563076 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.749161588 | Sep 04 08:38:36 AM UTC 24 | Sep 04 08:38:39 AM UTC 24 | 152343021 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.301237693 | Sep 04 08:38:38 AM UTC 24 | Sep 04 08:38:41 AM UTC 24 | 80366605 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.4141306922 | Sep 04 08:38:26 AM UTC 24 | Sep 04 08:38:39 AM UTC 24 | 781692788 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.3282786971 | Sep 04 08:38:37 AM UTC 24 | Sep 04 08:38:39 AM UTC 24 | 44544898 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.217928809 | Sep 04 08:38:37 AM UTC 24 | Sep 04 08:38:39 AM UTC 24 | 51501402 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.2071255609 | Sep 04 08:38:37 AM UTC 24 | Sep 04 08:38:40 AM UTC 24 | 39097556 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.1239720499 | Sep 04 08:38:37 AM UTC 24 | Sep 04 08:38:40 AM UTC 24 | 535372772 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.2303763113 | Sep 04 08:38:38 AM UTC 24 | Sep 04 08:38:41 AM UTC 24 | 138496584 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.1004364984 | Sep 04 08:38:38 AM UTC 24 | Sep 04 08:38:41 AM UTC 24 | 38914035 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.4219801884 | Sep 04 08:38:38 AM UTC 24 | Sep 04 08:38:41 AM UTC 24 | 149366259 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.38884894 | Sep 04 08:38:19 AM UTC 24 | Sep 04 08:38:41 AM UTC 24 | 4800568739 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.1216565200 | Sep 04 08:38:38 AM UTC 24 | Sep 04 08:38:41 AM UTC 24 | 40394193 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.3476513305 | Sep 04 08:38:38 AM UTC 24 | Sep 04 08:38:42 AM UTC 24 | 530219414 ps | ||
| T1289 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.1618552109 | Sep 04 08:38:40 AM UTC 24 | Sep 04 08:38:42 AM UTC 24 | 74626908 ps | ||
| T1290 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.2218380239 | Sep 04 08:38:39 AM UTC 24 | Sep 04 08:38:42 AM UTC 24 | 136149716 ps | ||
| T1291 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.909838573 | Sep 04 08:38:39 AM UTC 24 | Sep 04 08:38:42 AM UTC 24 | 77278631 ps | ||
| T1292 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.1455086456 | Sep 04 08:38:40 AM UTC 24 | Sep 04 08:38:42 AM UTC 24 | 58964294 ps | ||
| T1293 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2439759512 | Sep 04 08:38:16 AM UTC 24 | Sep 04 08:38:43 AM UTC 24 | 5083876127 ps | ||
| T1294 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.81781624 | Sep 04 08:38:40 AM UTC 24 | Sep 04 08:38:43 AM UTC 24 | 602754298 ps | ||
| T1295 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.889182089 | Sep 04 08:38:39 AM UTC 24 | Sep 04 08:38:43 AM UTC 24 | 554885415 ps | ||
| T1296 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.4138582270 | Sep 04 08:38:39 AM UTC 24 | Sep 04 08:38:43 AM UTC 24 | 575133954 ps | ||
| T1297 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.1241449785 | Sep 04 08:38:41 AM UTC 24 | Sep 04 08:38:43 AM UTC 24 | 130497605 ps | ||
| T1298 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1282128230 | Sep 04 08:38:32 AM UTC 24 | Sep 04 08:38:45 AM UTC 24 | 683573365 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2645580568 | Sep 04 08:38:21 AM UTC 24 | Sep 04 08:38:47 AM UTC 24 | 2141952240 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1198091108 | Sep 04 08:38:01 AM UTC 24 | Sep 04 08:38:49 AM UTC 24 | 20003803126 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3933233952 | Sep 04 08:38:30 AM UTC 24 | Sep 04 08:38:51 AM UTC 24 | 19967525940 ps | ||
| T1299 | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3446005185 | Sep 04 08:38:27 AM UTC 24 | Sep 04 08:38:51 AM UTC 24 | 2344920142 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.1784719370 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 297200955 ps |
| CPU time | 9.38 seconds |
| Started | Sep 04 08:38:57 AM UTC 24 |
| Finished | Sep 04 08:39:08 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784719370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.1784719370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.2083189361 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2502427583 ps |
| CPU time | 14.28 seconds |
| Started | Sep 04 08:39:07 AM UTC 24 |
| Finished | Sep 04 08:39:22 AM UTC 24 |
| Peak memory | 253748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083189361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.2083189361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.1678700203 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1722986065 ps |
| CPU time | 15.38 seconds |
| Started | Sep 04 08:39:04 AM UTC 24 |
| Finished | Sep 04 08:39:21 AM UTC 24 |
| Peak memory | 253616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678700203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.1678700203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.847989051 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2659835174 ps |
| CPU time | 49.1 seconds |
| Started | Sep 04 08:39:21 AM UTC 24 |
| Finished | Sep 04 08:40:11 AM UTC 24 |
| Peak memory | 257648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=847989051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.847989051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.4226690504 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1590166937 ps |
| CPU time | 33.15 seconds |
| Started | Sep 04 08:39:09 AM UTC 24 |
| Finished | Sep 04 08:39:44 AM UTC 24 |
| Peak memory | 253336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226690504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.4226690504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.3347629326 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 4360801495 ps |
| CPU time | 97.06 seconds |
| Started | Sep 04 08:39:55 AM UTC 24 |
| Finished | Sep 04 08:41:34 AM UTC 24 |
| Peak memory | 270192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347629326 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.3347629326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.1859685157 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1378114993 ps |
| CPU time | 22.25 seconds |
| Started | Sep 04 08:39:09 AM UTC 24 |
| Finished | Sep 04 08:39:33 AM UTC 24 |
| Peak memory | 255388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859685157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.1859685157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.2329946092 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 47068023730 ps |
| CPU time | 161.64 seconds |
| Started | Sep 04 08:39:07 AM UTC 24 |
| Finished | Sep 04 08:41:51 AM UTC 24 |
| Peak memory | 269820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329946092 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.2329946092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.1467436495 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 185760045 ps |
| CPU time | 3.72 seconds |
| Started | Sep 04 08:46:15 AM UTC 24 |
| Finished | Sep 04 08:46:20 AM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467436495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.1467436495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.2100654518 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 724084626 ps |
| CPU time | 15.15 seconds |
| Started | Sep 04 08:39:03 AM UTC 24 |
| Finished | Sep 04 08:39:20 AM UTC 24 |
| Peak memory | 257476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100654518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.2100654518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.249809676 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 11415849538 ps |
| CPU time | 181.58 seconds |
| Started | Sep 04 08:39:28 AM UTC 24 |
| Finished | Sep 04 08:42:33 AM UTC 24 |
| Peak memory | 287884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249809676 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.249809676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.3070503764 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 114239016 ps |
| CPU time | 4.7 seconds |
| Started | Sep 04 08:39:46 AM UTC 24 |
| Finished | Sep 04 08:39:52 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070503764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.3070503764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.1311592653 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 32081418480 ps |
| CPU time | 65.82 seconds |
| Started | Sep 04 08:39:09 AM UTC 24 |
| Finished | Sep 04 08:40:17 AM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311592653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1311592653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.865801375 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 586085834 ps |
| CPU time | 9.24 seconds |
| Started | Sep 04 08:40:31 AM UTC 24 |
| Finished | Sep 04 08:40:42 AM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865801375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.865801375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.986360090 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 18374202972 ps |
| CPU time | 245.3 seconds |
| Started | Sep 04 08:39:28 AM UTC 24 |
| Finished | Sep 04 08:43:37 AM UTC 24 |
| Peak memory | 274036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986360090 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.986360090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.708895143 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 12699022941 ps |
| CPU time | 25 seconds |
| Started | Sep 04 08:39:01 AM UTC 24 |
| Finished | Sep 04 08:39:28 AM UTC 24 |
| Peak memory | 257840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708895143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.708895143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1162259049 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2445573971 ps |
| CPU time | 18.18 seconds |
| Started | Sep 04 08:37:56 AM UTC 24 |
| Finished | Sep 04 08:38:15 AM UTC 24 |
| Peak memory | 256860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162259049 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.1162259049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.4125664220 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 3473631488 ps |
| CPU time | 35.32 seconds |
| Started | Sep 04 08:40:14 AM UTC 24 |
| Finished | Sep 04 08:40:51 AM UTC 24 |
| Peak memory | 257184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125664220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.4125664220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.3086152950 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 30108026117 ps |
| CPU time | 99 seconds |
| Started | Sep 04 08:39:40 AM UTC 24 |
| Finished | Sep 04 08:41:21 AM UTC 24 |
| Peak memory | 269868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086152950 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.3086152950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.3852623513 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 172222829 ps |
| CPU time | 3.87 seconds |
| Started | Sep 04 08:39:10 AM UTC 24 |
| Finished | Sep 04 08:39:15 AM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852623513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.3852623513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.3356912793 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 4071636344 ps |
| CPU time | 54.79 seconds |
| Started | Sep 04 08:43:32 AM UTC 24 |
| Finished | Sep 04 08:44:28 AM UTC 24 |
| Peak memory | 267988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3356912793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 29.otp_ctrl_stress_all_with_rand_reset.3356912793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.1476015745 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1625263185 ps |
| CPU time | 30.46 seconds |
| Started | Sep 04 08:39:38 AM UTC 24 |
| Finished | Sep 04 08:40:10 AM UTC 24 |
| Peak memory | 253344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476015745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.1476015745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.147128396 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1965925607 ps |
| CPU time | 3.95 seconds |
| Started | Sep 04 08:48:51 AM UTC 24 |
| Finished | Sep 04 08:48:56 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147128396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.147128396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.3949979522 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 15104214449 ps |
| CPU time | 87.27 seconds |
| Started | Sep 04 08:40:27 AM UTC 24 |
| Finished | Sep 04 08:41:57 AM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949979522 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.3949979522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.2152147326 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 19803455058 ps |
| CPU time | 179.38 seconds |
| Started | Sep 04 08:44:41 AM UTC 24 |
| Finished | Sep 04 08:47:44 AM UTC 24 |
| Peak memory | 286296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2152147326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.otp_ctrl_stress_all_with_rand_reset.2152147326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.2548273605 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 3794534236 ps |
| CPU time | 8.85 seconds |
| Started | Sep 04 08:40:20 AM UTC 24 |
| Finished | Sep 04 08:40:30 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548273605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.2548273605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.3331862959 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 583043495 ps |
| CPU time | 3.25 seconds |
| Started | Sep 04 08:37:35 AM UTC 24 |
| Finished | Sep 04 08:37:39 AM UTC 24 |
| Peak memory | 258856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331862959 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.3331862959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.3049338761 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 283835638 ps |
| CPU time | 4.14 seconds |
| Started | Sep 04 08:39:00 AM UTC 24 |
| Finished | Sep 04 08:39:05 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049338761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.3049338761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.3057533689 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 55877824 ps |
| CPU time | 2.05 seconds |
| Started | Sep 04 08:39:08 AM UTC 24 |
| Finished | Sep 04 08:39:11 AM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057533689 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.3057533689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.3096873692 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 9263143401 ps |
| CPU time | 20.72 seconds |
| Started | Sep 04 08:39:06 AM UTC 24 |
| Finished | Sep 04 08:39:27 AM UTC 24 |
| Peak memory | 253688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096873692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.3096873692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.1419613407 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 10431115610 ps |
| CPU time | 66.89 seconds |
| Started | Sep 04 08:41:12 AM UTC 24 |
| Finished | Sep 04 08:42:21 AM UTC 24 |
| Peak memory | 257880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419613407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.1419613407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.3556306984 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 359361673 ps |
| CPU time | 5.3 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:25 AM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556306984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.3556306984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.441154997 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4642093307 ps |
| CPU time | 38.7 seconds |
| Started | Sep 04 08:41:51 AM UTC 24 |
| Finished | Sep 04 08:42:32 AM UTC 24 |
| Peak memory | 267956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=441154997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.441154997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.2700499081 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2370474079 ps |
| CPU time | 6.79 seconds |
| Started | Sep 04 08:40:50 AM UTC 24 |
| Finished | Sep 04 08:40:58 AM UTC 24 |
| Peak memory | 251268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700499081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.2700499081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.2245275542 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 276931119 ps |
| CPU time | 5.99 seconds |
| Started | Sep 04 08:45:39 AM UTC 24 |
| Finished | Sep 04 08:45:46 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245275542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.2245275542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.4186103825 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2799333673 ps |
| CPU time | 7.63 seconds |
| Started | Sep 04 08:39:23 AM UTC 24 |
| Finished | Sep 04 08:39:31 AM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186103825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.4186103825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.1610516637 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 24507960464 ps |
| CPU time | 240.81 seconds |
| Started | Sep 04 08:39:21 AM UTC 24 |
| Finished | Sep 04 08:43:25 AM UTC 24 |
| Peak memory | 269780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610516637 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.1610516637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.1941207346 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 210756011 ps |
| CPU time | 4.28 seconds |
| Started | Sep 04 08:41:19 AM UTC 24 |
| Finished | Sep 04 08:41:25 AM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941207346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.1941207346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.1234243621 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1783904463 ps |
| CPU time | 26.17 seconds |
| Started | Sep 04 08:40:52 AM UTC 24 |
| Finished | Sep 04 08:41:21 AM UTC 24 |
| Peak memory | 255772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234243621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.1234243621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.2138250870 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 13185255102 ps |
| CPU time | 186.39 seconds |
| Started | Sep 04 08:44:53 AM UTC 24 |
| Finished | Sep 04 08:48:02 AM UTC 24 |
| Peak memory | 259436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138250870 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.2138250870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.473929829 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 573916749 ps |
| CPU time | 25.29 seconds |
| Started | Sep 04 08:39:08 AM UTC 24 |
| Finished | Sep 04 08:39:35 AM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473929829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.473929829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.3947495362 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 515953324 ps |
| CPU time | 17.89 seconds |
| Started | Sep 04 08:39:15 AM UTC 24 |
| Finished | Sep 04 08:39:34 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947495362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.3947495362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.1901756971 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 35527499824 ps |
| CPU time | 133.38 seconds |
| Started | Sep 04 08:43:47 AM UTC 24 |
| Finished | Sep 04 08:46:03 AM UTC 24 |
| Peak memory | 274092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1901756971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.otp_ctrl_stress_all_with_rand_reset.1901756971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.3621012435 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 134071192 ps |
| CPU time | 4.68 seconds |
| Started | Sep 04 08:40:58 AM UTC 24 |
| Finished | Sep 04 08:41:04 AM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621012435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.3621012435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.644762627 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1131516277 ps |
| CPU time | 10.44 seconds |
| Started | Sep 04 08:39:38 AM UTC 24 |
| Finished | Sep 04 08:39:49 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644762627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.644762627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.3971907646 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 123776977 ps |
| CPU time | 6.4 seconds |
| Started | Sep 04 08:47:54 AM UTC 24 |
| Finished | Sep 04 08:48:02 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971907646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.3971907646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.1721073613 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 22845853891 ps |
| CPU time | 73.53 seconds |
| Started | Sep 04 08:39:39 AM UTC 24 |
| Finished | Sep 04 08:40:54 AM UTC 24 |
| Peak memory | 267944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1721073613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.otp_ctrl_stress_all_with_rand_reset.1721073613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.3073741419 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 55501172151 ps |
| CPU time | 143 seconds |
| Started | Sep 04 08:44:57 AM UTC 24 |
| Finished | Sep 04 08:47:22 AM UTC 24 |
| Peak memory | 271900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073741419 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.3073741419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.2674770728 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1051708328 ps |
| CPU time | 9.38 seconds |
| Started | Sep 04 08:39:34 AM UTC 24 |
| Finished | Sep 04 08:39:45 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674770728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.2674770728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.220388475 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 6475478765 ps |
| CPU time | 34.42 seconds |
| Started | Sep 04 08:41:59 AM UTC 24 |
| Finished | Sep 04 08:42:35 AM UTC 24 |
| Peak memory | 257632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220388475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.220388475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.3667253389 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 17892902649 ps |
| CPU time | 260.42 seconds |
| Started | Sep 04 08:40:08 AM UTC 24 |
| Finished | Sep 04 08:44:32 AM UTC 24 |
| Peak memory | 284268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667253389 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.3667253389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.2789817825 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 111804875 ps |
| CPU time | 3.66 seconds |
| Started | Sep 04 08:49:08 AM UTC 24 |
| Finished | Sep 04 08:49:13 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789817825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.2789817825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.3514332912 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1805354448 ps |
| CPU time | 27.45 seconds |
| Started | Sep 04 08:41:24 AM UTC 24 |
| Finished | Sep 04 08:41:53 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514332912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.3514332912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.1748287246 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 301592324 ps |
| CPU time | 5.65 seconds |
| Started | Sep 04 08:43:15 AM UTC 24 |
| Finished | Sep 04 08:43:22 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748287246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.1748287246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.2078014844 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1926288904 ps |
| CPU time | 30.48 seconds |
| Started | Sep 04 08:43:53 AM UTC 24 |
| Finished | Sep 04 08:44:25 AM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078014844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.2078014844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.2403067416 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 239441797 ps |
| CPU time | 5.24 seconds |
| Started | Sep 04 08:48:12 AM UTC 24 |
| Finished | Sep 04 08:48:18 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403067416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.2403067416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.1170083881 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 312091183 ps |
| CPU time | 8.2 seconds |
| Started | Sep 04 08:46:31 AM UTC 24 |
| Finished | Sep 04 08:46:41 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170083881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.1170083881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.2879502055 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 16109955972 ps |
| CPU time | 39.44 seconds |
| Started | Sep 04 08:46:08 AM UTC 24 |
| Finished | Sep 04 08:46:49 AM UTC 24 |
| Peak memory | 257560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2879502055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 52.otp_ctrl_stress_all_with_rand_reset.2879502055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.740431857 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 1546772493 ps |
| CPU time | 27.77 seconds |
| Started | Sep 04 08:39:48 AM UTC 24 |
| Finished | Sep 04 08:40:17 AM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740431857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.740431857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.969195096 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 72118642173 ps |
| CPU time | 175 seconds |
| Started | Sep 04 08:41:37 AM UTC 24 |
| Finished | Sep 04 08:44:35 AM UTC 24 |
| Peak memory | 278424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=969195096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.969195096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.2894413183 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5026466655 ps |
| CPU time | 23.77 seconds |
| Started | Sep 04 08:44:18 AM UTC 24 |
| Finished | Sep 04 08:44:43 AM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894413183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.2894413183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.497149789 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 172281542 ps |
| CPU time | 4.64 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:24 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497149789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.497149789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.3654128292 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 707902475 ps |
| CPU time | 9.42 seconds |
| Started | Sep 04 08:47:55 AM UTC 24 |
| Finished | Sep 04 08:48:05 AM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654128292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.3654128292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.3487568145 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 168624357 ps |
| CPU time | 3.65 seconds |
| Started | Sep 04 08:48:12 AM UTC 24 |
| Finished | Sep 04 08:48:17 AM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487568145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.3487568145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.3163434820 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 393730112 ps |
| CPU time | 6.95 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:49 AM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163434820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3163434820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.3898370429 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 231742548 ps |
| CPU time | 5.22 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:13 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898370429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.3898370429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.1556400911 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5047710252 ps |
| CPU time | 21.34 seconds |
| Started | Sep 04 08:42:31 AM UTC 24 |
| Finished | Sep 04 08:42:54 AM UTC 24 |
| Peak memory | 253688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556400911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.1556400911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2645580568 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2141952240 ps |
| CPU time | 24.67 seconds |
| Started | Sep 04 08:38:21 AM UTC 24 |
| Finished | Sep 04 08:38:47 AM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645580568 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.2645580568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.3855986810 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 14254269789 ps |
| CPU time | 115.86 seconds |
| Started | Sep 04 08:43:13 AM UTC 24 |
| Finished | Sep 04 08:45:12 AM UTC 24 |
| Peak memory | 267952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3855986810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.otp_ctrl_stress_all_with_rand_reset.3855986810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.2508363430 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 10041137845 ps |
| CPU time | 82.73 seconds |
| Started | Sep 04 08:45:03 AM UTC 24 |
| Finished | Sep 04 08:46:28 AM UTC 24 |
| Peak memory | 257968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2508363430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.otp_ctrl_stress_all_with_rand_reset.2508363430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.3360085405 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 292687112 ps |
| CPU time | 11.49 seconds |
| Started | Sep 04 08:40:34 AM UTC 24 |
| Finished | Sep 04 08:40:47 AM UTC 24 |
| Peak memory | 251608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360085405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.3360085405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.882105630 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1329117544 ps |
| CPU time | 29.05 seconds |
| Started | Sep 04 08:41:30 AM UTC 24 |
| Finished | Sep 04 08:42:01 AM UTC 24 |
| Peak memory | 253372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882105630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.882105630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.690076129 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 4801208841 ps |
| CPU time | 19.79 seconds |
| Started | Sep 04 08:38:12 AM UTC 24 |
| Finished | Sep 04 08:38:33 AM UTC 24 |
| Peak memory | 252832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690076129 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.690076129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.1854975213 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3472031570 ps |
| CPU time | 19.79 seconds |
| Started | Sep 04 08:42:45 AM UTC 24 |
| Finished | Sep 04 08:43:07 AM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854975213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.1854975213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.2817357105 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 368655631 ps |
| CPU time | 6.27 seconds |
| Started | Sep 04 08:42:50 AM UTC 24 |
| Finished | Sep 04 08:42:58 AM UTC 24 |
| Peak memory | 257680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817357105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.2817357105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.2570173531 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 2911856950 ps |
| CPU time | 39.37 seconds |
| Started | Sep 04 08:41:09 AM UTC 24 |
| Finished | Sep 04 08:41:50 AM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570173531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.2570173531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.3826973368 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3841366665 ps |
| CPU time | 34.99 seconds |
| Started | Sep 04 08:39:08 AM UTC 24 |
| Finished | Sep 04 08:39:45 AM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826973368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.3826973368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.3907490079 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1179457303 ps |
| CPU time | 13.53 seconds |
| Started | Sep 04 08:45:39 AM UTC 24 |
| Finished | Sep 04 08:45:54 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907490079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.3907490079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.397616589 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 128439122 ps |
| CPU time | 3.5 seconds |
| Started | Sep 04 08:49:29 AM UTC 24 |
| Finished | Sep 04 08:49:34 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397616589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.397616589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3884020441 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 57280490 ps |
| CPU time | 4.19 seconds |
| Started | Sep 04 08:37:44 AM UTC 24 |
| Finished | Sep 04 08:37:49 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884020441 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.3884020441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.1063737732 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1049493465 ps |
| CPU time | 12.22 seconds |
| Started | Sep 04 08:39:23 AM UTC 24 |
| Finished | Sep 04 08:39:36 AM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063737732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.1063737732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.3981204192 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 65314138925 ps |
| CPU time | 103.09 seconds |
| Started | Sep 04 08:43:35 AM UTC 24 |
| Finished | Sep 04 08:45:21 AM UTC 24 |
| Peak memory | 257580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981204192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.3981204192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.2235775853 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 49488025210 ps |
| CPU time | 172.3 seconds |
| Started | Sep 04 08:41:17 AM UTC 24 |
| Finished | Sep 04 08:44:12 AM UTC 24 |
| Peak memory | 272112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235775853 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.2235775853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.50600014 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 266073451 ps |
| CPU time | 5.23 seconds |
| Started | Sep 04 08:39:08 AM UTC 24 |
| Finished | Sep 04 08:39:14 AM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50600014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.50600014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.3831932439 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 318416381 ps |
| CPU time | 5.03 seconds |
| Started | Sep 04 08:40:41 AM UTC 24 |
| Finished | Sep 04 08:40:49 AM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831932439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3831932439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1191773871 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1271957291 ps |
| CPU time | 12.7 seconds |
| Started | Sep 04 08:38:24 AM UTC 24 |
| Finished | Sep 04 08:38:38 AM UTC 24 |
| Peak memory | 256780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191773871 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.1191773871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.926648912 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 430565642 ps |
| CPU time | 16.4 seconds |
| Started | Sep 04 08:48:25 AM UTC 24 |
| Finished | Sep 04 08:48:42 AM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926648912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.926648912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.48392842 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1641207166 ps |
| CPU time | 5.52 seconds |
| Started | Sep 04 08:38:06 AM UTC 24 |
| Finished | Sep 04 08:38:13 AM UTC 24 |
| Peak memory | 259000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48392842 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.48392842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.595163871 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 154716314339 ps |
| CPU time | 211.8 seconds |
| Started | Sep 04 08:39:10 AM UTC 24 |
| Finished | Sep 04 08:42:45 AM UTC 24 |
| Peak memory | 290292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595163871 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.595163871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.35516040 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 220594870 ps |
| CPU time | 2.26 seconds |
| Started | Sep 04 08:38:57 AM UTC 24 |
| Finished | Sep 04 08:39:00 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35516040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.35516040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.2048974204 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1497577252 ps |
| CPU time | 19.96 seconds |
| Started | Sep 04 08:42:36 AM UTC 24 |
| Finished | Sep 04 08:42:57 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048974204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.2048974204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.836579856 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 798643860 ps |
| CPU time | 17.16 seconds |
| Started | Sep 04 08:39:57 AM UTC 24 |
| Finished | Sep 04 08:40:15 AM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836579856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.836579856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.22384488 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 197816741 ps |
| CPU time | 3.18 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22384488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.22384488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.3304734137 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 8629672422 ps |
| CPU time | 134.57 seconds |
| Started | Sep 04 08:45:25 AM UTC 24 |
| Finished | Sep 04 08:47:42 AM UTC 24 |
| Peak memory | 257724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304734137 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.3304734137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.3615266711 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 10555228892 ps |
| CPU time | 28.59 seconds |
| Started | Sep 04 08:42:07 AM UTC 24 |
| Finished | Sep 04 08:42:37 AM UTC 24 |
| Peak memory | 253496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615266711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.3615266711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.1481301422 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 181865149 ps |
| CPU time | 7.69 seconds |
| Started | Sep 04 08:40:05 AM UTC 24 |
| Finished | Sep 04 08:40:14 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481301422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.1481301422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.2569136542 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 217314746 ps |
| CPU time | 3.28 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:45 AM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569136542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.2569136542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.2832686816 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 230872018 ps |
| CPU time | 2.76 seconds |
| Started | Sep 04 08:49:17 AM UTC 24 |
| Finished | Sep 04 08:49:21 AM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832686816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.2832686816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.2816390928 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1484486427 ps |
| CPU time | 4.84 seconds |
| Started | Sep 04 08:43:32 AM UTC 24 |
| Finished | Sep 04 08:43:38 AM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816390928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.2816390928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.3017484255 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 105757285 ps |
| CPU time | 5.91 seconds |
| Started | Sep 04 08:46:22 AM UTC 24 |
| Finished | Sep 04 08:46:29 AM UTC 24 |
| Peak memory | 252152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017484255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.3017484255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.2275179954 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2917325721 ps |
| CPU time | 22.74 seconds |
| Started | Sep 04 08:40:53 AM UTC 24 |
| Finished | Sep 04 08:41:17 AM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275179954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.2275179954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2439567249 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 81339433 ps |
| CPU time | 4.89 seconds |
| Started | Sep 04 08:37:36 AM UTC 24 |
| Finished | Sep 04 08:37:42 AM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439567249 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.2439567249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.666187286 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 840198345 ps |
| CPU time | 8.79 seconds |
| Started | Sep 04 08:37:36 AM UTC 24 |
| Finished | Sep 04 08:37:46 AM UTC 24 |
| Peak memory | 252348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666187286 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.666187286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1527065877 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 89625726 ps |
| CPU time | 3.01 seconds |
| Started | Sep 04 08:37:35 AM UTC 24 |
| Finished | Sep 04 08:37:39 AM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527065877 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.1527065877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.4283100893 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 256069483 ps |
| CPU time | 4.15 seconds |
| Started | Sep 04 08:37:39 AM UTC 24 |
| Finished | Sep 04 08:37:44 AM UTC 24 |
| Peak memory | 259000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4283100893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_cs r_mem_rw_with_rand_reset.4283100893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.318459073 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 51903854 ps |
| CPU time | 2.51 seconds |
| Started | Sep 04 08:37:34 AM UTC 24 |
| Finished | Sep 04 08:37:37 AM UTC 24 |
| Peak memory | 241952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318459073 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.318459073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.520855024 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 72609662 ps |
| CPU time | 2.31 seconds |
| Started | Sep 04 08:37:35 AM UTC 24 |
| Finished | Sep 04 08:37:38 AM UTC 24 |
| Peak memory | 241200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520855024 -assert nopostproc +U VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.520855024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3667628972 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 101224147 ps |
| CPU time | 2.21 seconds |
| Started | Sep 04 08:37:35 AM UTC 24 |
| Finished | Sep 04 08:37:38 AM UTC 24 |
| Peak memory | 241424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667628972 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.3667628972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.2709549133 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1024283216 ps |
| CPU time | 4.16 seconds |
| Started | Sep 04 08:37:38 AM UTC 24 |
| Finished | Sep 04 08:37:43 AM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709549133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.2709549133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2236852016 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 64638359 ps |
| CPU time | 5.49 seconds |
| Started | Sep 04 08:37:33 AM UTC 24 |
| Finished | Sep 04 08:37:39 AM UTC 24 |
| Peak memory | 259096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236852016 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.2236852016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3156501018 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1933604567 ps |
| CPU time | 20.39 seconds |
| Started | Sep 04 08:37:33 AM UTC 24 |
| Finished | Sep 04 08:37:54 AM UTC 24 |
| Peak memory | 256872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156501018 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.3156501018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2949363956 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 248069223 ps |
| CPU time | 9.53 seconds |
| Started | Sep 04 08:37:43 AM UTC 24 |
| Finished | Sep 04 08:37:53 AM UTC 24 |
| Peak memory | 242528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949363956 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.2949363956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.375452012 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1017066442 ps |
| CPU time | 4.53 seconds |
| Started | Sep 04 08:37:41 AM UTC 24 |
| Finished | Sep 04 08:37:46 AM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375452012 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.375452012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.596233784 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1665147146 ps |
| CPU time | 5.27 seconds |
| Started | Sep 04 08:37:45 AM UTC 24 |
| Finished | Sep 04 08:37:51 AM UTC 24 |
| Peak memory | 258960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=596233784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr _mem_rw_with_rand_reset.596233784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1422177404 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 52010449 ps |
| CPU time | 2.27 seconds |
| Started | Sep 04 08:37:42 AM UTC 24 |
| Finished | Sep 04 08:37:45 AM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422177404 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1422177404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.1513571547 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 46698189 ps |
| CPU time | 2.38 seconds |
| Started | Sep 04 08:37:40 AM UTC 24 |
| Finished | Sep 04 08:37:44 AM UTC 24 |
| Peak memory | 241716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513571547 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.1513571547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3405504325 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 36226443 ps |
| CPU time | 2.24 seconds |
| Started | Sep 04 08:37:40 AM UTC 24 |
| Finished | Sep 04 08:37:44 AM UTC 24 |
| Peak memory | 241196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405504325 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.3405504325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.965699461 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 36305291 ps |
| CPU time | 2.18 seconds |
| Started | Sep 04 08:37:40 AM UTC 24 |
| Finished | Sep 04 08:37:44 AM UTC 24 |
| Peak memory | 241560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965699461 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.965699461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2859290955 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 654479247 ps |
| CPU time | 2.46 seconds |
| Started | Sep 04 08:37:45 AM UTC 24 |
| Finished | Sep 04 08:37:48 AM UTC 24 |
| Peak memory | 254676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859290955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.2859290955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2182215895 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 73009348 ps |
| CPU time | 6.85 seconds |
| Started | Sep 04 08:37:39 AM UTC 24 |
| Finished | Sep 04 08:37:47 AM UTC 24 |
| Peak memory | 252816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182215895 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.2182215895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1336889231 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2499223316 ps |
| CPU time | 16.33 seconds |
| Started | Sep 04 08:37:40 AM UTC 24 |
| Finished | Sep 04 08:37:58 AM UTC 24 |
| Peak memory | 257036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336889231 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.1336889231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2909015121 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 236394966 ps |
| CPU time | 4.15 seconds |
| Started | Sep 04 08:38:13 AM UTC 24 |
| Finished | Sep 04 08:38:18 AM UTC 24 |
| Peak memory | 258940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2909015121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_c sr_mem_rw_with_rand_reset.2909015121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3299521094 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 36943258 ps |
| CPU time | 2.33 seconds |
| Started | Sep 04 08:38:13 AM UTC 24 |
| Finished | Sep 04 08:38:16 AM UTC 24 |
| Peak memory | 254808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299521094 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3299521094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.1200457103 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 138413054 ps |
| CPU time | 2.17 seconds |
| Started | Sep 04 08:38:12 AM UTC 24 |
| Finished | Sep 04 08:38:15 AM UTC 24 |
| Peak memory | 242596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200457103 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.1200457103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1800168702 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 660197106 ps |
| CPU time | 2.59 seconds |
| Started | Sep 04 08:38:13 AM UTC 24 |
| Finished | Sep 04 08:38:17 AM UTC 24 |
| Peak memory | 252628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800168702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.1800168702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3298736075 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 754670110 ps |
| CPU time | 4.43 seconds |
| Started | Sep 04 08:38:11 AM UTC 24 |
| Finished | Sep 04 08:38:16 AM UTC 24 |
| Peak memory | 259004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298736075 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3298736075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3086374373 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 109496224 ps |
| CPU time | 4.51 seconds |
| Started | Sep 04 08:38:15 AM UTC 24 |
| Finished | Sep 04 08:38:21 AM UTC 24 |
| Peak memory | 258876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3086374373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_c sr_mem_rw_with_rand_reset.3086374373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3709527756 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 171436396 ps |
| CPU time | 2.79 seconds |
| Started | Sep 04 08:38:14 AM UTC 24 |
| Finished | Sep 04 08:38:18 AM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709527756 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.3709527756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.3189585339 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 142149696 ps |
| CPU time | 2.3 seconds |
| Started | Sep 04 08:38:14 AM UTC 24 |
| Finished | Sep 04 08:38:18 AM UTC 24 |
| Peak memory | 241700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189585339 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.3189585339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2673798591 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 650168110 ps |
| CPU time | 3.18 seconds |
| Started | Sep 04 08:38:15 AM UTC 24 |
| Finished | Sep 04 08:38:20 AM UTC 24 |
| Peak memory | 252628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673798591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.2673798591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3136974607 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 3216256525 ps |
| CPU time | 9.41 seconds |
| Started | Sep 04 08:38:14 AM UTC 24 |
| Finished | Sep 04 08:38:25 AM UTC 24 |
| Peak memory | 259224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136974607 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.3136974607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1680427961 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1306416908 ps |
| CPU time | 20.82 seconds |
| Started | Sep 04 08:38:14 AM UTC 24 |
| Finished | Sep 04 08:38:36 AM UTC 24 |
| Peak memory | 256908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680427961 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.1680427961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.3777797438 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 198754895 ps |
| CPU time | 3.79 seconds |
| Started | Sep 04 08:38:18 AM UTC 24 |
| Finished | Sep 04 08:38:23 AM UTC 24 |
| Peak memory | 258968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3777797438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_c sr_mem_rw_with_rand_reset.3777797438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.3672467974 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 62839855 ps |
| CPU time | 2.73 seconds |
| Started | Sep 04 08:38:18 AM UTC 24 |
| Finished | Sep 04 08:38:21 AM UTC 24 |
| Peak memory | 252900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672467974 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.3672467974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.4159525495 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 160395820 ps |
| CPU time | 2.3 seconds |
| Started | Sep 04 08:38:17 AM UTC 24 |
| Finished | Sep 04 08:38:20 AM UTC 24 |
| Peak memory | 242140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159525495 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.4159525495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1393637330 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 168047986 ps |
| CPU time | 2.03 seconds |
| Started | Sep 04 08:38:18 AM UTC 24 |
| Finished | Sep 04 08:38:21 AM UTC 24 |
| Peak memory | 252956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393637330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.1393637330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3285021017 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 175737455 ps |
| CPU time | 6.79 seconds |
| Started | Sep 04 08:38:15 AM UTC 24 |
| Finished | Sep 04 08:38:23 AM UTC 24 |
| Peak memory | 259032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285021017 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.3285021017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2439759512 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 5083876127 ps |
| CPU time | 25.94 seconds |
| Started | Sep 04 08:38:16 AM UTC 24 |
| Finished | Sep 04 08:38:43 AM UTC 24 |
| Peak memory | 256972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439759512 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.2439759512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.981562827 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 105406206 ps |
| CPU time | 3.57 seconds |
| Started | Sep 04 08:38:20 AM UTC 24 |
| Finished | Sep 04 08:38:25 AM UTC 24 |
| Peak memory | 256888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=981562827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_cs r_mem_rw_with_rand_reset.981562827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.181344217 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 606169856 ps |
| CPU time | 2.51 seconds |
| Started | Sep 04 08:38:19 AM UTC 24 |
| Finished | Sep 04 08:38:22 AM UTC 24 |
| Peak memory | 254680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181344217 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.181344217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.1103160450 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 70581696 ps |
| CPU time | 2.42 seconds |
| Started | Sep 04 08:38:19 AM UTC 24 |
| Finished | Sep 04 08:38:22 AM UTC 24 |
| Peak memory | 242608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103160450 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.1103160450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3528375426 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 76217003 ps |
| CPU time | 3.06 seconds |
| Started | Sep 04 08:38:19 AM UTC 24 |
| Finished | Sep 04 08:38:23 AM UTC 24 |
| Peak memory | 252864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528375426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.3528375426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3530149644 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 299135924 ps |
| CPU time | 6 seconds |
| Started | Sep 04 08:38:18 AM UTC 24 |
| Finished | Sep 04 08:38:25 AM UTC 24 |
| Peak memory | 259032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530149644 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3530149644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.38884894 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 4800568739 ps |
| CPU time | 20.76 seconds |
| Started | Sep 04 08:38:19 AM UTC 24 |
| Finished | Sep 04 08:38:41 AM UTC 24 |
| Peak memory | 256916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38884894 -assert nopostproc +UVM_TESTN AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.38884894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.3251379472 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 270218208 ps |
| CPU time | 3.71 seconds |
| Started | Sep 04 08:38:22 AM UTC 24 |
| Finished | Sep 04 08:38:27 AM UTC 24 |
| Peak memory | 259032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3251379472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_c sr_mem_rw_with_rand_reset.3251379472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3015719204 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 56497991 ps |
| CPU time | 2.8 seconds |
| Started | Sep 04 08:38:21 AM UTC 24 |
| Finished | Sep 04 08:38:25 AM UTC 24 |
| Peak memory | 254628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015719204 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.3015719204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.889576986 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 69974011 ps |
| CPU time | 1.7 seconds |
| Started | Sep 04 08:38:21 AM UTC 24 |
| Finished | Sep 04 08:38:24 AM UTC 24 |
| Peak memory | 241128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889576986 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.889576986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3392219308 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 254650799 ps |
| CPU time | 3.55 seconds |
| Started | Sep 04 08:38:21 AM UTC 24 |
| Finished | Sep 04 08:38:26 AM UTC 24 |
| Peak memory | 254852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392219308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.3392219308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3780931751 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 165295124 ps |
| CPU time | 7.13 seconds |
| Started | Sep 04 08:38:20 AM UTC 24 |
| Finished | Sep 04 08:38:28 AM UTC 24 |
| Peak memory | 258964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780931751 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3780931751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1488706921 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 204316176 ps |
| CPU time | 6.07 seconds |
| Started | Sep 04 08:38:25 AM UTC 24 |
| Finished | Sep 04 08:38:32 AM UTC 24 |
| Peak memory | 259040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1488706921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_c sr_mem_rw_with_rand_reset.1488706921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1255100607 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 137438276 ps |
| CPU time | 2.47 seconds |
| Started | Sep 04 08:38:24 AM UTC 24 |
| Finished | Sep 04 08:38:28 AM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255100607 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.1255100607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.2803412110 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 50278067 ps |
| CPU time | 2.25 seconds |
| Started | Sep 04 08:38:24 AM UTC 24 |
| Finished | Sep 04 08:38:27 AM UTC 24 |
| Peak memory | 242008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803412110 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.2803412110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.1773536741 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 119392664 ps |
| CPU time | 4.03 seconds |
| Started | Sep 04 08:38:25 AM UTC 24 |
| Finished | Sep 04 08:38:30 AM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773536741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.1773536741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1106971774 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 841443078 ps |
| CPU time | 3.94 seconds |
| Started | Sep 04 08:38:24 AM UTC 24 |
| Finished | Sep 04 08:38:29 AM UTC 24 |
| Peak memory | 259024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106971774 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1106971774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.3811972593 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 267809326 ps |
| CPU time | 5.24 seconds |
| Started | Sep 04 08:38:26 AM UTC 24 |
| Finished | Sep 04 08:38:33 AM UTC 24 |
| Peak memory | 259104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3811972593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_c sr_mem_rw_with_rand_reset.3811972593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.725086468 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 41497915 ps |
| CPU time | 1.77 seconds |
| Started | Sep 04 08:38:26 AM UTC 24 |
| Finished | Sep 04 08:38:29 AM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725086468 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.725086468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.916529685 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 142279346 ps |
| CPU time | 2.58 seconds |
| Started | Sep 04 08:38:26 AM UTC 24 |
| Finished | Sep 04 08:38:30 AM UTC 24 |
| Peak memory | 241740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916529685 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.916529685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.1253041932 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 426248004 ps |
| CPU time | 5.41 seconds |
| Started | Sep 04 08:38:26 AM UTC 24 |
| Finished | Sep 04 08:38:33 AM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253041932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.1253041932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3741461361 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 826442679 ps |
| CPU time | 5.87 seconds |
| Started | Sep 04 08:38:25 AM UTC 24 |
| Finished | Sep 04 08:38:32 AM UTC 24 |
| Peak memory | 259040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741461361 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.3741461361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.4141306922 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 781692788 ps |
| CPU time | 11.54 seconds |
| Started | Sep 04 08:38:26 AM UTC 24 |
| Finished | Sep 04 08:38:39 AM UTC 24 |
| Peak memory | 256924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141306922 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.4141306922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3432639560 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 268655272 ps |
| CPU time | 4.48 seconds |
| Started | Sep 04 08:38:28 AM UTC 24 |
| Finished | Sep 04 08:38:34 AM UTC 24 |
| Peak memory | 258964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3432639560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_c sr_mem_rw_with_rand_reset.3432639560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1838366984 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 674228305 ps |
| CPU time | 3.29 seconds |
| Started | Sep 04 08:38:28 AM UTC 24 |
| Finished | Sep 04 08:38:33 AM UTC 24 |
| Peak memory | 254756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838366984 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.1838366984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.1336321882 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 131434392 ps |
| CPU time | 2.24 seconds |
| Started | Sep 04 08:38:28 AM UTC 24 |
| Finished | Sep 04 08:38:32 AM UTC 24 |
| Peak memory | 242380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336321882 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.1336321882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.4256464884 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 55358709 ps |
| CPU time | 3.04 seconds |
| Started | Sep 04 08:38:28 AM UTC 24 |
| Finished | Sep 04 08:38:33 AM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256464884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.4256464884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.172434379 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 118420181 ps |
| CPU time | 3.92 seconds |
| Started | Sep 04 08:38:26 AM UTC 24 |
| Finished | Sep 04 08:38:31 AM UTC 24 |
| Peak memory | 259000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172434379 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.172434379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3446005185 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 2344920142 ps |
| CPU time | 22.67 seconds |
| Started | Sep 04 08:38:27 AM UTC 24 |
| Finished | Sep 04 08:38:51 AM UTC 24 |
| Peak memory | 257064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446005185 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.3446005185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1562514957 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 129124426 ps |
| CPU time | 3.33 seconds |
| Started | Sep 04 08:38:31 AM UTC 24 |
| Finished | Sep 04 08:38:35 AM UTC 24 |
| Peak memory | 256052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1562514957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_c sr_mem_rw_with_rand_reset.1562514957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.1296331448 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 77584181 ps |
| CPU time | 2.51 seconds |
| Started | Sep 04 08:38:30 AM UTC 24 |
| Finished | Sep 04 08:38:33 AM UTC 24 |
| Peak memory | 254740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296331448 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.1296331448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.3905124821 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 135870813 ps |
| CPU time | 2.22 seconds |
| Started | Sep 04 08:38:30 AM UTC 24 |
| Finished | Sep 04 08:38:33 AM UTC 24 |
| Peak memory | 241664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905124821 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.3905124821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1706751483 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 168208027 ps |
| CPU time | 2.13 seconds |
| Started | Sep 04 08:38:30 AM UTC 24 |
| Finished | Sep 04 08:38:33 AM UTC 24 |
| Peak memory | 252884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706751483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.1706751483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2153608223 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 145659131 ps |
| CPU time | 5.92 seconds |
| Started | Sep 04 08:38:30 AM UTC 24 |
| Finished | Sep 04 08:38:37 AM UTC 24 |
| Peak memory | 259028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153608223 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.2153608223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3933233952 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 19967525940 ps |
| CPU time | 19.82 seconds |
| Started | Sep 04 08:38:30 AM UTC 24 |
| Finished | Sep 04 08:38:51 AM UTC 24 |
| Peak memory | 256856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933233952 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.3933233952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1863202484 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 267783667 ps |
| CPU time | 2.37 seconds |
| Started | Sep 04 08:38:33 AM UTC 24 |
| Finished | Sep 04 08:38:36 AM UTC 24 |
| Peak memory | 256868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1863202484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_c sr_mem_rw_with_rand_reset.1863202484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.798270406 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 152444980 ps |
| CPU time | 2.76 seconds |
| Started | Sep 04 08:38:33 AM UTC 24 |
| Finished | Sep 04 08:38:37 AM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798270406 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.798270406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.2798101645 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 157234092 ps |
| CPU time | 2.22 seconds |
| Started | Sep 04 08:38:33 AM UTC 24 |
| Finished | Sep 04 08:38:36 AM UTC 24 |
| Peak memory | 242560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798101645 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.2798101645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1519813146 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 395775579 ps |
| CPU time | 3.85 seconds |
| Started | Sep 04 08:38:33 AM UTC 24 |
| Finished | Sep 04 08:38:38 AM UTC 24 |
| Peak memory | 252760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519813146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.1519813146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1547190927 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 244349294 ps |
| CPU time | 4.21 seconds |
| Started | Sep 04 08:38:31 AM UTC 24 |
| Finished | Sep 04 08:38:36 AM UTC 24 |
| Peak memory | 258296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547190927 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.1547190927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1282128230 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 683573365 ps |
| CPU time | 11.48 seconds |
| Started | Sep 04 08:38:32 AM UTC 24 |
| Finished | Sep 04 08:38:45 AM UTC 24 |
| Peak memory | 256732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282128230 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.1282128230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3017951337 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 179744148 ps |
| CPU time | 8.18 seconds |
| Started | Sep 04 08:37:48 AM UTC 24 |
| Finished | Sep 04 08:37:57 AM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017951337 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.3017951337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3731284430 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 774017944 ps |
| CPU time | 9.35 seconds |
| Started | Sep 04 08:37:48 AM UTC 24 |
| Finished | Sep 04 08:37:58 AM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731284430 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.3731284430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2700013322 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 92522606 ps |
| CPU time | 3.7 seconds |
| Started | Sep 04 08:37:47 AM UTC 24 |
| Finished | Sep 04 08:37:52 AM UTC 24 |
| Peak memory | 254740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700013322 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.2700013322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2561282160 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 71623993 ps |
| CPU time | 3.66 seconds |
| Started | Sep 04 08:37:49 AM UTC 24 |
| Finished | Sep 04 08:37:53 AM UTC 24 |
| Peak memory | 258952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2561282160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_cs r_mem_rw_with_rand_reset.2561282160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.3154265634 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 653222132 ps |
| CPU time | 3.29 seconds |
| Started | Sep 04 08:37:48 AM UTC 24 |
| Finished | Sep 04 08:37:52 AM UTC 24 |
| Peak memory | 252760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154265634 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.3154265634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.2968258725 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 41002437 ps |
| CPU time | 1.3 seconds |
| Started | Sep 04 08:37:45 AM UTC 24 |
| Finished | Sep 04 08:37:47 AM UTC 24 |
| Peak memory | 241196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968258725 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.2968258725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1794925882 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 70437605 ps |
| CPU time | 1.97 seconds |
| Started | Sep 04 08:37:46 AM UTC 24 |
| Finished | Sep 04 08:37:49 AM UTC 24 |
| Peak memory | 240536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794925882 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.1794925882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.218527572 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 147692361 ps |
| CPU time | 1.37 seconds |
| Started | Sep 04 08:37:46 AM UTC 24 |
| Finished | Sep 04 08:37:48 AM UTC 24 |
| Peak memory | 241612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218527572 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.218527572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3490489381 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 118596941 ps |
| CPU time | 5.38 seconds |
| Started | Sep 04 08:37:49 AM UTC 24 |
| Finished | Sep 04 08:37:55 AM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490489381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.3490489381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3337830499 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 849008982 ps |
| CPU time | 5.45 seconds |
| Started | Sep 04 08:37:45 AM UTC 24 |
| Finished | Sep 04 08:37:51 AM UTC 24 |
| Peak memory | 259000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337830499 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3337830499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.754599656 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 675376556 ps |
| CPU time | 9.71 seconds |
| Started | Sep 04 08:37:45 AM UTC 24 |
| Finished | Sep 04 08:37:56 AM UTC 24 |
| Peak memory | 256860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754599656 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.754599656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.2792373682 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 131182434 ps |
| CPU time | 2.24 seconds |
| Started | Sep 04 08:38:33 AM UTC 24 |
| Finished | Sep 04 08:38:36 AM UTC 24 |
| Peak memory | 241704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792373682 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.2792373682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.1323547369 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 551572511 ps |
| CPU time | 2.42 seconds |
| Started | Sep 04 08:38:33 AM UTC 24 |
| Finished | Sep 04 08:38:37 AM UTC 24 |
| Peak memory | 241864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323547369 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.1323547369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.1363629511 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 37801527 ps |
| CPU time | 2.23 seconds |
| Started | Sep 04 08:38:34 AM UTC 24 |
| Finished | Sep 04 08:38:38 AM UTC 24 |
| Peak memory | 242660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363629511 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.1363629511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.830187251 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 52851271 ps |
| CPU time | 1.99 seconds |
| Started | Sep 04 08:38:34 AM UTC 24 |
| Finished | Sep 04 08:38:37 AM UTC 24 |
| Peak memory | 241188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830187251 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.830187251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.2663904940 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 136032958 ps |
| CPU time | 2.08 seconds |
| Started | Sep 04 08:38:34 AM UTC 24 |
| Finished | Sep 04 08:38:38 AM UTC 24 |
| Peak memory | 241692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663904940 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.2663904940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.370589554 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 46814419 ps |
| CPU time | 2.22 seconds |
| Started | Sep 04 08:38:34 AM UTC 24 |
| Finished | Sep 04 08:38:38 AM UTC 24 |
| Peak memory | 242468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370589554 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.370589554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.140072509 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 66416079 ps |
| CPU time | 2.1 seconds |
| Started | Sep 04 08:38:35 AM UTC 24 |
| Finished | Sep 04 08:38:38 AM UTC 24 |
| Peak memory | 242596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140072509 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.140072509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.3222512009 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 582019854 ps |
| CPU time | 2.15 seconds |
| Started | Sep 04 08:38:35 AM UTC 24 |
| Finished | Sep 04 08:38:38 AM UTC 24 |
| Peak memory | 242116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222512009 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.3222512009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.749161588 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 152343021 ps |
| CPU time | 1.81 seconds |
| Started | Sep 04 08:38:36 AM UTC 24 |
| Finished | Sep 04 08:38:39 AM UTC 24 |
| Peak memory | 241696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749161588 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.749161588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.2754537204 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 140563076 ps |
| CPU time | 1.76 seconds |
| Started | Sep 04 08:38:36 AM UTC 24 |
| Finished | Sep 04 08:38:39 AM UTC 24 |
| Peak memory | 241636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754537204 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.2754537204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.4008360462 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 81827547 ps |
| CPU time | 5.44 seconds |
| Started | Sep 04 08:37:54 AM UTC 24 |
| Finished | Sep 04 08:38:01 AM UTC 24 |
| Peak memory | 252824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008360462 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.4008360462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2498093827 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1671550940 ps |
| CPU time | 10.67 seconds |
| Started | Sep 04 08:37:53 AM UTC 24 |
| Finished | Sep 04 08:38:05 AM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498093827 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.2498093827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3624954653 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1442487769 ps |
| CPU time | 3.49 seconds |
| Started | Sep 04 08:37:52 AM UTC 24 |
| Finished | Sep 04 08:37:57 AM UTC 24 |
| Peak memory | 254676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624954653 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.3624954653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2040971499 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 206923174 ps |
| CPU time | 3.2 seconds |
| Started | Sep 04 08:37:54 AM UTC 24 |
| Finished | Sep 04 08:37:59 AM UTC 24 |
| Peak memory | 258820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2040971499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_cs r_mem_rw_with_rand_reset.2040971499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2236202673 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 141422485 ps |
| CPU time | 2.44 seconds |
| Started | Sep 04 08:37:53 AM UTC 24 |
| Finished | Sep 04 08:37:57 AM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236202673 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.2236202673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.865104264 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 104940343 ps |
| CPU time | 2.39 seconds |
| Started | Sep 04 08:37:50 AM UTC 24 |
| Finished | Sep 04 08:37:53 AM UTC 24 |
| Peak memory | 242152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865104264 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.865104264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1765724725 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 73269771 ps |
| CPU time | 2.22 seconds |
| Started | Sep 04 08:37:52 AM UTC 24 |
| Finished | Sep 04 08:37:55 AM UTC 24 |
| Peak memory | 241452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765724725 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.1765724725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3405722586 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 39329320 ps |
| CPU time | 2.04 seconds |
| Started | Sep 04 08:37:50 AM UTC 24 |
| Finished | Sep 04 08:37:53 AM UTC 24 |
| Peak memory | 241504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405722586 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.3405722586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1725996839 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 961865617 ps |
| CPU time | 3.7 seconds |
| Started | Sep 04 08:37:54 AM UTC 24 |
| Finished | Sep 04 08:37:59 AM UTC 24 |
| Peak memory | 252624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725996839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.1725996839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.307190105 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 647425390 ps |
| CPU time | 8.6 seconds |
| Started | Sep 04 08:37:49 AM UTC 24 |
| Finished | Sep 04 08:37:58 AM UTC 24 |
| Peak memory | 258960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307190105 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.307190105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.306414933 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1470797175 ps |
| CPU time | 14.59 seconds |
| Started | Sep 04 08:37:50 AM UTC 24 |
| Finished | Sep 04 08:38:06 AM UTC 24 |
| Peak memory | 256984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306414933 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.306414933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.3282786971 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 44544898 ps |
| CPU time | 1.57 seconds |
| Started | Sep 04 08:38:37 AM UTC 24 |
| Finished | Sep 04 08:38:39 AM UTC 24 |
| Peak memory | 241688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282786971 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.3282786971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.217928809 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 51501402 ps |
| CPU time | 1.65 seconds |
| Started | Sep 04 08:38:37 AM UTC 24 |
| Finished | Sep 04 08:38:39 AM UTC 24 |
| Peak memory | 241748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217928809 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.217928809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.2071255609 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 39097556 ps |
| CPU time | 1.83 seconds |
| Started | Sep 04 08:38:37 AM UTC 24 |
| Finished | Sep 04 08:38:40 AM UTC 24 |
| Peak memory | 241108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071255609 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.2071255609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.1239720499 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 535372772 ps |
| CPU time | 2.21 seconds |
| Started | Sep 04 08:38:37 AM UTC 24 |
| Finished | Sep 04 08:38:40 AM UTC 24 |
| Peak memory | 241684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239720499 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.1239720499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.1004364984 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 38914035 ps |
| CPU time | 2 seconds |
| Started | Sep 04 08:38:38 AM UTC 24 |
| Finished | Sep 04 08:38:41 AM UTC 24 |
| Peak memory | 240996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004364984 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.1004364984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.301237693 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 80366605 ps |
| CPU time | 2.43 seconds |
| Started | Sep 04 08:38:38 AM UTC 24 |
| Finished | Sep 04 08:38:41 AM UTC 24 |
| Peak memory | 242472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301237693 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.301237693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.940730114 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 572572912 ps |
| CPU time | 2.24 seconds |
| Started | Sep 04 08:38:38 AM UTC 24 |
| Finished | Sep 04 08:38:41 AM UTC 24 |
| Peak memory | 241724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940730114 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.940730114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.4219801884 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 149366259 ps |
| CPU time | 1.85 seconds |
| Started | Sep 04 08:38:38 AM UTC 24 |
| Finished | Sep 04 08:38:41 AM UTC 24 |
| Peak memory | 241636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219801884 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.4219801884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.1216565200 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 40394193 ps |
| CPU time | 2.27 seconds |
| Started | Sep 04 08:38:38 AM UTC 24 |
| Finished | Sep 04 08:38:41 AM UTC 24 |
| Peak memory | 241756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216565200 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.1216565200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.2303763113 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 138496584 ps |
| CPU time | 1.63 seconds |
| Started | Sep 04 08:38:38 AM UTC 24 |
| Finished | Sep 04 08:38:41 AM UTC 24 |
| Peak memory | 241460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303763113 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.2303763113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2503181600 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 2986012605 ps |
| CPU time | 8.98 seconds |
| Started | Sep 04 08:37:58 AM UTC 24 |
| Finished | Sep 04 08:38:08 AM UTC 24 |
| Peak memory | 252760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503181600 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.2503181600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.4220041525 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 310556761 ps |
| CPU time | 5.86 seconds |
| Started | Sep 04 08:37:58 AM UTC 24 |
| Finished | Sep 04 08:38:05 AM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220041525 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.4220041525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.16686466 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 263890474 ps |
| CPU time | 2.02 seconds |
| Started | Sep 04 08:37:57 AM UTC 24 |
| Finished | Sep 04 08:38:00 AM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16686466 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.16686466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.2646186276 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 270131583 ps |
| CPU time | 2.94 seconds |
| Started | Sep 04 08:37:59 AM UTC 24 |
| Finished | Sep 04 08:38:03 AM UTC 24 |
| Peak memory | 259100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2646186276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_cs r_mem_rw_with_rand_reset.2646186276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.1536166566 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 59539845 ps |
| CPU time | 2.36 seconds |
| Started | Sep 04 08:37:58 AM UTC 24 |
| Finished | Sep 04 08:38:01 AM UTC 24 |
| Peak memory | 254752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536166566 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.1536166566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.2832711658 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 139766901 ps |
| CPU time | 1.99 seconds |
| Started | Sep 04 08:37:56 AM UTC 24 |
| Finished | Sep 04 08:37:59 AM UTC 24 |
| Peak memory | 241196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832711658 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.2832711658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.2244027817 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 37635683 ps |
| CPU time | 1.62 seconds |
| Started | Sep 04 08:37:57 AM UTC 24 |
| Finished | Sep 04 08:37:59 AM UTC 24 |
| Peak memory | 239924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244027817 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.2244027817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.912411671 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 68119094 ps |
| CPU time | 2.28 seconds |
| Started | Sep 04 08:37:57 AM UTC 24 |
| Finished | Sep 04 08:38:00 AM UTC 24 |
| Peak memory | 241720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912411671 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.912411671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3495849654 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 179907785 ps |
| CPU time | 3.12 seconds |
| Started | Sep 04 08:37:59 AM UTC 24 |
| Finished | Sep 04 08:38:03 AM UTC 24 |
| Peak memory | 252760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495849654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.3495849654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3615875385 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 2938460666 ps |
| CPU time | 5.83 seconds |
| Started | Sep 04 08:37:54 AM UTC 24 |
| Finished | Sep 04 08:38:01 AM UTC 24 |
| Peak memory | 259092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615875385 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3615875385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.967223745 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 142421079 ps |
| CPU time | 2.14 seconds |
| Started | Sep 04 08:38:38 AM UTC 24 |
| Finished | Sep 04 08:38:41 AM UTC 24 |
| Peak memory | 241776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967223745 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.967223745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.3476513305 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 530219414 ps |
| CPU time | 2.54 seconds |
| Started | Sep 04 08:38:38 AM UTC 24 |
| Finished | Sep 04 08:38:42 AM UTC 24 |
| Peak memory | 241700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476513305 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.3476513305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.2218380239 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 136149716 ps |
| CPU time | 1.7 seconds |
| Started | Sep 04 08:38:39 AM UTC 24 |
| Finished | Sep 04 08:38:42 AM UTC 24 |
| Peak memory | 241108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218380239 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2218380239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.889182089 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 554885415 ps |
| CPU time | 2.69 seconds |
| Started | Sep 04 08:38:39 AM UTC 24 |
| Finished | Sep 04 08:38:43 AM UTC 24 |
| Peak memory | 242596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889182089 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.889182089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.4138582270 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 575133954 ps |
| CPU time | 2.62 seconds |
| Started | Sep 04 08:38:39 AM UTC 24 |
| Finished | Sep 04 08:38:43 AM UTC 24 |
| Peak memory | 242596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138582270 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.4138582270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.909838573 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 77278631 ps |
| CPU time | 1.64 seconds |
| Started | Sep 04 08:38:39 AM UTC 24 |
| Finished | Sep 04 08:38:42 AM UTC 24 |
| Peak memory | 241188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909838573 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.909838573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.1618552109 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 74626908 ps |
| CPU time | 1.39 seconds |
| Started | Sep 04 08:38:40 AM UTC 24 |
| Finished | Sep 04 08:38:42 AM UTC 24 |
| Peak memory | 241188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618552109 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.1618552109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.1455086456 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 58964294 ps |
| CPU time | 1.74 seconds |
| Started | Sep 04 08:38:40 AM UTC 24 |
| Finished | Sep 04 08:38:42 AM UTC 24 |
| Peak memory | 241636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455086456 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.1455086456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.81781624 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 602754298 ps |
| CPU time | 2.4 seconds |
| Started | Sep 04 08:38:40 AM UTC 24 |
| Finished | Sep 04 08:38:43 AM UTC 24 |
| Peak memory | 242128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81781624 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.81781624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.1241449785 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 130497605 ps |
| CPU time | 1.69 seconds |
| Started | Sep 04 08:38:41 AM UTC 24 |
| Finished | Sep 04 08:38:43 AM UTC 24 |
| Peak memory | 241620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241449785 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.1241449785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.255685315 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 124261211 ps |
| CPU time | 3.21 seconds |
| Started | Sep 04 08:38:00 AM UTC 24 |
| Finished | Sep 04 08:38:05 AM UTC 24 |
| Peak memory | 256888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=255685315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr _mem_rw_with_rand_reset.255685315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.496513643 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 94259599 ps |
| CPU time | 2.61 seconds |
| Started | Sep 04 08:38:00 AM UTC 24 |
| Finished | Sep 04 08:38:04 AM UTC 24 |
| Peak memory | 252900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496513643 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.496513643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.3947810994 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 136106920 ps |
| CPU time | 1.72 seconds |
| Started | Sep 04 08:37:59 AM UTC 24 |
| Finished | Sep 04 08:38:02 AM UTC 24 |
| Peak memory | 241460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947810994 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3947810994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.457351622 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 99623783 ps |
| CPU time | 3.33 seconds |
| Started | Sep 04 08:38:00 AM UTC 24 |
| Finished | Sep 04 08:38:05 AM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457351622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.457351622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.600684164 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 123689074 ps |
| CPU time | 4.55 seconds |
| Started | Sep 04 08:37:59 AM UTC 24 |
| Finished | Sep 04 08:38:05 AM UTC 24 |
| Peak memory | 258952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600684164 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.600684164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1157360926 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 9773669158 ps |
| CPU time | 24.66 seconds |
| Started | Sep 04 08:37:59 AM UTC 24 |
| Finished | Sep 04 08:38:25 AM UTC 24 |
| Peak memory | 252848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157360926 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.1157360926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2940216521 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 109141291 ps |
| CPU time | 3.1 seconds |
| Started | Sep 04 08:38:04 AM UTC 24 |
| Finished | Sep 04 08:38:08 AM UTC 24 |
| Peak memory | 259100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2940216521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_cs r_mem_rw_with_rand_reset.2940216521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2782168064 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 625376479 ps |
| CPU time | 2.16 seconds |
| Started | Sep 04 08:38:03 AM UTC 24 |
| Finished | Sep 04 08:38:06 AM UTC 24 |
| Peak memory | 252816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782168064 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.2782168064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.2691548344 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 91627469 ps |
| CPU time | 1.81 seconds |
| Started | Sep 04 08:38:03 AM UTC 24 |
| Finished | Sep 04 08:38:06 AM UTC 24 |
| Peak memory | 241076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691548344 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.2691548344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.2895886538 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 72995082 ps |
| CPU time | 3.04 seconds |
| Started | Sep 04 08:38:03 AM UTC 24 |
| Finished | Sep 04 08:38:07 AM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895886538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.2895886538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.4045307886 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 346611181 ps |
| CPU time | 7.18 seconds |
| Started | Sep 04 08:38:00 AM UTC 24 |
| Finished | Sep 04 08:38:09 AM UTC 24 |
| Peak memory | 258960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045307886 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.4045307886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1198091108 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 20003803126 ps |
| CPU time | 45.71 seconds |
| Started | Sep 04 08:38:01 AM UTC 24 |
| Finished | Sep 04 08:38:49 AM UTC 24 |
| Peak memory | 258964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198091108 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.1198091108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.322402656 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 87720310 ps |
| CPU time | 3.42 seconds |
| Started | Sep 04 08:38:06 AM UTC 24 |
| Finished | Sep 04 08:38:11 AM UTC 24 |
| Peak memory | 259092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=322402656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr _mem_rw_with_rand_reset.322402656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3657538923 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 53873926 ps |
| CPU time | 2.07 seconds |
| Started | Sep 04 08:38:06 AM UTC 24 |
| Finished | Sep 04 08:38:09 AM UTC 24 |
| Peak memory | 254788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657538923 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.3657538923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.151866845 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 59804623 ps |
| CPU time | 2.16 seconds |
| Started | Sep 04 08:38:05 AM UTC 24 |
| Finished | Sep 04 08:38:08 AM UTC 24 |
| Peak memory | 241964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151866845 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.151866845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1506991066 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 131894943 ps |
| CPU time | 5.29 seconds |
| Started | Sep 04 08:38:06 AM UTC 24 |
| Finished | Sep 04 08:38:13 AM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506991066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.1506991066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2818256769 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 373090017 ps |
| CPU time | 6.91 seconds |
| Started | Sep 04 08:38:04 AM UTC 24 |
| Finished | Sep 04 08:38:12 AM UTC 24 |
| Peak memory | 258948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818256769 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.2818256769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3261178555 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 4971419589 ps |
| CPU time | 23.26 seconds |
| Started | Sep 04 08:38:04 AM UTC 24 |
| Finished | Sep 04 08:38:28 AM UTC 24 |
| Peak memory | 256988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261178555 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.3261178555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3806854540 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 135447830 ps |
| CPU time | 4 seconds |
| Started | Sep 04 08:38:07 AM UTC 24 |
| Finished | Sep 04 08:38:13 AM UTC 24 |
| Peak memory | 259072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3806854540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_cs r_mem_rw_with_rand_reset.3806854540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.44843894 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 177442618 ps |
| CPU time | 2.93 seconds |
| Started | Sep 04 08:38:07 AM UTC 24 |
| Finished | Sep 04 08:38:12 AM UTC 24 |
| Peak memory | 254796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44843894 -assert nopostproc +UVM_TESTNAME=otp_c trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.44843894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.1400234105 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 150187496 ps |
| CPU time | 2.44 seconds |
| Started | Sep 04 08:38:06 AM UTC 24 |
| Finished | Sep 04 08:38:10 AM UTC 24 |
| Peak memory | 242552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400234105 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.1400234105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.1847846988 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 134432600 ps |
| CPU time | 3.47 seconds |
| Started | Sep 04 08:38:07 AM UTC 24 |
| Finished | Sep 04 08:38:12 AM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847846988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.1847846988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3819183987 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 4584538311 ps |
| CPU time | 17.59 seconds |
| Started | Sep 04 08:38:06 AM UTC 24 |
| Finished | Sep 04 08:38:25 AM UTC 24 |
| Peak memory | 256884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819183987 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.3819183987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1159846842 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 179213397 ps |
| CPU time | 2.75 seconds |
| Started | Sep 04 08:38:09 AM UTC 24 |
| Finished | Sep 04 08:38:13 AM UTC 24 |
| Peak memory | 254680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159846842 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1159846842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.1286507545 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 155559836 ps |
| CPU time | 2.62 seconds |
| Started | Sep 04 08:38:09 AM UTC 24 |
| Finished | Sep 04 08:38:13 AM UTC 24 |
| Peak memory | 241748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286507545 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.1286507545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.4029576229 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 376858788 ps |
| CPU time | 3.66 seconds |
| Started | Sep 04 08:38:10 AM UTC 24 |
| Finished | Sep 04 08:38:15 AM UTC 24 |
| Peak memory | 254728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029576229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.4029576229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.454676994 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 362327538 ps |
| CPU time | 6.89 seconds |
| Started | Sep 04 08:38:07 AM UTC 24 |
| Finished | Sep 04 08:38:16 AM UTC 24 |
| Peak memory | 258908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454676994 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.454676994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.300910376 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2602498770 ps |
| CPU time | 23.52 seconds |
| Started | Sep 04 08:38:09 AM UTC 24 |
| Finished | Sep 04 08:38:34 AM UTC 24 |
| Peak memory | 256860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300910376 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.300910376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.3263328003 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 349603379 ps |
| CPU time | 15.2 seconds |
| Started | Sep 04 08:39:03 AM UTC 24 |
| Finished | Sep 04 08:39:20 AM UTC 24 |
| Peak memory | 257604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263328003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.3263328003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.2595432250 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5923428747 ps |
| CPU time | 13.41 seconds |
| Started | Sep 04 08:38:59 AM UTC 24 |
| Finished | Sep 04 08:39:14 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595432250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.2595432250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.211219869 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 807759904 ps |
| CPU time | 15.63 seconds |
| Started | Sep 04 08:39:06 AM UTC 24 |
| Finished | Sep 04 08:39:22 AM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211219869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.211219869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.4167123771 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 168011187 ps |
| CPU time | 3.27 seconds |
| Started | Sep 04 08:39:03 AM UTC 24 |
| Finished | Sep 04 08:39:08 AM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167123771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.4167123771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.3874207494 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 704517286 ps |
| CPU time | 20.91 seconds |
| Started | Sep 04 08:39:01 AM UTC 24 |
| Finished | Sep 04 08:39:23 AM UTC 24 |
| Peak memory | 257364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874207494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.3874207494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.1989996372 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1603104542 ps |
| CPU time | 19.42 seconds |
| Started | Sep 04 08:38:58 AM UTC 24 |
| Finished | Sep 04 08:39:19 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989996372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.1989996372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.1443326779 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 110138089 ps |
| CPU time | 4.27 seconds |
| Started | Sep 04 08:39:07 AM UTC 24 |
| Finished | Sep 04 08:39:12 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443326779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.1443326779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.1223782914 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 37540829670 ps |
| CPU time | 185.99 seconds |
| Started | Sep 04 08:39:08 AM UTC 24 |
| Finished | Sep 04 08:42:17 AM UTC 24 |
| Peak memory | 289772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223782914 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.1223782914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.558967911 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1697068975 ps |
| CPU time | 54.59 seconds |
| Started | Sep 04 08:39:07 AM UTC 24 |
| Finished | Sep 04 08:40:03 AM UTC 24 |
| Peak memory | 267768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=558967911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.558967911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.2505847 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 227181165 ps |
| CPU time | 3.22 seconds |
| Started | Sep 04 08:39:10 AM UTC 24 |
| Finished | Sep 04 08:39:14 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505847 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.2505847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.3080362778 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1743357134 ps |
| CPU time | 17.63 seconds |
| Started | Sep 04 08:39:08 AM UTC 24 |
| Finished | Sep 04 08:39:27 AM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080362778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.3080362778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.534467527 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 2093191830 ps |
| CPU time | 17.3 seconds |
| Started | Sep 04 08:39:08 AM UTC 24 |
| Finished | Sep 04 08:39:27 AM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534467527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.534467527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.3603239003 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 202732706 ps |
| CPU time | 2.89 seconds |
| Started | Sep 04 08:39:08 AM UTC 24 |
| Finished | Sep 04 08:39:12 AM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603239003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.3603239003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.1531157703 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 969904182 ps |
| CPU time | 10.74 seconds |
| Started | Sep 04 08:39:09 AM UTC 24 |
| Finished | Sep 04 08:39:21 AM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531157703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.1531157703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.2376648135 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 41728616835 ps |
| CPU time | 199.08 seconds |
| Started | Sep 04 08:39:10 AM UTC 24 |
| Finished | Sep 04 08:42:32 AM UTC 24 |
| Peak memory | 296132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376648135 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.2376648135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.3131650380 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 225811084 ps |
| CPU time | 4.79 seconds |
| Started | Sep 04 08:39:08 AM UTC 24 |
| Finished | Sep 04 08:39:14 AM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131650380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3131650380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.1815157539 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 636609916 ps |
| CPU time | 14.31 seconds |
| Started | Sep 04 08:39:09 AM UTC 24 |
| Finished | Sep 04 08:39:25 AM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815157539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.1815157539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.3046244250 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 109626174 ps |
| CPU time | 2.71 seconds |
| Started | Sep 04 08:40:50 AM UTC 24 |
| Finished | Sep 04 08:40:54 AM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046244250 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.3046244250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.549168262 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1318574626 ps |
| CPU time | 21 seconds |
| Started | Sep 04 08:40:45 AM UTC 24 |
| Finished | Sep 04 08:41:07 AM UTC 24 |
| Peak memory | 253624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549168262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.549168262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.792026234 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 10704090852 ps |
| CPU time | 17.79 seconds |
| Started | Sep 04 08:40:45 AM UTC 24 |
| Finished | Sep 04 08:41:04 AM UTC 24 |
| Peak memory | 251576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792026234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.792026234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.865139694 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1085773930 ps |
| CPU time | 23.14 seconds |
| Started | Sep 04 08:40:45 AM UTC 24 |
| Finished | Sep 04 08:41:09 AM UTC 24 |
| Peak memory | 251580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865139694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.865139694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.1563256567 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 955379455 ps |
| CPU time | 8.58 seconds |
| Started | Sep 04 08:40:45 AM UTC 24 |
| Finished | Sep 04 08:40:55 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563256567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.1563256567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.3633215820 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 872830185 ps |
| CPU time | 21.07 seconds |
| Started | Sep 04 08:40:48 AM UTC 24 |
| Finished | Sep 04 08:41:10 AM UTC 24 |
| Peak memory | 253344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633215820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.3633215820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.1004149187 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 308174764 ps |
| CPU time | 5.93 seconds |
| Started | Sep 04 08:40:43 AM UTC 24 |
| Finished | Sep 04 08:40:50 AM UTC 24 |
| Peak memory | 257564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004149187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.1004149187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.1488743786 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 3044286208 ps |
| CPU time | 30.04 seconds |
| Started | Sep 04 08:40:43 AM UTC 24 |
| Finished | Sep 04 08:41:14 AM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488743786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.1488743786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.1798824432 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 370630034 ps |
| CPU time | 7.2 seconds |
| Started | Sep 04 08:40:48 AM UTC 24 |
| Finished | Sep 04 08:40:56 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798824432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.1798824432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.3906918378 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1659999812 ps |
| CPU time | 7.33 seconds |
| Started | Sep 04 08:40:40 AM UTC 24 |
| Finished | Sep 04 08:40:48 AM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906918378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.3906918378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.3320036917 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 8186725797 ps |
| CPU time | 46.78 seconds |
| Started | Sep 04 08:40:48 AM UTC 24 |
| Finished | Sep 04 08:41:36 AM UTC 24 |
| Peak memory | 253632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320036917 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.3320036917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.1383316537 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 9500863703 ps |
| CPU time | 28.6 seconds |
| Started | Sep 04 08:40:48 AM UTC 24 |
| Finished | Sep 04 08:41:18 AM UTC 24 |
| Peak memory | 253400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383316537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.1383316537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.1035202226 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 117383655 ps |
| CPU time | 4.59 seconds |
| Started | Sep 04 08:47:47 AM UTC 24 |
| Finished | Sep 04 08:47:53 AM UTC 24 |
| Peak memory | 251052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035202226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.1035202226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.4092800229 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 335438298 ps |
| CPU time | 9.57 seconds |
| Started | Sep 04 08:47:47 AM UTC 24 |
| Finished | Sep 04 08:47:58 AM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092800229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.4092800229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.1175727834 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 157216152 ps |
| CPU time | 5.16 seconds |
| Started | Sep 04 08:47:47 AM UTC 24 |
| Finished | Sep 04 08:47:54 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175727834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.1175727834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.504202326 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 90397035 ps |
| CPU time | 2.58 seconds |
| Started | Sep 04 08:47:47 AM UTC 24 |
| Finished | Sep 04 08:47:51 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504202326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.504202326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.2676330181 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 106992887 ps |
| CPU time | 4.61 seconds |
| Started | Sep 04 08:47:47 AM UTC 24 |
| Finished | Sep 04 08:47:53 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676330181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.2676330181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.2866599459 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 1186588061 ps |
| CPU time | 3.94 seconds |
| Started | Sep 04 08:47:48 AM UTC 24 |
| Finished | Sep 04 08:47:52 AM UTC 24 |
| Peak memory | 251124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866599459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.2866599459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.1891988283 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 80666986 ps |
| CPU time | 2.89 seconds |
| Started | Sep 04 08:47:48 AM UTC 24 |
| Finished | Sep 04 08:47:51 AM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891988283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.1891988283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.3696165291 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 700939058 ps |
| CPU time | 21.21 seconds |
| Started | Sep 04 08:47:48 AM UTC 24 |
| Finished | Sep 04 08:48:10 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696165291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.3696165291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.263131391 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 308448229 ps |
| CPU time | 5.16 seconds |
| Started | Sep 04 08:47:48 AM UTC 24 |
| Finished | Sep 04 08:47:54 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263131391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.263131391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.4107093269 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 211317400 ps |
| CPU time | 8.68 seconds |
| Started | Sep 04 08:47:54 AM UTC 24 |
| Finished | Sep 04 08:48:04 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107093269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.4107093269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.2347455931 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 223888551 ps |
| CPU time | 5.73 seconds |
| Started | Sep 04 08:47:54 AM UTC 24 |
| Finished | Sep 04 08:48:01 AM UTC 24 |
| Peak memory | 250748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347455931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.2347455931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.741185476 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 498342937 ps |
| CPU time | 5.51 seconds |
| Started | Sep 04 08:47:54 AM UTC 24 |
| Finished | Sep 04 08:48:01 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741185476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.741185476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.3927597408 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 184420989 ps |
| CPU time | 4.87 seconds |
| Started | Sep 04 08:47:54 AM UTC 24 |
| Finished | Sep 04 08:48:00 AM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927597408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.3927597408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.635104559 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 19502538695 ps |
| CPU time | 46.35 seconds |
| Started | Sep 04 08:47:54 AM UTC 24 |
| Finished | Sep 04 08:48:42 AM UTC 24 |
| Peak memory | 253300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635104559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.635104559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.3038182994 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 147792349 ps |
| CPU time | 5.2 seconds |
| Started | Sep 04 08:47:54 AM UTC 24 |
| Finished | Sep 04 08:48:01 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038182994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.3038182994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.491018053 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 2524414305 ps |
| CPU time | 6.89 seconds |
| Started | Sep 04 08:47:54 AM UTC 24 |
| Finished | Sep 04 08:48:02 AM UTC 24 |
| Peak memory | 251580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491018053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.491018053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.3444665304 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 339312478 ps |
| CPU time | 6.41 seconds |
| Started | Sep 04 08:47:54 AM UTC 24 |
| Finished | Sep 04 08:48:02 AM UTC 24 |
| Peak memory | 250036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444665304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3444665304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.2277056803 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 314470418 ps |
| CPU time | 5.52 seconds |
| Started | Sep 04 08:47:55 AM UTC 24 |
| Finished | Sep 04 08:48:01 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277056803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.2277056803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.828922748 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 109617746 ps |
| CPU time | 2.77 seconds |
| Started | Sep 04 08:40:56 AM UTC 24 |
| Finished | Sep 04 08:41:00 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828922748 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.828922748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.3512428133 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 4585996410 ps |
| CPU time | 14.84 seconds |
| Started | Sep 04 08:40:52 AM UTC 24 |
| Finished | Sep 04 08:41:09 AM UTC 24 |
| Peak memory | 253496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512428133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.3512428133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.1678627025 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1088514825 ps |
| CPU time | 15.26 seconds |
| Started | Sep 04 08:40:52 AM UTC 24 |
| Finished | Sep 04 08:41:09 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678627025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.1678627025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.1225092621 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 1263871815 ps |
| CPU time | 28.23 seconds |
| Started | Sep 04 08:40:52 AM UTC 24 |
| Finished | Sep 04 08:41:23 AM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225092621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.1225092621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.778594067 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2716281763 ps |
| CPU time | 20.78 seconds |
| Started | Sep 04 08:40:52 AM UTC 24 |
| Finished | Sep 04 08:41:15 AM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778594067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.778594067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.3014314437 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 686056388 ps |
| CPU time | 19.05 seconds |
| Started | Sep 04 08:40:50 AM UTC 24 |
| Finished | Sep 04 08:41:10 AM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014314437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.3014314437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.2934669070 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 283249457 ps |
| CPU time | 11.37 seconds |
| Started | Sep 04 08:40:54 AM UTC 24 |
| Finished | Sep 04 08:41:07 AM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934669070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.2934669070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.3241353970 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 379052626 ps |
| CPU time | 12.83 seconds |
| Started | Sep 04 08:40:50 AM UTC 24 |
| Finished | Sep 04 08:41:04 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241353970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.3241353970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.2759967672 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 4772209967 ps |
| CPU time | 43.38 seconds |
| Started | Sep 04 08:40:56 AM UTC 24 |
| Finished | Sep 04 08:41:41 AM UTC 24 |
| Peak memory | 255420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759967672 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.2759967672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.4231538178 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 9771629728 ps |
| CPU time | 80.88 seconds |
| Started | Sep 04 08:40:56 AM UTC 24 |
| Finished | Sep 04 08:42:19 AM UTC 24 |
| Peak memory | 261804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4231538178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.otp_ctrl_stress_all_with_rand_reset.4231538178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.3072071420 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1209364623 ps |
| CPU time | 26.96 seconds |
| Started | Sep 04 08:40:56 AM UTC 24 |
| Finished | Sep 04 08:41:24 AM UTC 24 |
| Peak memory | 253336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072071420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.3072071420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.4031578065 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 176580407 ps |
| CPU time | 5.57 seconds |
| Started | Sep 04 08:47:55 AM UTC 24 |
| Finished | Sep 04 08:48:01 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031578065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.4031578065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.2952458782 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 89713396 ps |
| CPU time | 5.74 seconds |
| Started | Sep 04 08:47:55 AM UTC 24 |
| Finished | Sep 04 08:48:01 AM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952458782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.2952458782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.165658932 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 491837107 ps |
| CPU time | 6.3 seconds |
| Started | Sep 04 08:47:57 AM UTC 24 |
| Finished | Sep 04 08:48:04 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165658932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.165658932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.97348616 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 3274902210 ps |
| CPU time | 20.94 seconds |
| Started | Sep 04 08:47:57 AM UTC 24 |
| Finished | Sep 04 08:48:19 AM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97348616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.97348616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.543513824 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 2120241231 ps |
| CPU time | 5.21 seconds |
| Started | Sep 04 08:47:57 AM UTC 24 |
| Finished | Sep 04 08:48:03 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543513824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.543513824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.3950957695 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 95629734 ps |
| CPU time | 5.54 seconds |
| Started | Sep 04 08:47:57 AM UTC 24 |
| Finished | Sep 04 08:48:03 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950957695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.3950957695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.1021655927 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 119938753 ps |
| CPU time | 3.78 seconds |
| Started | Sep 04 08:47:57 AM UTC 24 |
| Finished | Sep 04 08:48:02 AM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021655927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.1021655927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.2283728799 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 1153987804 ps |
| CPU time | 8.78 seconds |
| Started | Sep 04 08:47:59 AM UTC 24 |
| Finished | Sep 04 08:48:09 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283728799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.2283728799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.4113478303 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 129726987 ps |
| CPU time | 3.24 seconds |
| Started | Sep 04 08:48:04 AM UTC 24 |
| Finished | Sep 04 08:48:08 AM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113478303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.4113478303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.2313606712 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 131371976 ps |
| CPU time | 3.2 seconds |
| Started | Sep 04 08:48:04 AM UTC 24 |
| Finished | Sep 04 08:48:08 AM UTC 24 |
| Peak memory | 250912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313606712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.2313606712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.3044809063 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 375629224 ps |
| CPU time | 3.98 seconds |
| Started | Sep 04 08:48:04 AM UTC 24 |
| Finished | Sep 04 08:48:09 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044809063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.3044809063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.739838911 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 7675498127 ps |
| CPU time | 13.31 seconds |
| Started | Sep 04 08:48:04 AM UTC 24 |
| Finished | Sep 04 08:48:19 AM UTC 24 |
| Peak memory | 257392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739838911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.739838911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.1829965587 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 1975165379 ps |
| CPU time | 4.83 seconds |
| Started | Sep 04 08:48:04 AM UTC 24 |
| Finished | Sep 04 08:48:10 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829965587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.1829965587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.239242970 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 79248936 ps |
| CPU time | 3.5 seconds |
| Started | Sep 04 08:48:04 AM UTC 24 |
| Finished | Sep 04 08:48:09 AM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239242970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.239242970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.1646763696 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 137087012 ps |
| CPU time | 3.69 seconds |
| Started | Sep 04 08:48:04 AM UTC 24 |
| Finished | Sep 04 08:48:09 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646763696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.1646763696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.1036136008 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 528372563 ps |
| CPU time | 5.83 seconds |
| Started | Sep 04 08:48:04 AM UTC 24 |
| Finished | Sep 04 08:48:11 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036136008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.1036136008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.3394017443 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 207225236 ps |
| CPU time | 4.97 seconds |
| Started | Sep 04 08:48:04 AM UTC 24 |
| Finished | Sep 04 08:48:10 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394017443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.3394017443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.3624027531 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 271473178 ps |
| CPU time | 7.45 seconds |
| Started | Sep 04 08:48:04 AM UTC 24 |
| Finished | Sep 04 08:48:13 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624027531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.3624027531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.1455060988 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 107002554 ps |
| CPU time | 4.17 seconds |
| Started | Sep 04 08:48:04 AM UTC 24 |
| Finished | Sep 04 08:48:10 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455060988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.1455060988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.1937374741 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 773096252 ps |
| CPU time | 9.33 seconds |
| Started | Sep 04 08:48:04 AM UTC 24 |
| Finished | Sep 04 08:48:15 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937374741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.1937374741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.2051771287 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 82162204 ps |
| CPU time | 1.87 seconds |
| Started | Sep 04 08:41:09 AM UTC 24 |
| Finished | Sep 04 08:41:12 AM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051771287 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.2051771287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.3710517836 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2293137007 ps |
| CPU time | 12.95 seconds |
| Started | Sep 04 08:41:06 AM UTC 24 |
| Finished | Sep 04 08:41:20 AM UTC 24 |
| Peak memory | 253688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710517836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.3710517836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.3657990395 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1233417956 ps |
| CPU time | 18.38 seconds |
| Started | Sep 04 08:41:06 AM UTC 24 |
| Finished | Sep 04 08:41:26 AM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657990395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.3657990395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.241230651 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1455340079 ps |
| CPU time | 33.42 seconds |
| Started | Sep 04 08:41:04 AM UTC 24 |
| Finished | Sep 04 08:41:39 AM UTC 24 |
| Peak memory | 253604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241230651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.241230651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.994405631 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1546539344 ps |
| CPU time | 20.94 seconds |
| Started | Sep 04 08:41:06 AM UTC 24 |
| Finished | Sep 04 08:41:28 AM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994405631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.994405631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.726452613 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2508155138 ps |
| CPU time | 7.72 seconds |
| Started | Sep 04 08:41:06 AM UTC 24 |
| Finished | Sep 04 08:41:15 AM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726452613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.726452613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.2929336196 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 147420316 ps |
| CPU time | 6.04 seconds |
| Started | Sep 04 08:41:00 AM UTC 24 |
| Finished | Sep 04 08:41:08 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929336196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.2929336196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.2163327136 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2153812323 ps |
| CPU time | 8.26 seconds |
| Started | Sep 04 08:40:59 AM UTC 24 |
| Finished | Sep 04 08:41:09 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163327136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.2163327136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.1748250690 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 133548047 ps |
| CPU time | 5.5 seconds |
| Started | Sep 04 08:41:09 AM UTC 24 |
| Finished | Sep 04 08:41:15 AM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748250690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1748250690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.526779797 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 188954066 ps |
| CPU time | 8.42 seconds |
| Started | Sep 04 08:40:57 AM UTC 24 |
| Finished | Sep 04 08:41:07 AM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526779797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.526779797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.1167947353 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 92454695705 ps |
| CPU time | 302.35 seconds |
| Started | Sep 04 08:41:09 AM UTC 24 |
| Finished | Sep 04 08:46:16 AM UTC 24 |
| Peak memory | 288604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167947353 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.1167947353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.3453377221 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 106868783 ps |
| CPU time | 4.13 seconds |
| Started | Sep 04 08:48:04 AM UTC 24 |
| Finished | Sep 04 08:48:10 AM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453377221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.3453377221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.1228290297 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 475130991 ps |
| CPU time | 9.07 seconds |
| Started | Sep 04 08:48:05 AM UTC 24 |
| Finished | Sep 04 08:48:15 AM UTC 24 |
| Peak memory | 251392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228290297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.1228290297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.3801949261 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 2594069846 ps |
| CPU time | 6.12 seconds |
| Started | Sep 04 08:48:05 AM UTC 24 |
| Finished | Sep 04 08:48:12 AM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801949261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.3801949261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.1504373343 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 165264497 ps |
| CPU time | 3.8 seconds |
| Started | Sep 04 08:48:11 AM UTC 24 |
| Finished | Sep 04 08:48:16 AM UTC 24 |
| Peak memory | 253236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504373343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.1504373343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.1935926833 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 196721253 ps |
| CPU time | 4.59 seconds |
| Started | Sep 04 08:48:11 AM UTC 24 |
| Finished | Sep 04 08:48:17 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935926833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.1935926833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.4163177989 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 5863488094 ps |
| CPU time | 13.5 seconds |
| Started | Sep 04 08:48:12 AM UTC 24 |
| Finished | Sep 04 08:48:26 AM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163177989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.4163177989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.3545666737 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 156898841 ps |
| CPU time | 3.83 seconds |
| Started | Sep 04 08:48:12 AM UTC 24 |
| Finished | Sep 04 08:48:16 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545666737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.3545666737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.3969742703 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 8518282279 ps |
| CPU time | 15.94 seconds |
| Started | Sep 04 08:48:12 AM UTC 24 |
| Finished | Sep 04 08:48:29 AM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969742703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.3969742703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.3533167050 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 144489988 ps |
| CPU time | 3.33 seconds |
| Started | Sep 04 08:48:12 AM UTC 24 |
| Finished | Sep 04 08:48:16 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533167050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.3533167050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.2156430328 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 932812759 ps |
| CPU time | 6.19 seconds |
| Started | Sep 04 08:48:12 AM UTC 24 |
| Finished | Sep 04 08:48:19 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156430328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.2156430328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.594355195 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 781000319 ps |
| CPU time | 8.82 seconds |
| Started | Sep 04 08:48:12 AM UTC 24 |
| Finished | Sep 04 08:48:22 AM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594355195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.594355195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.2929607298 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 136376292 ps |
| CPU time | 3.31 seconds |
| Started | Sep 04 08:48:12 AM UTC 24 |
| Finished | Sep 04 08:48:16 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929607298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.2929607298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.2652723257 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 188435082 ps |
| CPU time | 4.35 seconds |
| Started | Sep 04 08:48:12 AM UTC 24 |
| Finished | Sep 04 08:48:17 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652723257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.2652723257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.2071652886 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 2082719410 ps |
| CPU time | 7.28 seconds |
| Started | Sep 04 08:48:12 AM UTC 24 |
| Finished | Sep 04 08:48:20 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071652886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.2071652886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.2891072353 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 755748403 ps |
| CPU time | 9.38 seconds |
| Started | Sep 04 08:48:12 AM UTC 24 |
| Finished | Sep 04 08:48:22 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891072353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.2891072353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.701134006 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 259930877 ps |
| CPU time | 4.15 seconds |
| Started | Sep 04 08:48:12 AM UTC 24 |
| Finished | Sep 04 08:48:17 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701134006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.701134006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.828622692 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 305352815 ps |
| CPU time | 4.38 seconds |
| Started | Sep 04 08:48:12 AM UTC 24 |
| Finished | Sep 04 08:48:18 AM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828622692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.828622692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.2639299708 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 589575113 ps |
| CPU time | 6.49 seconds |
| Started | Sep 04 08:48:12 AM UTC 24 |
| Finished | Sep 04 08:48:20 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639299708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.2639299708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.2403303833 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 210607994 ps |
| CPU time | 3.27 seconds |
| Started | Sep 04 08:41:18 AM UTC 24 |
| Finished | Sep 04 08:41:22 AM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403303833 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.2403303833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.3376071608 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 859847297 ps |
| CPU time | 31.65 seconds |
| Started | Sep 04 08:41:12 AM UTC 24 |
| Finished | Sep 04 08:41:46 AM UTC 24 |
| Peak memory | 253284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376071608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.3376071608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.687361166 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2107536947 ps |
| CPU time | 11.19 seconds |
| Started | Sep 04 08:41:12 AM UTC 24 |
| Finished | Sep 04 08:41:25 AM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687361166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.687361166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.2145008029 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 482996609 ps |
| CPU time | 5.85 seconds |
| Started | Sep 04 08:41:12 AM UTC 24 |
| Finished | Sep 04 08:41:19 AM UTC 24 |
| Peak memory | 251524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145008029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.2145008029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.2373535329 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1235493982 ps |
| CPU time | 14.93 seconds |
| Started | Sep 04 08:41:12 AM UTC 24 |
| Finished | Sep 04 08:41:29 AM UTC 24 |
| Peak memory | 253344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373535329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.2373535329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.1066164576 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 17619088062 ps |
| CPU time | 37.98 seconds |
| Started | Sep 04 08:41:14 AM UTC 24 |
| Finished | Sep 04 08:41:53 AM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066164576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.1066164576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.2550310349 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2225293599 ps |
| CPU time | 18.2 seconds |
| Started | Sep 04 08:41:12 AM UTC 24 |
| Finished | Sep 04 08:41:32 AM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550310349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.2550310349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.1398408429 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 222608948 ps |
| CPU time | 7.32 seconds |
| Started | Sep 04 08:41:12 AM UTC 24 |
| Finished | Sep 04 08:41:21 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398408429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.1398408429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.665186835 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 4660956186 ps |
| CPU time | 13.83 seconds |
| Started | Sep 04 08:41:17 AM UTC 24 |
| Finished | Sep 04 08:41:32 AM UTC 24 |
| Peak memory | 253392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665186835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.665186835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.2830729408 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1424882822 ps |
| CPU time | 10.99 seconds |
| Started | Sep 04 08:41:09 AM UTC 24 |
| Finished | Sep 04 08:41:21 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830729408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.2830729408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.3227263753 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 7247288310 ps |
| CPU time | 53.36 seconds |
| Started | Sep 04 08:41:17 AM UTC 24 |
| Finished | Sep 04 08:42:12 AM UTC 24 |
| Peak memory | 257532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3227263753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.otp_ctrl_stress_all_with_rand_reset.3227263753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.2048825635 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1628314339 ps |
| CPU time | 15.38 seconds |
| Started | Sep 04 08:41:17 AM UTC 24 |
| Finished | Sep 04 08:41:33 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048825635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.2048825635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.2339999842 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 126417589 ps |
| CPU time | 3.71 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:24 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339999842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.2339999842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.2091074161 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 879282387 ps |
| CPU time | 10.34 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:31 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091074161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.2091074161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.4241044186 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1865120232 ps |
| CPU time | 3.72 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:24 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241044186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.4241044186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.3386720403 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 297678460 ps |
| CPU time | 4.92 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:26 AM UTC 24 |
| Peak memory | 257248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386720403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.3386720403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.4126184171 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 123313085 ps |
| CPU time | 4.45 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:25 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126184171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.4126184171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.885200752 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 369549047 ps |
| CPU time | 9.24 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:30 AM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885200752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.885200752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.454408372 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1865828641 ps |
| CPU time | 5.3 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:26 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454408372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.454408372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.3311377600 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 1104315793 ps |
| CPU time | 4.4 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:25 AM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311377600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.3311377600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.742844149 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 1980640303 ps |
| CPU time | 4.88 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:26 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742844149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.742844149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.4046855120 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 433723110 ps |
| CPU time | 5.72 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:27 AM UTC 24 |
| Peak memory | 251092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046855120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.4046855120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.788483911 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 167789748 ps |
| CPU time | 4.75 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:26 AM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788483911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.788483911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.2481209253 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 4425491584 ps |
| CPU time | 9.38 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:30 AM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481209253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.2481209253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.2242804815 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 400310806 ps |
| CPU time | 4.47 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:26 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242804815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.2242804815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.1713673942 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 273059794 ps |
| CPU time | 13.81 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:35 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713673942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1713673942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.635786921 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 101276136 ps |
| CPU time | 3.51 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:25 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635786921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.635786921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.3757532776 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 806480854 ps |
| CPU time | 6.17 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:27 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757532776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.3757532776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.2648189975 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 229150681 ps |
| CPU time | 3.92 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:25 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648189975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.2648189975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.270826380 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 1576009690 ps |
| CPU time | 6.22 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:28 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270826380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.270826380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.2770725536 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 737028390 ps |
| CPU time | 4.65 seconds |
| Started | Sep 04 08:48:20 AM UTC 24 |
| Finished | Sep 04 08:48:26 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770725536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2770725536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.2124583625 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 214608793 ps |
| CPU time | 4.68 seconds |
| Started | Sep 04 08:48:24 AM UTC 24 |
| Finished | Sep 04 08:48:30 AM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124583625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.2124583625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.2355285234 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 49613331 ps |
| CPU time | 2.32 seconds |
| Started | Sep 04 08:41:27 AM UTC 24 |
| Finished | Sep 04 08:41:31 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355285234 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.2355285234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.2721230285 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1506955618 ps |
| CPU time | 12.86 seconds |
| Started | Sep 04 08:41:24 AM UTC 24 |
| Finished | Sep 04 08:41:38 AM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721230285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.2721230285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.59558103 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 780113508 ps |
| CPU time | 19.12 seconds |
| Started | Sep 04 08:41:24 AM UTC 24 |
| Finished | Sep 04 08:41:45 AM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59558103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.59558103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.465220741 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 6240753364 ps |
| CPU time | 15.38 seconds |
| Started | Sep 04 08:41:24 AM UTC 24 |
| Finished | Sep 04 08:41:41 AM UTC 24 |
| Peak memory | 253468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465220741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.465220741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.4119325344 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 920789402 ps |
| CPU time | 28.51 seconds |
| Started | Sep 04 08:41:24 AM UTC 24 |
| Finished | Sep 04 08:41:54 AM UTC 24 |
| Peak memory | 255480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119325344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.4119325344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.2768550479 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 533172038 ps |
| CPU time | 9.08 seconds |
| Started | Sep 04 08:41:21 AM UTC 24 |
| Finished | Sep 04 08:41:31 AM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768550479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.2768550479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.4243983555 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 218528010 ps |
| CPU time | 8.36 seconds |
| Started | Sep 04 08:41:21 AM UTC 24 |
| Finished | Sep 04 08:41:30 AM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243983555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.4243983555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.656546839 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 158906569 ps |
| CPU time | 7.8 seconds |
| Started | Sep 04 08:41:24 AM UTC 24 |
| Finished | Sep 04 08:41:33 AM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656546839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.656546839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.2813718170 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 4013426066 ps |
| CPU time | 7.63 seconds |
| Started | Sep 04 08:41:18 AM UTC 24 |
| Finished | Sep 04 08:41:27 AM UTC 24 |
| Peak memory | 253532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813718170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.2813718170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.2995167673 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 15851381759 ps |
| CPU time | 99.99 seconds |
| Started | Sep 04 08:41:27 AM UTC 24 |
| Finished | Sep 04 08:43:09 AM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995167673 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.2995167673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.1602640253 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 3861752873 ps |
| CPU time | 23.75 seconds |
| Started | Sep 04 08:41:27 AM UTC 24 |
| Finished | Sep 04 08:41:52 AM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602640253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.1602640253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.3172991111 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 2561723174 ps |
| CPU time | 4.17 seconds |
| Started | Sep 04 08:48:25 AM UTC 24 |
| Finished | Sep 04 08:48:30 AM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172991111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.3172991111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.1739765678 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 154759881 ps |
| CPU time | 2.91 seconds |
| Started | Sep 04 08:48:25 AM UTC 24 |
| Finished | Sep 04 08:48:29 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739765678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.1739765678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.3591981369 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 166795423 ps |
| CPU time | 2.97 seconds |
| Started | Sep 04 08:48:25 AM UTC 24 |
| Finished | Sep 04 08:48:29 AM UTC 24 |
| Peak memory | 251104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591981369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.3591981369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.3833039309 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 438898030 ps |
| CPU time | 4.15 seconds |
| Started | Sep 04 08:48:25 AM UTC 24 |
| Finished | Sep 04 08:48:30 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833039309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3833039309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.4048876585 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 372465717 ps |
| CPU time | 7.66 seconds |
| Started | Sep 04 08:48:25 AM UTC 24 |
| Finished | Sep 04 08:48:33 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048876585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.4048876585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.3145610515 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 162949992 ps |
| CPU time | 3.15 seconds |
| Started | Sep 04 08:48:25 AM UTC 24 |
| Finished | Sep 04 08:48:29 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145610515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3145610515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.460930143 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 222684168 ps |
| CPU time | 10.48 seconds |
| Started | Sep 04 08:48:25 AM UTC 24 |
| Finished | Sep 04 08:48:36 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460930143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.460930143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.2258683490 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 415252551 ps |
| CPU time | 3.46 seconds |
| Started | Sep 04 08:48:25 AM UTC 24 |
| Finished | Sep 04 08:48:29 AM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258683490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.2258683490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.3262141277 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 304231631 ps |
| CPU time | 7.79 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:40 AM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262141277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.3262141277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.3899215108 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 171043519 ps |
| CPU time | 3.71 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:36 AM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899215108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.3899215108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.1347259623 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 5189889166 ps |
| CPU time | 20.08 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:52 AM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347259623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.1347259623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.2152076368 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 198159400 ps |
| CPU time | 3.31 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:36 AM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152076368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.2152076368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.2669035613 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 2700133480 ps |
| CPU time | 7.68 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:40 AM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669035613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.2669035613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.2055658280 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 2902288620 ps |
| CPU time | 5.27 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:37 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055658280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.2055658280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.4273176594 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 2226820020 ps |
| CPU time | 21.39 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:54 AM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273176594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.4273176594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.3454012588 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 156364599 ps |
| CPU time | 3.71 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:36 AM UTC 24 |
| Peak memory | 253264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454012588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.3454012588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.1236475797 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 1039736510 ps |
| CPU time | 12.84 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:45 AM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236475797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.1236475797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.965408176 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 111248575 ps |
| CPU time | 4.08 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:36 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965408176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.965408176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.3315726540 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 164276315 ps |
| CPU time | 6.78 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:39 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315726540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.3315726540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.3213202543 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 151020046 ps |
| CPU time | 3.05 seconds |
| Started | Sep 04 08:41:37 AM UTC 24 |
| Finished | Sep 04 08:41:41 AM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213202543 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.3213202543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.2337278711 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 717054695 ps |
| CPU time | 11.49 seconds |
| Started | Sep 04 08:41:32 AM UTC 24 |
| Finished | Sep 04 08:41:44 AM UTC 24 |
| Peak memory | 257464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337278711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.2337278711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.30048169 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 395509452 ps |
| CPU time | 10.81 seconds |
| Started | Sep 04 08:41:32 AM UTC 24 |
| Finished | Sep 04 08:41:44 AM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30048169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.30048169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.255930451 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 113953546 ps |
| CPU time | 4.72 seconds |
| Started | Sep 04 08:41:27 AM UTC 24 |
| Finished | Sep 04 08:41:33 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255930451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.255930451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.1963382860 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 2125785783 ps |
| CPU time | 5.13 seconds |
| Started | Sep 04 08:41:32 AM UTC 24 |
| Finished | Sep 04 08:41:38 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963382860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.1963382860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.801027283 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2348639731 ps |
| CPU time | 25.52 seconds |
| Started | Sep 04 08:41:33 AM UTC 24 |
| Finished | Sep 04 08:42:00 AM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801027283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.801027283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.3018196855 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 320441310 ps |
| CPU time | 4.01 seconds |
| Started | Sep 04 08:41:30 AM UTC 24 |
| Finished | Sep 04 08:41:35 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018196855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.3018196855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.303877795 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 237123853 ps |
| CPU time | 3.59 seconds |
| Started | Sep 04 08:41:30 AM UTC 24 |
| Finished | Sep 04 08:41:35 AM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303877795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.303877795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.509365408 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 268979722 ps |
| CPU time | 6.33 seconds |
| Started | Sep 04 08:41:34 AM UTC 24 |
| Finished | Sep 04 08:41:41 AM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509365408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.509365408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.2193963662 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 385911569 ps |
| CPU time | 12.02 seconds |
| Started | Sep 04 08:41:27 AM UTC 24 |
| Finished | Sep 04 08:41:41 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193963662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.2193963662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.965316008 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 23929880837 ps |
| CPU time | 306.35 seconds |
| Started | Sep 04 08:41:37 AM UTC 24 |
| Finished | Sep 04 08:46:48 AM UTC 24 |
| Peak memory | 290412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965316008 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.965316008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.3066758962 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2098133146 ps |
| CPU time | 28.18 seconds |
| Started | Sep 04 08:41:37 AM UTC 24 |
| Finished | Sep 04 08:42:06 AM UTC 24 |
| Peak memory | 257456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066758962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.3066758962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.1671213997 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 485215200 ps |
| CPU time | 4.3 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:37 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671213997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.1671213997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.108203294 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 115920108 ps |
| CPU time | 4.04 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:36 AM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108203294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.108203294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.1862744354 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1765946912 ps |
| CPU time | 6.39 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:39 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862744354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.1862744354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.1523565126 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 216966075 ps |
| CPU time | 3.31 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:36 AM UTC 24 |
| Peak memory | 251128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523565126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.1523565126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.2449604050 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 187254151 ps |
| CPU time | 4.66 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:37 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449604050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.2449604050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.2510961047 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 817977583 ps |
| CPU time | 5.34 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:38 AM UTC 24 |
| Peak memory | 250748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510961047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.2510961047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.1973861139 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 1808107911 ps |
| CPU time | 4.3 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:37 AM UTC 24 |
| Peak memory | 250832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973861139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.1973861139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.3339177020 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 2921554958 ps |
| CPU time | 10.73 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:43 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339177020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.3339177020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.2505657948 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 159461990 ps |
| CPU time | 3.98 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:37 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505657948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.2505657948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.85036963 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 516048839 ps |
| CPU time | 5.59 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:38 AM UTC 24 |
| Peak memory | 253232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85036963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.85036963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.2282206447 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 162277187 ps |
| CPU time | 4.68 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:37 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282206447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.2282206447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.384972001 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 389724448 ps |
| CPU time | 3.27 seconds |
| Started | Sep 04 08:48:31 AM UTC 24 |
| Finished | Sep 04 08:48:36 AM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384972001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.384972001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.4109518833 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 147145542 ps |
| CPU time | 3.8 seconds |
| Started | Sep 04 08:48:39 AM UTC 24 |
| Finished | Sep 04 08:48:45 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109518833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.4109518833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.2800047125 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 1465787203 ps |
| CPU time | 19.26 seconds |
| Started | Sep 04 08:48:39 AM UTC 24 |
| Finished | Sep 04 08:49:01 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800047125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.2800047125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.1688457834 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 249621391 ps |
| CPU time | 4.54 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:46 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688457834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.1688457834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.1387504299 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 604310952 ps |
| CPU time | 7.38 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:49 AM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387504299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.1387504299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.3191394504 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 519522241 ps |
| CPU time | 4.2 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:46 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191394504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.3191394504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.475076707 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 372167995 ps |
| CPU time | 5.08 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:47 AM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475076707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.475076707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.3279638349 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 119792869 ps |
| CPU time | 4.68 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:46 AM UTC 24 |
| Peak memory | 251112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279638349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.3279638349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.4015366106 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 274065528 ps |
| CPU time | 3.63 seconds |
| Started | Sep 04 08:41:43 AM UTC 24 |
| Finished | Sep 04 08:41:48 AM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015366106 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.4015366106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.1445852735 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1065061255 ps |
| CPU time | 14.92 seconds |
| Started | Sep 04 08:41:43 AM UTC 24 |
| Finished | Sep 04 08:41:59 AM UTC 24 |
| Peak memory | 253368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445852735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.1445852735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.218380957 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2257219442 ps |
| CPU time | 35.24 seconds |
| Started | Sep 04 08:41:39 AM UTC 24 |
| Finished | Sep 04 08:42:16 AM UTC 24 |
| Peak memory | 257540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218380957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.218380957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.2519615716 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 917631524 ps |
| CPU time | 16.9 seconds |
| Started | Sep 04 08:41:39 AM UTC 24 |
| Finished | Sep 04 08:41:57 AM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519615716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.2519615716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.3421549492 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 234995455 ps |
| CPU time | 3.95 seconds |
| Started | Sep 04 08:41:37 AM UTC 24 |
| Finished | Sep 04 08:41:42 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421549492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.3421549492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.4294435014 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 511234409 ps |
| CPU time | 7.78 seconds |
| Started | Sep 04 08:41:43 AM UTC 24 |
| Finished | Sep 04 08:41:52 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294435014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.4294435014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.329614615 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 147582559 ps |
| CPU time | 4.66 seconds |
| Started | Sep 04 08:41:43 AM UTC 24 |
| Finished | Sep 04 08:41:48 AM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329614615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.329614615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.382962453 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 4516992645 ps |
| CPU time | 28.93 seconds |
| Started | Sep 04 08:41:39 AM UTC 24 |
| Finished | Sep 04 08:42:09 AM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382962453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.382962453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.3850481282 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 6694604147 ps |
| CPU time | 15.42 seconds |
| Started | Sep 04 08:41:37 AM UTC 24 |
| Finished | Sep 04 08:41:54 AM UTC 24 |
| Peak memory | 257428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850481282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.3850481282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.3829268694 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1757597720 ps |
| CPU time | 6.68 seconds |
| Started | Sep 04 08:41:43 AM UTC 24 |
| Finished | Sep 04 08:41:51 AM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829268694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.3829268694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.572725915 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 620229918 ps |
| CPU time | 11.06 seconds |
| Started | Sep 04 08:41:37 AM UTC 24 |
| Finished | Sep 04 08:41:49 AM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572725915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.572725915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.1102454693 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 55968307829 ps |
| CPU time | 232.54 seconds |
| Started | Sep 04 08:41:43 AM UTC 24 |
| Finished | Sep 04 08:45:39 AM UTC 24 |
| Peak memory | 290484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102454693 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.1102454693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.1094894895 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1366385790 ps |
| CPU time | 46.45 seconds |
| Started | Sep 04 08:41:43 AM UTC 24 |
| Finished | Sep 04 08:42:31 AM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1094894895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.otp_ctrl_stress_all_with_rand_reset.1094894895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.1464169380 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 453059427 ps |
| CPU time | 6.19 seconds |
| Started | Sep 04 08:41:43 AM UTC 24 |
| Finished | Sep 04 08:41:50 AM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464169380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.1464169380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.1954441121 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 223366620 ps |
| CPU time | 3.59 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:45 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954441121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.1954441121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.2417715998 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 116104477 ps |
| CPU time | 2.94 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:45 AM UTC 24 |
| Peak memory | 251080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417715998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.2417715998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.1388432528 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 240084388 ps |
| CPU time | 4.89 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:47 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388432528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.1388432528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.3663269122 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 174069688 ps |
| CPU time | 5.08 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:47 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663269122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.3663269122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.1729966711 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 8412198960 ps |
| CPU time | 18.63 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:49:01 AM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729966711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.1729966711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.692668507 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 227200479 ps |
| CPU time | 3.48 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:45 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692668507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.692668507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.2037939693 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 2376328308 ps |
| CPU time | 28.77 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:49:11 AM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037939693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.2037939693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.1022152802 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1556132614 ps |
| CPU time | 4.34 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:46 AM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022152802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.1022152802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.2499051471 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 2602832533 ps |
| CPU time | 18.34 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:49:00 AM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499051471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.2499051471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.1554330286 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 205462816 ps |
| CPU time | 3.24 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:45 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554330286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.1554330286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.2717807207 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 974208170 ps |
| CPU time | 3.18 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:45 AM UTC 24 |
| Peak memory | 253144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717807207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.2717807207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.2174239522 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 219019669 ps |
| CPU time | 3.49 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:45 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174239522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.2174239522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.4178962829 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 204281420 ps |
| CPU time | 7.45 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:49 AM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178962829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.4178962829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.1778944081 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 106393892 ps |
| CPU time | 2.79 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:45 AM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778944081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.1778944081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.3324596835 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 692050469 ps |
| CPU time | 15.74 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:58 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324596835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.3324596835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.1337138417 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 596040202 ps |
| CPU time | 6.49 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:49 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337138417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.1337138417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.1447209893 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 162055667 ps |
| CPU time | 4.2 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:47 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447209893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.1447209893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.4071620776 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 594690711 ps |
| CPU time | 5.24 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:48 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071620776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.4071620776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.2174844202 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 70783364 ps |
| CPU time | 2.92 seconds |
| Started | Sep 04 08:41:52 AM UTC 24 |
| Finished | Sep 04 08:41:55 AM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174844202 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.2174844202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.1298674879 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 2470080300 ps |
| CPU time | 5.2 seconds |
| Started | Sep 04 08:41:49 AM UTC 24 |
| Finished | Sep 04 08:41:55 AM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298674879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.1298674879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.594700809 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 3516281423 ps |
| CPU time | 33.71 seconds |
| Started | Sep 04 08:41:48 AM UTC 24 |
| Finished | Sep 04 08:42:23 AM UTC 24 |
| Peak memory | 257508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594700809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.594700809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.1667176569 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2423979973 ps |
| CPU time | 20.15 seconds |
| Started | Sep 04 08:41:48 AM UTC 24 |
| Finished | Sep 04 08:42:09 AM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667176569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.1667176569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.1395840360 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 288605304 ps |
| CPU time | 5.19 seconds |
| Started | Sep 04 08:41:46 AM UTC 24 |
| Finished | Sep 04 08:41:52 AM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395840360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.1395840360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.3305035893 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1020872415 ps |
| CPU time | 18.34 seconds |
| Started | Sep 04 08:41:49 AM UTC 24 |
| Finished | Sep 04 08:42:09 AM UTC 24 |
| Peak memory | 257568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305035893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.3305035893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.3705457678 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 415980690 ps |
| CPU time | 13.08 seconds |
| Started | Sep 04 08:41:49 AM UTC 24 |
| Finished | Sep 04 08:42:03 AM UTC 24 |
| Peak memory | 253336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705457678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.3705457678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.3257065059 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 629091508 ps |
| CPU time | 8.89 seconds |
| Started | Sep 04 08:41:48 AM UTC 24 |
| Finished | Sep 04 08:41:58 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257065059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.3257065059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.1267922206 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 195532401 ps |
| CPU time | 7.59 seconds |
| Started | Sep 04 08:41:46 AM UTC 24 |
| Finished | Sep 04 08:41:55 AM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267922206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.1267922206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.1192997806 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 285531848 ps |
| CPU time | 9.94 seconds |
| Started | Sep 04 08:41:51 AM UTC 24 |
| Finished | Sep 04 08:42:02 AM UTC 24 |
| Peak memory | 251136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192997806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.1192997806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.1221956054 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 570686460 ps |
| CPU time | 5.49 seconds |
| Started | Sep 04 08:41:44 AM UTC 24 |
| Finished | Sep 04 08:41:51 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221956054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.1221956054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.1213386095 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 50237341705 ps |
| CPU time | 151.33 seconds |
| Started | Sep 04 08:41:52 AM UTC 24 |
| Finished | Sep 04 08:44:25 AM UTC 24 |
| Peak memory | 284128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213386095 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.1213386095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.2563572233 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 537115501 ps |
| CPU time | 20.31 seconds |
| Started | Sep 04 08:41:51 AM UTC 24 |
| Finished | Sep 04 08:42:13 AM UTC 24 |
| Peak memory | 250796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563572233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.2563572233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.3218507692 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 621350427 ps |
| CPU time | 5.17 seconds |
| Started | Sep 04 08:48:40 AM UTC 24 |
| Finished | Sep 04 08:48:48 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218507692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.3218507692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.962991171 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 179823048 ps |
| CPU time | 5.03 seconds |
| Started | Sep 04 08:48:51 AM UTC 24 |
| Finished | Sep 04 08:48:57 AM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962991171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.962991171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.518656546 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 1579526951 ps |
| CPU time | 5.3 seconds |
| Started | Sep 04 08:48:51 AM UTC 24 |
| Finished | Sep 04 08:48:57 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518656546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.518656546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.1771580835 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 3218708941 ps |
| CPU time | 7.21 seconds |
| Started | Sep 04 08:48:51 AM UTC 24 |
| Finished | Sep 04 08:49:00 AM UTC 24 |
| Peak memory | 257376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771580835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.1771580835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.543100295 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 184064438 ps |
| CPU time | 3.42 seconds |
| Started | Sep 04 08:48:51 AM UTC 24 |
| Finished | Sep 04 08:48:56 AM UTC 24 |
| Peak memory | 250992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543100295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.543100295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.4073017917 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 163536175 ps |
| CPU time | 6.6 seconds |
| Started | Sep 04 08:48:51 AM UTC 24 |
| Finished | Sep 04 08:48:59 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073017917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.4073017917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.912371270 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 595557099 ps |
| CPU time | 4.19 seconds |
| Started | Sep 04 08:48:51 AM UTC 24 |
| Finished | Sep 04 08:48:57 AM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912371270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.912371270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.2374542952 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 6436105423 ps |
| CPU time | 11.16 seconds |
| Started | Sep 04 08:48:51 AM UTC 24 |
| Finished | Sep 04 08:49:04 AM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374542952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.2374542952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.2275838 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 678026119 ps |
| CPU time | 6.89 seconds |
| Started | Sep 04 08:48:51 AM UTC 24 |
| Finished | Sep 04 08:48:59 AM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.2275838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.2611682936 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 267022504 ps |
| CPU time | 3.23 seconds |
| Started | Sep 04 08:48:51 AM UTC 24 |
| Finished | Sep 04 08:48:56 AM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611682936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.2611682936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.3755631831 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 1711638596 ps |
| CPU time | 5.69 seconds |
| Started | Sep 04 08:48:51 AM UTC 24 |
| Finished | Sep 04 08:48:58 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755631831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.3755631831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.3890466863 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 213738518 ps |
| CPU time | 3.49 seconds |
| Started | Sep 04 08:48:51 AM UTC 24 |
| Finished | Sep 04 08:48:56 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890466863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3890466863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.2226080232 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 268940265 ps |
| CPU time | 6.08 seconds |
| Started | Sep 04 08:48:51 AM UTC 24 |
| Finished | Sep 04 08:48:59 AM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226080232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.2226080232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.840276092 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 149596433 ps |
| CPU time | 3.48 seconds |
| Started | Sep 04 08:48:51 AM UTC 24 |
| Finished | Sep 04 08:48:56 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840276092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.840276092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.2961638031 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 142777439 ps |
| CPU time | 5.21 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:48:58 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961638031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.2961638031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.790792171 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 106234972 ps |
| CPU time | 3.21 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:48:56 AM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790792171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.790792171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.939664198 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 756395060 ps |
| CPU time | 7.68 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:49:01 AM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939664198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.939664198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.2628934712 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 242177363 ps |
| CPU time | 4.04 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:48:57 AM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628934712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.2628934712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.1890952603 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 627464301 ps |
| CPU time | 6.94 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:49:00 AM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890952603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.1890952603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.180691161 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 42601031 ps |
| CPU time | 2.28 seconds |
| Started | Sep 04 08:42:00 AM UTC 24 |
| Finished | Sep 04 08:42:03 AM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180691161 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.180691161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.1726865960 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 5956945293 ps |
| CPU time | 34.58 seconds |
| Started | Sep 04 08:41:59 AM UTC 24 |
| Finished | Sep 04 08:42:35 AM UTC 24 |
| Peak memory | 257552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726865960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.1726865960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.2783007563 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 15473035197 ps |
| CPU time | 40.95 seconds |
| Started | Sep 04 08:41:59 AM UTC 24 |
| Finished | Sep 04 08:42:42 AM UTC 24 |
| Peak memory | 257464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783007563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.2783007563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.852582376 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 720708301 ps |
| CPU time | 18.57 seconds |
| Started | Sep 04 08:41:59 AM UTC 24 |
| Finished | Sep 04 08:42:19 AM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852582376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.852582376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.1338185883 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 283664726 ps |
| CPU time | 6.23 seconds |
| Started | Sep 04 08:41:59 AM UTC 24 |
| Finished | Sep 04 08:42:06 AM UTC 24 |
| Peak memory | 251100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338185883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.1338185883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.333041806 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 380621566 ps |
| CPU time | 5.57 seconds |
| Started | Sep 04 08:41:59 AM UTC 24 |
| Finished | Sep 04 08:42:06 AM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333041806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.333041806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.2991208822 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 490111922 ps |
| CPU time | 14.73 seconds |
| Started | Sep 04 08:41:59 AM UTC 24 |
| Finished | Sep 04 08:42:15 AM UTC 24 |
| Peak memory | 251100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991208822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.2991208822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.895256860 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 3897291370 ps |
| CPU time | 9.11 seconds |
| Started | Sep 04 08:41:59 AM UTC 24 |
| Finished | Sep 04 08:42:09 AM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895256860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.895256860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.2037686518 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 146270930 ps |
| CPU time | 7.71 seconds |
| Started | Sep 04 08:41:59 AM UTC 24 |
| Finished | Sep 04 08:42:08 AM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037686518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.2037686518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.600238028 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 137724505 ps |
| CPU time | 6.81 seconds |
| Started | Sep 04 08:41:59 AM UTC 24 |
| Finished | Sep 04 08:42:07 AM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600238028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.600238028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.80700398 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 92750145408 ps |
| CPU time | 121.84 seconds |
| Started | Sep 04 08:42:00 AM UTC 24 |
| Finished | Sep 04 08:44:04 AM UTC 24 |
| Peak memory | 271836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80700398 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.80700398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.115166616 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 12241332530 ps |
| CPU time | 45.21 seconds |
| Started | Sep 04 08:42:00 AM UTC 24 |
| Finished | Sep 04 08:42:46 AM UTC 24 |
| Peak memory | 257856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=115166616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.115166616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.3897050588 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 12555507433 ps |
| CPU time | 36.55 seconds |
| Started | Sep 04 08:42:00 AM UTC 24 |
| Finished | Sep 04 08:42:38 AM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897050588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.3897050588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.1714856074 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 271548663 ps |
| CPU time | 3.57 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:48:57 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714856074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.1714856074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.952055207 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 187760333 ps |
| CPU time | 4.61 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:48:58 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952055207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.952055207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.3063797908 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 111590348 ps |
| CPU time | 3.63 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:48:57 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063797908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3063797908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.2032115838 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 664214228 ps |
| CPU time | 9.43 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:49:03 AM UTC 24 |
| Peak memory | 250752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032115838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.2032115838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.4154010617 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 161472421 ps |
| CPU time | 4.66 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:48:58 AM UTC 24 |
| Peak memory | 250732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154010617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.4154010617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.2062862683 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 550667835 ps |
| CPU time | 7.34 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:49:01 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062862683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.2062862683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.413778309 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 110897785 ps |
| CPU time | 4.81 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:48:58 AM UTC 24 |
| Peak memory | 250996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413778309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.413778309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.3561246301 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 290100268 ps |
| CPU time | 14.12 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:49:07 AM UTC 24 |
| Peak memory | 250480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561246301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.3561246301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.4210512947 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 2507350768 ps |
| CPU time | 8.1 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:49:01 AM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210512947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.4210512947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.2902825211 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 9017442510 ps |
| CPU time | 19.95 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:49:13 AM UTC 24 |
| Peak memory | 251576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902825211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.2902825211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.2444259863 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 109034620 ps |
| CPU time | 4.7 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:48:58 AM UTC 24 |
| Peak memory | 250576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444259863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.2444259863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.3185615731 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 170510704 ps |
| CPU time | 6.84 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:49:00 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185615731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.3185615731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.443206241 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 356346376 ps |
| CPU time | 3.98 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:48:57 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443206241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.443206241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.2137583508 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 2317345319 ps |
| CPU time | 15.92 seconds |
| Started | Sep 04 08:48:52 AM UTC 24 |
| Finished | Sep 04 08:49:09 AM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137583508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.2137583508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.3773281164 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 95375076 ps |
| CPU time | 2.88 seconds |
| Started | Sep 04 08:48:59 AM UTC 24 |
| Finished | Sep 04 08:49:04 AM UTC 24 |
| Peak memory | 250740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773281164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.3773281164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.323087999 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 418596245 ps |
| CPU time | 4.25 seconds |
| Started | Sep 04 08:48:59 AM UTC 24 |
| Finished | Sep 04 08:49:05 AM UTC 24 |
| Peak memory | 250364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323087999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.323087999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.3825104523 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 141953075 ps |
| CPU time | 3.3 seconds |
| Started | Sep 04 08:48:59 AM UTC 24 |
| Finished | Sep 04 08:49:04 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825104523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.3825104523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.597988257 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 1937778934 ps |
| CPU time | 22.4 seconds |
| Started | Sep 04 08:48:59 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597988257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.597988257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.2324174021 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 158334544 ps |
| CPU time | 3.6 seconds |
| Started | Sep 04 08:48:59 AM UTC 24 |
| Finished | Sep 04 08:49:04 AM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324174021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2324174021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.2858543371 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 3167608778 ps |
| CPU time | 13.1 seconds |
| Started | Sep 04 08:48:59 AM UTC 24 |
| Finished | Sep 04 08:49:14 AM UTC 24 |
| Peak memory | 251064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858543371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.2858543371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.274485099 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 82820930 ps |
| CPU time | 2.61 seconds |
| Started | Sep 04 08:42:10 AM UTC 24 |
| Finished | Sep 04 08:42:14 AM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274485099 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.274485099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.2794654358 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 6230131062 ps |
| CPU time | 14.17 seconds |
| Started | Sep 04 08:42:03 AM UTC 24 |
| Finished | Sep 04 08:42:19 AM UTC 24 |
| Peak memory | 253556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794654358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.2794654358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.3915940305 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 21233163318 ps |
| CPU time | 48.97 seconds |
| Started | Sep 04 08:42:03 AM UTC 24 |
| Finished | Sep 04 08:42:54 AM UTC 24 |
| Peak memory | 257340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915940305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.3915940305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.1533000172 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 28317048631 ps |
| CPU time | 84.09 seconds |
| Started | Sep 04 08:42:02 AM UTC 24 |
| Finished | Sep 04 08:43:28 AM UTC 24 |
| Peak memory | 253408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533000172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.1533000172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.325328360 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 498149140 ps |
| CPU time | 5.33 seconds |
| Started | Sep 04 08:42:02 AM UTC 24 |
| Finished | Sep 04 08:42:08 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325328360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.325328360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.2907901353 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1349422243 ps |
| CPU time | 12.99 seconds |
| Started | Sep 04 08:42:05 AM UTC 24 |
| Finished | Sep 04 08:42:19 AM UTC 24 |
| Peak memory | 253344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907901353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.2907901353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.3520680244 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 290609432 ps |
| CPU time | 9.56 seconds |
| Started | Sep 04 08:42:02 AM UTC 24 |
| Finished | Sep 04 08:42:13 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520680244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.3520680244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.1610496986 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 4605568441 ps |
| CPU time | 10.63 seconds |
| Started | Sep 04 08:42:02 AM UTC 24 |
| Finished | Sep 04 08:42:14 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610496986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.1610496986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.3787943799 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 2665594984 ps |
| CPU time | 9.31 seconds |
| Started | Sep 04 08:42:08 AM UTC 24 |
| Finished | Sep 04 08:42:19 AM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787943799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.3787943799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.564546918 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 526226734 ps |
| CPU time | 8.25 seconds |
| Started | Sep 04 08:42:00 AM UTC 24 |
| Finished | Sep 04 08:42:09 AM UTC 24 |
| Peak memory | 257568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564546918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.564546918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.4224262063 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 8761563329 ps |
| CPU time | 52.42 seconds |
| Started | Sep 04 08:42:10 AM UTC 24 |
| Finished | Sep 04 08:43:04 AM UTC 24 |
| Peak memory | 253376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224262063 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.4224262063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.952052008 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1743791403 ps |
| CPU time | 13.76 seconds |
| Started | Sep 04 08:42:08 AM UTC 24 |
| Finished | Sep 04 08:42:23 AM UTC 24 |
| Peak memory | 251564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952052008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.952052008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.2998267753 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 1734596531 ps |
| CPU time | 5.24 seconds |
| Started | Sep 04 08:48:59 AM UTC 24 |
| Finished | Sep 04 08:49:06 AM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998267753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.2998267753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.3778711176 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 7383873412 ps |
| CPU time | 15.64 seconds |
| Started | Sep 04 08:48:59 AM UTC 24 |
| Finished | Sep 04 08:49:16 AM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778711176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.3778711176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.2089885019 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 301884787 ps |
| CPU time | 3.74 seconds |
| Started | Sep 04 08:48:59 AM UTC 24 |
| Finished | Sep 04 08:49:04 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089885019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.2089885019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.2803962071 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 122883755 ps |
| CPU time | 3.17 seconds |
| Started | Sep 04 08:49:00 AM UTC 24 |
| Finished | Sep 04 08:49:04 AM UTC 24 |
| Peak memory | 251128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803962071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2803962071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.1025594689 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 1550979627 ps |
| CPU time | 4.43 seconds |
| Started | Sep 04 08:49:00 AM UTC 24 |
| Finished | Sep 04 08:49:05 AM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025594689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.1025594689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.3089057130 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 1144893456 ps |
| CPU time | 6.88 seconds |
| Started | Sep 04 08:49:00 AM UTC 24 |
| Finished | Sep 04 08:49:08 AM UTC 24 |
| Peak memory | 250796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089057130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.3089057130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.3766464199 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 381852183 ps |
| CPU time | 2.95 seconds |
| Started | Sep 04 08:49:00 AM UTC 24 |
| Finished | Sep 04 08:49:04 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766464199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.3766464199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.2752595886 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 2172696640 ps |
| CPU time | 3.88 seconds |
| Started | Sep 04 08:49:00 AM UTC 24 |
| Finished | Sep 04 08:49:05 AM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752595886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.2752595886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.2820235359 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 418618949 ps |
| CPU time | 3.78 seconds |
| Started | Sep 04 08:49:00 AM UTC 24 |
| Finished | Sep 04 08:49:05 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820235359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.2820235359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.1892783596 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 883295869 ps |
| CPU time | 11.12 seconds |
| Started | Sep 04 08:49:00 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892783596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.1892783596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.3528585965 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 130261924 ps |
| CPU time | 3.52 seconds |
| Started | Sep 04 08:49:00 AM UTC 24 |
| Finished | Sep 04 08:49:05 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528585965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.3528585965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.1871496753 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 426982359 ps |
| CPU time | 3.64 seconds |
| Started | Sep 04 08:49:00 AM UTC 24 |
| Finished | Sep 04 08:49:05 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871496753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.1871496753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.4280281125 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 224175233 ps |
| CPU time | 3.57 seconds |
| Started | Sep 04 08:49:00 AM UTC 24 |
| Finished | Sep 04 08:49:05 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280281125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.4280281125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.3844789908 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 3271608087 ps |
| CPU time | 6.63 seconds |
| Started | Sep 04 08:49:00 AM UTC 24 |
| Finished | Sep 04 08:49:08 AM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844789908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.3844789908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.1256376556 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 117166369 ps |
| CPU time | 3.99 seconds |
| Started | Sep 04 08:49:00 AM UTC 24 |
| Finished | Sep 04 08:49:05 AM UTC 24 |
| Peak memory | 253328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256376556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.1256376556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.504404459 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 1087543311 ps |
| CPU time | 14.52 seconds |
| Started | Sep 04 08:49:00 AM UTC 24 |
| Finished | Sep 04 08:49:16 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504404459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.504404459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.44906270 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 159165550 ps |
| CPU time | 3.92 seconds |
| Started | Sep 04 08:49:00 AM UTC 24 |
| Finished | Sep 04 08:49:05 AM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44906270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.44906270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.734005561 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 374507183 ps |
| CPU time | 4.18 seconds |
| Started | Sep 04 08:49:00 AM UTC 24 |
| Finished | Sep 04 08:49:06 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734005561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.734005561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.3350279268 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 380001915 ps |
| CPU time | 2.97 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:11 AM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350279268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.3350279268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.3264538970 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 149533960 ps |
| CPU time | 2.7 seconds |
| Started | Sep 04 08:39:21 AM UTC 24 |
| Finished | Sep 04 08:39:25 AM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264538970 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.3264538970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.1752493338 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 4278808730 ps |
| CPU time | 42.06 seconds |
| Started | Sep 04 08:39:11 AM UTC 24 |
| Finished | Sep 04 08:39:54 AM UTC 24 |
| Peak memory | 253684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752493338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.1752493338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.2490872788 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 303209519 ps |
| CPU time | 8.56 seconds |
| Started | Sep 04 08:39:15 AM UTC 24 |
| Finished | Sep 04 08:39:25 AM UTC 24 |
| Peak memory | 253368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490872788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.2490872788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.1927291578 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 12920460087 ps |
| CPU time | 46.27 seconds |
| Started | Sep 04 08:39:14 AM UTC 24 |
| Finished | Sep 04 08:40:02 AM UTC 24 |
| Peak memory | 255428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927291578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1927291578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.3442723970 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1063380597 ps |
| CPU time | 21.19 seconds |
| Started | Sep 04 08:39:13 AM UTC 24 |
| Finished | Sep 04 08:39:36 AM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442723970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.3442723970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.3795050350 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 405081610 ps |
| CPU time | 7.23 seconds |
| Started | Sep 04 08:39:15 AM UTC 24 |
| Finished | Sep 04 08:39:24 AM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795050350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.3795050350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.142017482 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 377697233 ps |
| CPU time | 5.32 seconds |
| Started | Sep 04 08:39:13 AM UTC 24 |
| Finished | Sep 04 08:39:19 AM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142017482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.142017482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.1133879877 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 247512231 ps |
| CPU time | 7.06 seconds |
| Started | Sep 04 08:39:12 AM UTC 24 |
| Finished | Sep 04 08:39:20 AM UTC 24 |
| Peak memory | 257772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133879877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.1133879877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.2247778112 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 172512084 ps |
| CPU time | 7.84 seconds |
| Started | Sep 04 08:39:15 AM UTC 24 |
| Finished | Sep 04 08:39:24 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247778112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.2247778112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.2912499751 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 165661286363 ps |
| CPU time | 317.41 seconds |
| Started | Sep 04 08:39:21 AM UTC 24 |
| Finished | Sep 04 08:44:43 AM UTC 24 |
| Peak memory | 285908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912499751 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.2912499751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.2713655615 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 169016431 ps |
| CPU time | 4.71 seconds |
| Started | Sep 04 08:39:10 AM UTC 24 |
| Finished | Sep 04 08:39:15 AM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713655615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.2713655615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.2764244140 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 396849330 ps |
| CPU time | 8.87 seconds |
| Started | Sep 04 08:39:17 AM UTC 24 |
| Finished | Sep 04 08:39:27 AM UTC 24 |
| Peak memory | 257716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764244140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.2764244140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.1692358665 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 170148580 ps |
| CPU time | 2.85 seconds |
| Started | Sep 04 08:42:19 AM UTC 24 |
| Finished | Sep 04 08:42:23 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692358665 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.1692358665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.1080264265 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 444864483 ps |
| CPU time | 12.26 seconds |
| Started | Sep 04 08:42:13 AM UTC 24 |
| Finished | Sep 04 08:42:27 AM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080264265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.1080264265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.1427886982 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 7174284553 ps |
| CPU time | 35.66 seconds |
| Started | Sep 04 08:42:13 AM UTC 24 |
| Finished | Sep 04 08:42:51 AM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427886982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.1427886982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.2432209973 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 558514088 ps |
| CPU time | 18.99 seconds |
| Started | Sep 04 08:42:12 AM UTC 24 |
| Finished | Sep 04 08:42:32 AM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432209973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.2432209973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.2660590463 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 239056425 ps |
| CPU time | 6.6 seconds |
| Started | Sep 04 08:42:10 AM UTC 24 |
| Finished | Sep 04 08:42:18 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660590463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.2660590463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.3309432703 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 2843981129 ps |
| CPU time | 18.29 seconds |
| Started | Sep 04 08:42:15 AM UTC 24 |
| Finished | Sep 04 08:42:35 AM UTC 24 |
| Peak memory | 257568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309432703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.3309432703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.2943640589 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 790596102 ps |
| CPU time | 9.29 seconds |
| Started | Sep 04 08:42:15 AM UTC 24 |
| Finished | Sep 04 08:42:26 AM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943640589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.2943640589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.1756450965 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1092464161 ps |
| CPU time | 8.65 seconds |
| Started | Sep 04 08:42:10 AM UTC 24 |
| Finished | Sep 04 08:42:20 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756450965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.1756450965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.2191040971 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 760973703 ps |
| CPU time | 17.6 seconds |
| Started | Sep 04 08:42:10 AM UTC 24 |
| Finished | Sep 04 08:42:29 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191040971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.2191040971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.3018056128 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 429864940 ps |
| CPU time | 6.22 seconds |
| Started | Sep 04 08:42:15 AM UTC 24 |
| Finished | Sep 04 08:42:23 AM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018056128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.3018056128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.493293164 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 4265917583 ps |
| CPU time | 10.21 seconds |
| Started | Sep 04 08:42:10 AM UTC 24 |
| Finished | Sep 04 08:42:21 AM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493293164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.493293164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.942169868 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 12978541110 ps |
| CPU time | 130.47 seconds |
| Started | Sep 04 08:42:19 AM UTC 24 |
| Finished | Sep 04 08:44:32 AM UTC 24 |
| Peak memory | 267704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942169868 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.942169868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.2892414154 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 765839114 ps |
| CPU time | 14.19 seconds |
| Started | Sep 04 08:42:17 AM UTC 24 |
| Finished | Sep 04 08:42:33 AM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892414154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.2892414154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.3635766027 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1870393063 ps |
| CPU time | 3.93 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635766027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.3635766027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.2759103215 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 278731902 ps |
| CPU time | 3.8 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759103215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.2759103215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.3888393297 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 156380456 ps |
| CPU time | 3.56 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888393297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.3888393297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.1648314706 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 168976272 ps |
| CPU time | 3.77 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648314706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.1648314706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.2140856392 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 527181442 ps |
| CPU time | 3.04 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:11 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140856392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.2140856392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.4102632608 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 105695749 ps |
| CPU time | 2.63 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:11 AM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102632608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.4102632608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.617596480 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 272649882 ps |
| CPU time | 4.49 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:13 AM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617596480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.617596480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.4169070508 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 370914860 ps |
| CPU time | 4.11 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169070508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.4169070508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.3646540060 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 559965317 ps |
| CPU time | 3.87 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646540060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.3646540060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.1061190796 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 282228481 ps |
| CPU time | 4.17 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:13 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061190796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.1061190796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.819543647 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 94296266 ps |
| CPU time | 2.69 seconds |
| Started | Sep 04 08:42:26 AM UTC 24 |
| Finished | Sep 04 08:42:30 AM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819543647 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.819543647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.1140536523 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 338743780 ps |
| CPU time | 12.86 seconds |
| Started | Sep 04 08:42:23 AM UTC 24 |
| Finished | Sep 04 08:42:37 AM UTC 24 |
| Peak memory | 253720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140536523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.1140536523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.2605831086 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 513674668 ps |
| CPU time | 18.06 seconds |
| Started | Sep 04 08:42:21 AM UTC 24 |
| Finished | Sep 04 08:42:41 AM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605831086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.2605831086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.1461306669 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 7346975973 ps |
| CPU time | 13.76 seconds |
| Started | Sep 04 08:42:21 AM UTC 24 |
| Finished | Sep 04 08:42:36 AM UTC 24 |
| Peak memory | 253436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461306669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1461306669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.2687429962 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 158274935 ps |
| CPU time | 5.42 seconds |
| Started | Sep 04 08:42:21 AM UTC 24 |
| Finished | Sep 04 08:42:28 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687429962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.2687429962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.1430469394 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1307293345 ps |
| CPU time | 14.76 seconds |
| Started | Sep 04 08:42:23 AM UTC 24 |
| Finished | Sep 04 08:42:39 AM UTC 24 |
| Peak memory | 251456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430469394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.1430469394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.4130937271 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 770329822 ps |
| CPU time | 31.66 seconds |
| Started | Sep 04 08:42:23 AM UTC 24 |
| Finished | Sep 04 08:42:56 AM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130937271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.4130937271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.4244607288 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1891368635 ps |
| CPU time | 12.99 seconds |
| Started | Sep 04 08:42:21 AM UTC 24 |
| Finished | Sep 04 08:42:35 AM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244607288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.4244607288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.3716931759 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 911005455 ps |
| CPU time | 16.52 seconds |
| Started | Sep 04 08:42:21 AM UTC 24 |
| Finished | Sep 04 08:42:39 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716931759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.3716931759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.1907137598 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 3941444069 ps |
| CPU time | 8.67 seconds |
| Started | Sep 04 08:42:23 AM UTC 24 |
| Finished | Sep 04 08:42:33 AM UTC 24 |
| Peak memory | 253392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907137598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.1907137598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.2339519009 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 389330643 ps |
| CPU time | 7.74 seconds |
| Started | Sep 04 08:42:21 AM UTC 24 |
| Finished | Sep 04 08:42:30 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339519009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.2339519009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.2382535858 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 3199174320 ps |
| CPU time | 110.79 seconds |
| Started | Sep 04 08:42:26 AM UTC 24 |
| Finished | Sep 04 08:44:19 AM UTC 24 |
| Peak memory | 268056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382535858 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.2382535858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.1556192488 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 16502204688 ps |
| CPU time | 54.82 seconds |
| Started | Sep 04 08:42:26 AM UTC 24 |
| Finished | Sep 04 08:43:22 AM UTC 24 |
| Peak memory | 267952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1556192488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.otp_ctrl_stress_all_with_rand_reset.1556192488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.341605392 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 14916813798 ps |
| CPU time | 35.62 seconds |
| Started | Sep 04 08:42:26 AM UTC 24 |
| Finished | Sep 04 08:43:03 AM UTC 24 |
| Peak memory | 253524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341605392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.341605392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.339113039 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 353156169 ps |
| CPU time | 3.32 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339113039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.339113039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.350246325 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 356870620 ps |
| CPU time | 3.74 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350246325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.350246325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.126116850 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 195968200 ps |
| CPU time | 4.97 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:13 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126116850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.126116850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.2526450121 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 180760970 ps |
| CPU time | 3.2 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526450121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.2526450121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.2596566536 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 257921251 ps |
| CPU time | 3.02 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:11 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596566536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.2596566536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.1003197718 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 240135290 ps |
| CPU time | 2.8 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:11 AM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003197718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.1003197718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.506573647 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 477850394 ps |
| CPU time | 3.53 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506573647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.506573647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.560669775 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 498819155 ps |
| CPU time | 3.47 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560669775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.560669775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.2057344881 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 111665676 ps |
| CPU time | 3.43 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057344881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.2057344881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.3949856982 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 265878358 ps |
| CPU time | 3.33 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949856982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.3949856982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.3804074818 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 79478591 ps |
| CPU time | 2.33 seconds |
| Started | Sep 04 08:42:34 AM UTC 24 |
| Finished | Sep 04 08:42:38 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804074818 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.3804074818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.3119226311 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 209011519 ps |
| CPU time | 9.91 seconds |
| Started | Sep 04 08:42:31 AM UTC 24 |
| Finished | Sep 04 08:42:42 AM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119226311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.3119226311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.2908496199 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 2344738380 ps |
| CPU time | 16.46 seconds |
| Started | Sep 04 08:42:31 AM UTC 24 |
| Finished | Sep 04 08:42:49 AM UTC 24 |
| Peak memory | 257532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908496199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2908496199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.2437003045 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 527682067 ps |
| CPU time | 4.98 seconds |
| Started | Sep 04 08:42:30 AM UTC 24 |
| Finished | Sep 04 08:42:36 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437003045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.2437003045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.4280088131 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 1551237336 ps |
| CPU time | 24.76 seconds |
| Started | Sep 04 08:42:34 AM UTC 24 |
| Finished | Sep 04 08:43:00 AM UTC 24 |
| Peak memory | 253664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280088131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.4280088131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.1595330678 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1259878589 ps |
| CPU time | 24.09 seconds |
| Started | Sep 04 08:42:34 AM UTC 24 |
| Finished | Sep 04 08:42:59 AM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595330678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.1595330678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.236413982 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 261417464 ps |
| CPU time | 6.27 seconds |
| Started | Sep 04 08:42:30 AM UTC 24 |
| Finished | Sep 04 08:42:37 AM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236413982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.236413982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.3205065959 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 1061589174 ps |
| CPU time | 16.53 seconds |
| Started | Sep 04 08:42:30 AM UTC 24 |
| Finished | Sep 04 08:42:48 AM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205065959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.3205065959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.2896794860 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 143540937 ps |
| CPU time | 5.65 seconds |
| Started | Sep 04 08:42:34 AM UTC 24 |
| Finished | Sep 04 08:42:41 AM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896794860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.2896794860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.714472416 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 395977794 ps |
| CPU time | 8.97 seconds |
| Started | Sep 04 08:42:30 AM UTC 24 |
| Finished | Sep 04 08:42:40 AM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714472416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.714472416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.375182831 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 1366027050 ps |
| CPU time | 24.07 seconds |
| Started | Sep 04 08:42:34 AM UTC 24 |
| Finished | Sep 04 08:43:00 AM UTC 24 |
| Peak memory | 253280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375182831 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.375182831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.1755476398 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 7424569221 ps |
| CPU time | 129.25 seconds |
| Started | Sep 04 08:42:34 AM UTC 24 |
| Finished | Sep 04 08:44:46 AM UTC 24 |
| Peak memory | 278132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1755476398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.otp_ctrl_stress_all_with_rand_reset.1755476398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.1903110333 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 1346649885 ps |
| CPU time | 23.08 seconds |
| Started | Sep 04 08:42:34 AM UTC 24 |
| Finished | Sep 04 08:42:58 AM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903110333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.1903110333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.674526075 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 253190952 ps |
| CPU time | 3.96 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:13 AM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674526075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.674526075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.4194313789 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 127066077 ps |
| CPU time | 3.57 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194313789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.4194313789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.2924653534 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 376708951 ps |
| CPU time | 3.34 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924653534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.2924653534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.2761080831 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 115152323 ps |
| CPU time | 3.97 seconds |
| Started | Sep 04 08:49:07 AM UTC 24 |
| Finished | Sep 04 08:49:13 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761080831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.2761080831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.1504835225 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 478150277 ps |
| CPU time | 3.15 seconds |
| Started | Sep 04 08:49:08 AM UTC 24 |
| Finished | Sep 04 08:49:12 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504835225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.1504835225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.1661273174 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 2551395002 ps |
| CPU time | 5.36 seconds |
| Started | Sep 04 08:49:08 AM UTC 24 |
| Finished | Sep 04 08:49:14 AM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661273174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.1661273174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.1223401001 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 458366299 ps |
| CPU time | 4.2 seconds |
| Started | Sep 04 08:49:08 AM UTC 24 |
| Finished | Sep 04 08:49:13 AM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223401001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.1223401001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.1170123034 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 512706200 ps |
| CPU time | 3.9 seconds |
| Started | Sep 04 08:49:08 AM UTC 24 |
| Finished | Sep 04 08:49:13 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170123034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1170123034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.3073917017 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 109158279 ps |
| CPU time | 2.86 seconds |
| Started | Sep 04 08:42:41 AM UTC 24 |
| Finished | Sep 04 08:42:45 AM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073917017 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.3073917017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.4183947143 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 1276595786 ps |
| CPU time | 11.91 seconds |
| Started | Sep 04 08:42:39 AM UTC 24 |
| Finished | Sep 04 08:42:52 AM UTC 24 |
| Peak memory | 257496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183947143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.4183947143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.4196547999 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 15326177096 ps |
| CPU time | 36.6 seconds |
| Started | Sep 04 08:42:39 AM UTC 24 |
| Finished | Sep 04 08:43:17 AM UTC 24 |
| Peak memory | 257404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196547999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.4196547999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.803865021 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 581019364 ps |
| CPU time | 8.78 seconds |
| Started | Sep 04 08:42:39 AM UTC 24 |
| Finished | Sep 04 08:42:49 AM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803865021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.803865021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.3599503064 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 261418957 ps |
| CPU time | 4.58 seconds |
| Started | Sep 04 08:42:36 AM UTC 24 |
| Finished | Sep 04 08:42:42 AM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599503064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.3599503064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.3082191844 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2025664294 ps |
| CPU time | 34.32 seconds |
| Started | Sep 04 08:42:39 AM UTC 24 |
| Finished | Sep 04 08:43:15 AM UTC 24 |
| Peak memory | 253492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082191844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.3082191844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.86848664 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 660356256 ps |
| CPU time | 10.24 seconds |
| Started | Sep 04 08:42:39 AM UTC 24 |
| Finished | Sep 04 08:42:50 AM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86848664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.86848664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.953087125 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1905500644 ps |
| CPU time | 13.79 seconds |
| Started | Sep 04 08:42:36 AM UTC 24 |
| Finished | Sep 04 08:42:51 AM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953087125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.953087125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.3131287408 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 590463433 ps |
| CPU time | 6.49 seconds |
| Started | Sep 04 08:42:39 AM UTC 24 |
| Finished | Sep 04 08:42:47 AM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131287408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.3131287408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.2937788248 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 5911769253 ps |
| CPU time | 11.21 seconds |
| Started | Sep 04 08:42:36 AM UTC 24 |
| Finished | Sep 04 08:42:48 AM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937788248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.2937788248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.1164393685 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 20917555228 ps |
| CPU time | 67.58 seconds |
| Started | Sep 04 08:42:41 AM UTC 24 |
| Finished | Sep 04 08:43:50 AM UTC 24 |
| Peak memory | 257472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164393685 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.1164393685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.1652091527 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1018408294 ps |
| CPU time | 20.38 seconds |
| Started | Sep 04 08:42:39 AM UTC 24 |
| Finished | Sep 04 08:43:01 AM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652091527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.1652091527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.913956439 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 1867289542 ps |
| CPU time | 5.42 seconds |
| Started | Sep 04 08:49:17 AM UTC 24 |
| Finished | Sep 04 08:49:24 AM UTC 24 |
| Peak memory | 253260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913956439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.913956439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.2076256817 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 1983546620 ps |
| CPU time | 6.46 seconds |
| Started | Sep 04 08:49:17 AM UTC 24 |
| Finished | Sep 04 08:49:25 AM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076256817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.2076256817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.2221184177 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 2411689430 ps |
| CPU time | 5.04 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:24 AM UTC 24 |
| Peak memory | 250660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221184177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.2221184177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.2117099755 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 399838739 ps |
| CPU time | 3.68 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:22 AM UTC 24 |
| Peak memory | 250904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117099755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.2117099755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.566981268 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 113997492 ps |
| CPU time | 4.14 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566981268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.566981268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.2827391727 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 1987001977 ps |
| CPU time | 3.29 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:22 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827391727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.2827391727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.4129299003 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 333369773 ps |
| CPU time | 3.41 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:22 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129299003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.4129299003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.1879032196 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 231458967 ps |
| CPU time | 3.51 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:22 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879032196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.1879032196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.3347903081 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 184858719 ps |
| CPU time | 3.29 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:22 AM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347903081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.3347903081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.3795575511 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 185756599 ps |
| CPU time | 2.65 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:22 AM UTC 24 |
| Peak memory | 253264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795575511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.3795575511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.236306999 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 49342198 ps |
| CPU time | 2.65 seconds |
| Started | Sep 04 08:42:50 AM UTC 24 |
| Finished | Sep 04 08:42:54 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236306999 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.236306999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.2585378021 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1260856699 ps |
| CPU time | 14.52 seconds |
| Started | Sep 04 08:42:45 AM UTC 24 |
| Finished | Sep 04 08:43:02 AM UTC 24 |
| Peak memory | 251364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585378021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.2585378021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.2134069277 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 2190428257 ps |
| CPU time | 21.54 seconds |
| Started | Sep 04 08:42:43 AM UTC 24 |
| Finished | Sep 04 08:43:06 AM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134069277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.2134069277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.3609738152 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 259067302 ps |
| CPU time | 4.36 seconds |
| Started | Sep 04 08:42:43 AM UTC 24 |
| Finished | Sep 04 08:42:49 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609738152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.3609738152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.2235681952 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 454272024 ps |
| CPU time | 5.57 seconds |
| Started | Sep 04 08:42:50 AM UTC 24 |
| Finished | Sep 04 08:42:57 AM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235681952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.2235681952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.1867028860 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 10043338070 ps |
| CPU time | 46.89 seconds |
| Started | Sep 04 08:42:50 AM UTC 24 |
| Finished | Sep 04 08:43:39 AM UTC 24 |
| Peak memory | 253584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867028860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.1867028860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.1200992889 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 221350295 ps |
| CPU time | 5.03 seconds |
| Started | Sep 04 08:42:43 AM UTC 24 |
| Finished | Sep 04 08:42:49 AM UTC 24 |
| Peak memory | 251060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200992889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1200992889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.1927816054 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 802865647 ps |
| CPU time | 24.06 seconds |
| Started | Sep 04 08:42:43 AM UTC 24 |
| Finished | Sep 04 08:43:09 AM UTC 24 |
| Peak memory | 257344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927816054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.1927816054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.2383994389 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 323936642 ps |
| CPU time | 12.43 seconds |
| Started | Sep 04 08:42:41 AM UTC 24 |
| Finished | Sep 04 08:42:55 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383994389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.2383994389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.3007474473 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 338438598 ps |
| CPU time | 9.86 seconds |
| Started | Sep 04 08:42:50 AM UTC 24 |
| Finished | Sep 04 08:43:02 AM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007474473 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.3007474473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.3589795218 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 323118541 ps |
| CPU time | 4.26 seconds |
| Started | Sep 04 08:42:50 AM UTC 24 |
| Finished | Sep 04 08:42:56 AM UTC 24 |
| Peak memory | 257308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589795218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.3589795218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.4045036132 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 1686930542 ps |
| CPU time | 4.3 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045036132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.4045036132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.908190460 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 239075660 ps |
| CPU time | 3.45 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:22 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908190460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.908190460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.2057100577 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 176399567 ps |
| CPU time | 3.31 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:22 AM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057100577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.2057100577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.2480739711 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 290056990 ps |
| CPU time | 4.9 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:24 AM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480739711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.2480739711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.1862501082 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 372467511 ps |
| CPU time | 4.73 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:24 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862501082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.1862501082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.2340376552 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 147251475 ps |
| CPU time | 3.08 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:22 AM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340376552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.2340376552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.1006537234 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 122702436 ps |
| CPU time | 3.83 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006537234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1006537234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.2701877389 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 179493782 ps |
| CPU time | 2.83 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:22 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701877389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.2701877389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.3090284087 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 506517531 ps |
| CPU time | 4.08 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090284087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.3090284087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.1683644202 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 601422680 ps |
| CPU time | 4.92 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:24 AM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683644202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.1683644202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.4151818831 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 173559646 ps |
| CPU time | 2.79 seconds |
| Started | Sep 04 08:42:59 AM UTC 24 |
| Finished | Sep 04 08:43:03 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151818831 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.4151818831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.2928928793 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5216401271 ps |
| CPU time | 32.46 seconds |
| Started | Sep 04 08:42:53 AM UTC 24 |
| Finished | Sep 04 08:43:27 AM UTC 24 |
| Peak memory | 255480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928928793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.2928928793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.3831727267 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 3892422421 ps |
| CPU time | 29.84 seconds |
| Started | Sep 04 08:42:53 AM UTC 24 |
| Finished | Sep 04 08:43:25 AM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831727267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.3831727267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.508260180 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 936440546 ps |
| CPU time | 33.86 seconds |
| Started | Sep 04 08:42:53 AM UTC 24 |
| Finished | Sep 04 08:43:29 AM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508260180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.508260180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.1164825256 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 285861772 ps |
| CPU time | 5.11 seconds |
| Started | Sep 04 08:42:51 AM UTC 24 |
| Finished | Sep 04 08:42:58 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164825256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.1164825256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.3582161420 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 6340177933 ps |
| CPU time | 14.3 seconds |
| Started | Sep 04 08:42:56 AM UTC 24 |
| Finished | Sep 04 08:43:11 AM UTC 24 |
| Peak memory | 253312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582161420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.3582161420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.2796529590 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 865080340 ps |
| CPU time | 11.02 seconds |
| Started | Sep 04 08:42:56 AM UTC 24 |
| Finished | Sep 04 08:43:08 AM UTC 24 |
| Peak memory | 251132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796529590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.2796529590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.775755545 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 319087831 ps |
| CPU time | 17.23 seconds |
| Started | Sep 04 08:42:51 AM UTC 24 |
| Finished | Sep 04 08:43:10 AM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775755545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.775755545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.3990246627 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 362054256 ps |
| CPU time | 13.58 seconds |
| Started | Sep 04 08:42:51 AM UTC 24 |
| Finished | Sep 04 08:43:07 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990246627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.3990246627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.2600805960 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 415853592 ps |
| CPU time | 4.37 seconds |
| Started | Sep 04 08:42:56 AM UTC 24 |
| Finished | Sep 04 08:43:01 AM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600805960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.2600805960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.1597170617 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 112023327 ps |
| CPU time | 5.78 seconds |
| Started | Sep 04 08:42:50 AM UTC 24 |
| Finished | Sep 04 08:42:58 AM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597170617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.1597170617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.2503741488 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 2305886551 ps |
| CPU time | 72.88 seconds |
| Started | Sep 04 08:42:58 AM UTC 24 |
| Finished | Sep 04 08:44:13 AM UTC 24 |
| Peak memory | 257728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503741488 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.2503741488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.1105470832 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 5114644233 ps |
| CPU time | 64.48 seconds |
| Started | Sep 04 08:42:58 AM UTC 24 |
| Finished | Sep 04 08:44:05 AM UTC 24 |
| Peak memory | 257596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1105470832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.otp_ctrl_stress_all_with_rand_reset.1105470832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.4199156475 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1529814171 ps |
| CPU time | 29.52 seconds |
| Started | Sep 04 08:42:56 AM UTC 24 |
| Finished | Sep 04 08:43:27 AM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199156475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.4199156475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.1971543958 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 320933196 ps |
| CPU time | 4.55 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:24 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971543958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1971543958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.254976777 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 475779371 ps |
| CPU time | 4.55 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:24 AM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254976777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.254976777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.784954045 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 297597376 ps |
| CPU time | 3.65 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 253268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784954045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.784954045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.3947953257 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 265790169 ps |
| CPU time | 5.27 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:25 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947953257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.3947953257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.2777618547 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 403456945 ps |
| CPU time | 3.57 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777618547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.2777618547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.2568779395 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 176821831 ps |
| CPU time | 3.61 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568779395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2568779395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.769406113 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 613173314 ps |
| CPU time | 4.81 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:24 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769406113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.769406113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.625895621 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 2277078238 ps |
| CPU time | 4.53 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:24 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625895621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.625895621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.2559801760 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 167107579 ps |
| CPU time | 2.63 seconds |
| Started | Sep 04 08:43:04 AM UTC 24 |
| Finished | Sep 04 08:43:08 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559801760 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2559801760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.3407978873 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 5928546517 ps |
| CPU time | 34.12 seconds |
| Started | Sep 04 08:43:01 AM UTC 24 |
| Finished | Sep 04 08:43:37 AM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407978873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3407978873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.4257547517 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 10503640372 ps |
| CPU time | 30.32 seconds |
| Started | Sep 04 08:43:01 AM UTC 24 |
| Finished | Sep 04 08:43:33 AM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257547517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.4257547517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.3244949680 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 4917413929 ps |
| CPU time | 26.3 seconds |
| Started | Sep 04 08:43:01 AM UTC 24 |
| Finished | Sep 04 08:43:29 AM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244949680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.3244949680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.2182655078 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2309904703 ps |
| CPU time | 5.7 seconds |
| Started | Sep 04 08:42:59 AM UTC 24 |
| Finished | Sep 04 08:43:06 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182655078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.2182655078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.1688332147 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1486937365 ps |
| CPU time | 10.82 seconds |
| Started | Sep 04 08:43:01 AM UTC 24 |
| Finished | Sep 04 08:43:13 AM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688332147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.1688332147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.2922101896 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 4322387471 ps |
| CPU time | 48.13 seconds |
| Started | Sep 04 08:43:04 AM UTC 24 |
| Finished | Sep 04 08:43:54 AM UTC 24 |
| Peak memory | 253316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922101896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.2922101896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.777535688 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 186871893 ps |
| CPU time | 3.92 seconds |
| Started | Sep 04 08:42:59 AM UTC 24 |
| Finished | Sep 04 08:43:04 AM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777535688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.777535688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.584435922 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 5835871522 ps |
| CPU time | 17.11 seconds |
| Started | Sep 04 08:42:59 AM UTC 24 |
| Finished | Sep 04 08:43:17 AM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584435922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.584435922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.669950186 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 3394530496 ps |
| CPU time | 7.76 seconds |
| Started | Sep 04 08:43:04 AM UTC 24 |
| Finished | Sep 04 08:43:13 AM UTC 24 |
| Peak memory | 251340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669950186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.669950186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.574558374 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 392509574 ps |
| CPU time | 4.38 seconds |
| Started | Sep 04 08:42:59 AM UTC 24 |
| Finished | Sep 04 08:43:04 AM UTC 24 |
| Peak memory | 257440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574558374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.574558374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.3218309208 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 18893713373 ps |
| CPU time | 127.66 seconds |
| Started | Sep 04 08:43:04 AM UTC 24 |
| Finished | Sep 04 08:45:14 AM UTC 24 |
| Peak memory | 270104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218309208 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.3218309208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.1209132623 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 19142296368 ps |
| CPU time | 100.64 seconds |
| Started | Sep 04 08:43:04 AM UTC 24 |
| Finished | Sep 04 08:44:47 AM UTC 24 |
| Peak memory | 267796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1209132623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.otp_ctrl_stress_all_with_rand_reset.1209132623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.3911647447 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 559072335 ps |
| CPU time | 14.09 seconds |
| Started | Sep 04 08:43:04 AM UTC 24 |
| Finished | Sep 04 08:43:19 AM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911647447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.3911647447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.2335160361 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 474427021 ps |
| CPU time | 3.88 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335160361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.2335160361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.3881753503 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 336400166 ps |
| CPU time | 4.31 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:24 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881753503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.3881753503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.1137987207 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 180934486 ps |
| CPU time | 3.71 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137987207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.1137987207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.2937543465 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 154451694 ps |
| CPU time | 3.12 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937543465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.2937543465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.3154702348 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 1569558435 ps |
| CPU time | 3.83 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154702348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.3154702348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.1373392066 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 116641306 ps |
| CPU time | 3.15 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373392066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.1373392066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.493259727 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 400779459 ps |
| CPU time | 4.11 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:24 AM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493259727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.493259727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.3134908821 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 97592801 ps |
| CPU time | 2.88 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134908821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.3134908821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.793854653 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 132315579 ps |
| CPU time | 3.64 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:23 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793854653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.793854653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.2294029747 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 251639237 ps |
| CPU time | 2.95 seconds |
| Started | Sep 04 08:43:13 AM UTC 24 |
| Finished | Sep 04 08:43:18 AM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294029747 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.2294029747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.647869480 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 715120004 ps |
| CPU time | 13.46 seconds |
| Started | Sep 04 08:43:09 AM UTC 24 |
| Finished | Sep 04 08:43:24 AM UTC 24 |
| Peak memory | 250672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647869480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.647869480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.533416692 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 1094291627 ps |
| CPU time | 15.26 seconds |
| Started | Sep 04 08:43:07 AM UTC 24 |
| Finished | Sep 04 08:43:24 AM UTC 24 |
| Peak memory | 253412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533416692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.533416692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.2475465919 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 287947480 ps |
| CPU time | 7.18 seconds |
| Started | Sep 04 08:43:07 AM UTC 24 |
| Finished | Sep 04 08:43:16 AM UTC 24 |
| Peak memory | 253372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475465919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.2475465919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.3238892420 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 126158831 ps |
| CPU time | 4.37 seconds |
| Started | Sep 04 08:43:07 AM UTC 24 |
| Finished | Sep 04 08:43:13 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238892420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.3238892420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.316785198 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 6007503155 ps |
| CPU time | 36.76 seconds |
| Started | Sep 04 08:43:09 AM UTC 24 |
| Finished | Sep 04 08:43:48 AM UTC 24 |
| Peak memory | 271988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316785198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.316785198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.1998367640 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 386630836 ps |
| CPU time | 13.92 seconds |
| Started | Sep 04 08:43:09 AM UTC 24 |
| Finished | Sep 04 08:43:25 AM UTC 24 |
| Peak memory | 250692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998367640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.1998367640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.647908437 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 976994576 ps |
| CPU time | 11.93 seconds |
| Started | Sep 04 08:43:07 AM UTC 24 |
| Finished | Sep 04 08:43:20 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647908437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.647908437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.4068039136 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1787926739 ps |
| CPU time | 20.41 seconds |
| Started | Sep 04 08:43:07 AM UTC 24 |
| Finished | Sep 04 08:43:29 AM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068039136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.4068039136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.1279601863 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 256210187 ps |
| CPU time | 7.41 seconds |
| Started | Sep 04 08:43:09 AM UTC 24 |
| Finished | Sep 04 08:43:18 AM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279601863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.1279601863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.3171599227 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 504595727 ps |
| CPU time | 8.42 seconds |
| Started | Sep 04 08:43:07 AM UTC 24 |
| Finished | Sep 04 08:43:17 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171599227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.3171599227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.1592829676 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 6253905188 ps |
| CPU time | 23.62 seconds |
| Started | Sep 04 08:43:13 AM UTC 24 |
| Finished | Sep 04 08:43:38 AM UTC 24 |
| Peak memory | 251520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592829676 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.1592829676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.500987223 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 2086939592 ps |
| CPU time | 13.28 seconds |
| Started | Sep 04 08:43:13 AM UTC 24 |
| Finished | Sep 04 08:43:28 AM UTC 24 |
| Peak memory | 257488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500987223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.500987223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.2879142089 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 1562917641 ps |
| CPU time | 5.05 seconds |
| Started | Sep 04 08:49:18 AM UTC 24 |
| Finished | Sep 04 08:49:25 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879142089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2879142089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.1387515959 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 469778949 ps |
| CPU time | 3.87 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:33 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387515959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.1387515959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.1366871983 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 113781477 ps |
| CPU time | 3.51 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:33 AM UTC 24 |
| Peak memory | 250988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366871983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.1366871983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.2884073544 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 1933256866 ps |
| CPU time | 3.9 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:33 AM UTC 24 |
| Peak memory | 250944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884073544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.2884073544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.396043103 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 419855200 ps |
| CPU time | 4.23 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:33 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396043103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.396043103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.901025009 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 364480350 ps |
| CPU time | 3.91 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:33 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901025009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.901025009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.2632459369 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 137883523 ps |
| CPU time | 3.1 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:32 AM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632459369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.2632459369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.2504847899 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 302765411 ps |
| CPU time | 4.96 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:34 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504847899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.2504847899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.2115168907 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 151026461 ps |
| CPU time | 4.51 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:34 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115168907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.2115168907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.1138216504 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 516083086 ps |
| CPU time | 5.51 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:35 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138216504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.1138216504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.1455833366 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1088577576 ps |
| CPU time | 2.99 seconds |
| Started | Sep 04 08:43:22 AM UTC 24 |
| Finished | Sep 04 08:43:26 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455833366 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.1455833366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.3304677842 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 3272884334 ps |
| CPU time | 26.74 seconds |
| Started | Sep 04 08:43:18 AM UTC 24 |
| Finished | Sep 04 08:43:46 AM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304677842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.3304677842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.4081153001 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1857980780 ps |
| CPU time | 16.3 seconds |
| Started | Sep 04 08:43:18 AM UTC 24 |
| Finished | Sep 04 08:43:35 AM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081153001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.4081153001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.292660231 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 5022780287 ps |
| CPU time | 38.12 seconds |
| Started | Sep 04 08:43:17 AM UTC 24 |
| Finished | Sep 04 08:43:57 AM UTC 24 |
| Peak memory | 253740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292660231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.292660231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.2756328787 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 7000411390 ps |
| CPU time | 13.86 seconds |
| Started | Sep 04 08:43:20 AM UTC 24 |
| Finished | Sep 04 08:43:35 AM UTC 24 |
| Peak memory | 257784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756328787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.2756328787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.1430684639 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 2474044176 ps |
| CPU time | 11.56 seconds |
| Started | Sep 04 08:43:20 AM UTC 24 |
| Finished | Sep 04 08:43:33 AM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430684639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.1430684639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.2256253510 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2277222146 ps |
| CPU time | 14.72 seconds |
| Started | Sep 04 08:43:16 AM UTC 24 |
| Finished | Sep 04 08:43:32 AM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256253510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.2256253510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.736949341 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 8798733855 ps |
| CPU time | 22.06 seconds |
| Started | Sep 04 08:43:16 AM UTC 24 |
| Finished | Sep 04 08:43:39 AM UTC 24 |
| Peak memory | 257424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736949341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.736949341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.1907861107 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 539446655 ps |
| CPU time | 9.43 seconds |
| Started | Sep 04 08:43:20 AM UTC 24 |
| Finished | Sep 04 08:43:31 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907861107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.1907861107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.3316277637 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 254837580 ps |
| CPU time | 5.32 seconds |
| Started | Sep 04 08:43:13 AM UTC 24 |
| Finished | Sep 04 08:43:20 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316277637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.3316277637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.4014844220 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 16448476434 ps |
| CPU time | 155.21 seconds |
| Started | Sep 04 08:43:22 AM UTC 24 |
| Finished | Sep 04 08:46:00 AM UTC 24 |
| Peak memory | 267804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014844220 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.4014844220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.3766103196 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2569922635 ps |
| CPU time | 25.46 seconds |
| Started | Sep 04 08:43:20 AM UTC 24 |
| Finished | Sep 04 08:43:47 AM UTC 24 |
| Peak memory | 251092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766103196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.3766103196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.808607004 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 1930620322 ps |
| CPU time | 4.41 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:34 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808607004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.808607004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.428002026 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 282690512 ps |
| CPU time | 3.17 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:33 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428002026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.428002026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.1863436154 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 587033298 ps |
| CPU time | 3.53 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:33 AM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863436154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.1863436154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.2608227140 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 129818553 ps |
| CPU time | 3.68 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:33 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608227140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.2608227140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.1498739671 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 2012169452 ps |
| CPU time | 3.83 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:34 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498739671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.1498739671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.567871031 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 156758159 ps |
| CPU time | 3.53 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:33 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567871031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.567871031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.2835542388 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 497490982 ps |
| CPU time | 5.19 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:35 AM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835542388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.2835542388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.3416352951 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 136912088 ps |
| CPU time | 4.35 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:34 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416352951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.3416352951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.1470315870 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 1843009670 ps |
| CPU time | 3.68 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:33 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470315870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.1470315870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.36608788 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 398463964 ps |
| CPU time | 4.42 seconds |
| Started | Sep 04 08:49:28 AM UTC 24 |
| Finished | Sep 04 08:49:34 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36608788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.36608788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.1623041478 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 591158146 ps |
| CPU time | 2.79 seconds |
| Started | Sep 04 08:43:32 AM UTC 24 |
| Finished | Sep 04 08:43:36 AM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623041478 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.1623041478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.55709941 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2540570725 ps |
| CPU time | 19.77 seconds |
| Started | Sep 04 08:43:31 AM UTC 24 |
| Finished | Sep 04 08:43:53 AM UTC 24 |
| Peak memory | 253716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55709941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.55709941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.1146718594 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 430354475 ps |
| CPU time | 12.92 seconds |
| Started | Sep 04 08:43:31 AM UTC 24 |
| Finished | Sep 04 08:43:46 AM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146718594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.1146718594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.3636726380 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 298601440 ps |
| CPU time | 8.49 seconds |
| Started | Sep 04 08:43:25 AM UTC 24 |
| Finished | Sep 04 08:43:35 AM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636726380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3636726380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.2112707165 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 307522528 ps |
| CPU time | 4.16 seconds |
| Started | Sep 04 08:43:23 AM UTC 24 |
| Finished | Sep 04 08:43:29 AM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112707165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.2112707165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.1631927473 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1621805673 ps |
| CPU time | 13.35 seconds |
| Started | Sep 04 08:43:31 AM UTC 24 |
| Finished | Sep 04 08:43:46 AM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631927473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.1631927473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.860361587 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1305277189 ps |
| CPU time | 24.36 seconds |
| Started | Sep 04 08:43:32 AM UTC 24 |
| Finished | Sep 04 08:43:57 AM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860361587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.860361587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.2653117592 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 1455719272 ps |
| CPU time | 10.99 seconds |
| Started | Sep 04 08:43:25 AM UTC 24 |
| Finished | Sep 04 08:43:37 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653117592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.2653117592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.2571955046 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 3447891576 ps |
| CPU time | 25.49 seconds |
| Started | Sep 04 08:43:25 AM UTC 24 |
| Finished | Sep 04 08:43:52 AM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571955046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.2571955046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.1694905347 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 206950828 ps |
| CPU time | 6.66 seconds |
| Started | Sep 04 08:43:32 AM UTC 24 |
| Finished | Sep 04 08:43:39 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694905347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.1694905347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.219389252 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1076784960 ps |
| CPU time | 9 seconds |
| Started | Sep 04 08:43:23 AM UTC 24 |
| Finished | Sep 04 08:43:33 AM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219389252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.219389252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.1703550997 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 96293238810 ps |
| CPU time | 184.01 seconds |
| Started | Sep 04 08:43:32 AM UTC 24 |
| Finished | Sep 04 08:46:39 AM UTC 24 |
| Peak memory | 267708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703550997 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.1703550997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.2911518103 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 26105459790 ps |
| CPU time | 43.57 seconds |
| Started | Sep 04 08:43:32 AM UTC 24 |
| Finished | Sep 04 08:44:17 AM UTC 24 |
| Peak memory | 257496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911518103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.2911518103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.1373515876 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 452526751 ps |
| CPU time | 3.59 seconds |
| Started | Sep 04 08:49:29 AM UTC 24 |
| Finished | Sep 04 08:49:33 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373515876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.1373515876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.1877554875 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 141367221 ps |
| CPU time | 3.87 seconds |
| Started | Sep 04 08:49:29 AM UTC 24 |
| Finished | Sep 04 08:49:34 AM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877554875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.1877554875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.3378813966 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 417696460 ps |
| CPU time | 4.1 seconds |
| Started | Sep 04 08:49:29 AM UTC 24 |
| Finished | Sep 04 08:49:34 AM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378813966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.3378813966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.242862439 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 241213214 ps |
| CPU time | 3.82 seconds |
| Started | Sep 04 08:49:29 AM UTC 24 |
| Finished | Sep 04 08:49:34 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242862439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.242862439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.3431742920 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 297370117 ps |
| CPU time | 4.38 seconds |
| Started | Sep 04 08:49:29 AM UTC 24 |
| Finished | Sep 04 08:49:34 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431742920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.3431742920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.351192487 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 575174511 ps |
| CPU time | 3.66 seconds |
| Started | Sep 04 08:49:29 AM UTC 24 |
| Finished | Sep 04 08:49:34 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351192487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.351192487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.3865172756 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 210044896 ps |
| CPU time | 4.47 seconds |
| Started | Sep 04 08:49:29 AM UTC 24 |
| Finished | Sep 04 08:49:35 AM UTC 24 |
| Peak memory | 251432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865172756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.3865172756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.578370507 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 605288156 ps |
| CPU time | 3.76 seconds |
| Started | Sep 04 08:49:29 AM UTC 24 |
| Finished | Sep 04 08:49:34 AM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578370507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.578370507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.314214846 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 1246422788 ps |
| CPU time | 5.06 seconds |
| Started | Sep 04 08:49:29 AM UTC 24 |
| Finished | Sep 04 08:49:35 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314214846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.314214846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.397339983 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 663126688 ps |
| CPU time | 2.61 seconds |
| Started | Sep 04 08:39:30 AM UTC 24 |
| Finished | Sep 04 08:39:34 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397339983 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.397339983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.4030211179 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1519366385 ps |
| CPU time | 19.88 seconds |
| Started | Sep 04 08:39:23 AM UTC 24 |
| Finished | Sep 04 08:39:44 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030211179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.4030211179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.2880248920 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 944425364 ps |
| CPU time | 14.62 seconds |
| Started | Sep 04 08:39:26 AM UTC 24 |
| Finished | Sep 04 08:39:42 AM UTC 24 |
| Peak memory | 253116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880248920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.2880248920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.3261153265 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1025014850 ps |
| CPU time | 19.15 seconds |
| Started | Sep 04 08:39:25 AM UTC 24 |
| Finished | Sep 04 08:39:45 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261153265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.3261153265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.1065616613 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1448417754 ps |
| CPU time | 14.1 seconds |
| Started | Sep 04 08:39:25 AM UTC 24 |
| Finished | Sep 04 08:39:40 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065616613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.1065616613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.2199973865 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 729118157 ps |
| CPU time | 26.38 seconds |
| Started | Sep 04 08:39:26 AM UTC 24 |
| Finished | Sep 04 08:39:54 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199973865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.2199973865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.1190768665 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 5115533419 ps |
| CPU time | 20.1 seconds |
| Started | Sep 04 08:39:26 AM UTC 24 |
| Finished | Sep 04 08:39:48 AM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190768665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.1190768665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.2221454561 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 2595713765 ps |
| CPU time | 25.92 seconds |
| Started | Sep 04 08:39:24 AM UTC 24 |
| Finished | Sep 04 08:39:52 AM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221454561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.2221454561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.1995502891 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 215984543 ps |
| CPU time | 5.55 seconds |
| Started | Sep 04 08:39:26 AM UTC 24 |
| Finished | Sep 04 08:39:33 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995502891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.1995502891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.505523931 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 479501351 ps |
| CPU time | 6.67 seconds |
| Started | Sep 04 08:39:21 AM UTC 24 |
| Finished | Sep 04 08:39:29 AM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505523931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.505523931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.2122210248 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1790030738 ps |
| CPU time | 23.81 seconds |
| Started | Sep 04 08:39:28 AM UTC 24 |
| Finished | Sep 04 08:39:53 AM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122210248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.2122210248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.3450186492 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 324389183 ps |
| CPU time | 5.45 seconds |
| Started | Sep 04 08:43:45 AM UTC 24 |
| Finished | Sep 04 08:43:51 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450186492 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.3450186492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.866041478 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 807896449 ps |
| CPU time | 25.26 seconds |
| Started | Sep 04 08:43:35 AM UTC 24 |
| Finished | Sep 04 08:44:02 AM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866041478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.866041478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.2901689889 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2039541919 ps |
| CPU time | 15.06 seconds |
| Started | Sep 04 08:43:34 AM UTC 24 |
| Finished | Sep 04 08:43:50 AM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901689889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.2901689889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.1746535375 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2113433496 ps |
| CPU time | 32.08 seconds |
| Started | Sep 04 08:43:37 AM UTC 24 |
| Finished | Sep 04 08:44:10 AM UTC 24 |
| Peak memory | 255392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746535375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.1746535375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.986149876 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 2098206209 ps |
| CPU time | 21.17 seconds |
| Started | Sep 04 08:43:37 AM UTC 24 |
| Finished | Sep 04 08:43:59 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986149876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.986149876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.3074125184 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1578762864 ps |
| CPU time | 5.82 seconds |
| Started | Sep 04 08:43:34 AM UTC 24 |
| Finished | Sep 04 08:43:40 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074125184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.3074125184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.1605264410 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 11723962639 ps |
| CPU time | 35.17 seconds |
| Started | Sep 04 08:43:32 AM UTC 24 |
| Finished | Sep 04 08:44:09 AM UTC 24 |
| Peak memory | 257688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605264410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.1605264410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.2239277151 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 405289682 ps |
| CPU time | 5.86 seconds |
| Started | Sep 04 08:43:37 AM UTC 24 |
| Finished | Sep 04 08:43:44 AM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239277151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.2239277151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.972641506 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 404052233 ps |
| CPU time | 6.22 seconds |
| Started | Sep 04 08:43:32 AM UTC 24 |
| Finished | Sep 04 08:43:39 AM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972641506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.972641506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.2587067909 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 193964580 ps |
| CPU time | 4.21 seconds |
| Started | Sep 04 08:43:45 AM UTC 24 |
| Finished | Sep 04 08:43:50 AM UTC 24 |
| Peak memory | 253148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587067909 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.2587067909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.2859446020 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 9040762341 ps |
| CPU time | 77.8 seconds |
| Started | Sep 04 08:43:45 AM UTC 24 |
| Finished | Sep 04 08:45:04 AM UTC 24 |
| Peak memory | 270252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2859446020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.otp_ctrl_stress_all_with_rand_reset.2859446020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.4081644386 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 836545013 ps |
| CPU time | 19.51 seconds |
| Started | Sep 04 08:43:37 AM UTC 24 |
| Finished | Sep 04 08:43:58 AM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081644386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.4081644386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.423430873 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 205412531 ps |
| CPU time | 3.06 seconds |
| Started | Sep 04 08:43:49 AM UTC 24 |
| Finished | Sep 04 08:43:53 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423430873 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.423430873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.3980768008 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 11517367251 ps |
| CPU time | 29.35 seconds |
| Started | Sep 04 08:43:45 AM UTC 24 |
| Finished | Sep 04 08:44:16 AM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980768008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.3980768008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.349578365 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 3790273364 ps |
| CPU time | 18.46 seconds |
| Started | Sep 04 08:43:45 AM UTC 24 |
| Finished | Sep 04 08:44:05 AM UTC 24 |
| Peak memory | 253472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349578365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.349578365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.1738419352 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 782298036 ps |
| CPU time | 13.85 seconds |
| Started | Sep 04 08:43:45 AM UTC 24 |
| Finished | Sep 04 08:44:00 AM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738419352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.1738419352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.981764003 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 668349131 ps |
| CPU time | 4.28 seconds |
| Started | Sep 04 08:43:45 AM UTC 24 |
| Finished | Sep 04 08:43:50 AM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981764003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.981764003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.1344243252 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1481918450 ps |
| CPU time | 18.28 seconds |
| Started | Sep 04 08:43:45 AM UTC 24 |
| Finished | Sep 04 08:44:05 AM UTC 24 |
| Peak memory | 257224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344243252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.1344243252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.2280449815 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 4346517639 ps |
| CPU time | 22.91 seconds |
| Started | Sep 04 08:43:45 AM UTC 24 |
| Finished | Sep 04 08:44:09 AM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280449815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.2280449815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.1860489174 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 726301781 ps |
| CPU time | 16.8 seconds |
| Started | Sep 04 08:43:45 AM UTC 24 |
| Finished | Sep 04 08:44:03 AM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860489174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.1860489174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.3704564102 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 456477768 ps |
| CPU time | 8.46 seconds |
| Started | Sep 04 08:43:45 AM UTC 24 |
| Finished | Sep 04 08:43:55 AM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704564102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.3704564102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.3733870988 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 315863934 ps |
| CPU time | 8.01 seconds |
| Started | Sep 04 08:43:47 AM UTC 24 |
| Finished | Sep 04 08:43:56 AM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733870988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.3733870988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.2563123628 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 1678763729 ps |
| CPU time | 11.51 seconds |
| Started | Sep 04 08:43:45 AM UTC 24 |
| Finished | Sep 04 08:43:58 AM UTC 24 |
| Peak memory | 257560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563123628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.2563123628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.3937408067 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 2388319809 ps |
| CPU time | 47.24 seconds |
| Started | Sep 04 08:43:47 AM UTC 24 |
| Finished | Sep 04 08:44:36 AM UTC 24 |
| Peak memory | 257464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937408067 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.3937408067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.82940387 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 1084487418 ps |
| CPU time | 8.92 seconds |
| Started | Sep 04 08:43:47 AM UTC 24 |
| Finished | Sep 04 08:43:57 AM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82940387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.82940387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.898122551 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 118024227 ps |
| CPU time | 2.28 seconds |
| Started | Sep 04 08:43:59 AM UTC 24 |
| Finished | Sep 04 08:44:03 AM UTC 24 |
| Peak memory | 250888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898122551 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.898122551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.1040749888 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 571043104 ps |
| CPU time | 16.8 seconds |
| Started | Sep 04 08:43:53 AM UTC 24 |
| Finished | Sep 04 08:44:11 AM UTC 24 |
| Peak memory | 251576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040749888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.1040749888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.545326409 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 1449390224 ps |
| CPU time | 15.37 seconds |
| Started | Sep 04 08:43:53 AM UTC 24 |
| Finished | Sep 04 08:44:10 AM UTC 24 |
| Peak memory | 251332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545326409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.545326409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.3462335050 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 213571270 ps |
| CPU time | 5.45 seconds |
| Started | Sep 04 08:43:51 AM UTC 24 |
| Finished | Sep 04 08:43:57 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462335050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.3462335050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.3699142411 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 793164717 ps |
| CPU time | 22.25 seconds |
| Started | Sep 04 08:43:53 AM UTC 24 |
| Finished | Sep 04 08:44:17 AM UTC 24 |
| Peak memory | 255736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699142411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.3699142411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.2738367997 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 1702060391 ps |
| CPU time | 31.38 seconds |
| Started | Sep 04 08:43:57 AM UTC 24 |
| Finished | Sep 04 08:44:30 AM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738367997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.2738367997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.3598158089 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 345168538 ps |
| CPU time | 7.56 seconds |
| Started | Sep 04 08:43:51 AM UTC 24 |
| Finished | Sep 04 08:43:59 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598158089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.3598158089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.1411839646 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 899799193 ps |
| CPU time | 15.03 seconds |
| Started | Sep 04 08:43:51 AM UTC 24 |
| Finished | Sep 04 08:44:07 AM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411839646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.1411839646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.4081986781 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 132251427 ps |
| CPU time | 4.24 seconds |
| Started | Sep 04 08:43:57 AM UTC 24 |
| Finished | Sep 04 08:44:03 AM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081986781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.4081986781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.3976567663 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 1558306811 ps |
| CPU time | 9.41 seconds |
| Started | Sep 04 08:43:49 AM UTC 24 |
| Finished | Sep 04 08:43:59 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976567663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.3976567663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.2958724651 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 8240118790 ps |
| CPU time | 94.91 seconds |
| Started | Sep 04 08:43:57 AM UTC 24 |
| Finished | Sep 04 08:45:34 AM UTC 24 |
| Peak memory | 259776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958724651 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.2958724651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.3604078808 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 2373270550 ps |
| CPU time | 69.25 seconds |
| Started | Sep 04 08:43:57 AM UTC 24 |
| Finished | Sep 04 08:45:08 AM UTC 24 |
| Peak memory | 271896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3604078808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.otp_ctrl_stress_all_with_rand_reset.3604078808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.1835886115 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 3810070740 ps |
| CPU time | 24.96 seconds |
| Started | Sep 04 08:43:57 AM UTC 24 |
| Finished | Sep 04 08:44:24 AM UTC 24 |
| Peak memory | 251328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835886115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.1835886115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.849775932 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 47396136 ps |
| CPU time | 2.4 seconds |
| Started | Sep 04 08:44:04 AM UTC 24 |
| Finished | Sep 04 08:44:08 AM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849775932 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.849775932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.228025221 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 624026172 ps |
| CPU time | 15.64 seconds |
| Started | Sep 04 08:44:02 AM UTC 24 |
| Finished | Sep 04 08:44:19 AM UTC 24 |
| Peak memory | 253396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228025221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.228025221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.971371908 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 180021872 ps |
| CPU time | 8.65 seconds |
| Started | Sep 04 08:44:00 AM UTC 24 |
| Finished | Sep 04 08:44:09 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971371908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.971371908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.305096899 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 719162710 ps |
| CPU time | 11.42 seconds |
| Started | Sep 04 08:44:00 AM UTC 24 |
| Finished | Sep 04 08:44:12 AM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305096899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.305096899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.2036013134 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 434093123 ps |
| CPU time | 5.29 seconds |
| Started | Sep 04 08:44:00 AM UTC 24 |
| Finished | Sep 04 08:44:06 AM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036013134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.2036013134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.4180097909 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 139531855 ps |
| CPU time | 4.88 seconds |
| Started | Sep 04 08:44:02 AM UTC 24 |
| Finished | Sep 04 08:44:08 AM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180097909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.4180097909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.3933096576 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 1980277195 ps |
| CPU time | 22.11 seconds |
| Started | Sep 04 08:44:02 AM UTC 24 |
| Finished | Sep 04 08:44:25 AM UTC 24 |
| Peak memory | 253368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933096576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.3933096576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.4061799675 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 136579110 ps |
| CPU time | 7.19 seconds |
| Started | Sep 04 08:44:00 AM UTC 24 |
| Finished | Sep 04 08:44:08 AM UTC 24 |
| Peak memory | 251112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061799675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.4061799675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.2123841933 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 518856751 ps |
| CPU time | 18.16 seconds |
| Started | Sep 04 08:44:00 AM UTC 24 |
| Finished | Sep 04 08:44:19 AM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123841933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.2123841933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.2135240330 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 243859775 ps |
| CPU time | 5.5 seconds |
| Started | Sep 04 08:44:02 AM UTC 24 |
| Finished | Sep 04 08:44:08 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135240330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.2135240330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.372193467 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 135494399 ps |
| CPU time | 5.53 seconds |
| Started | Sep 04 08:43:59 AM UTC 24 |
| Finished | Sep 04 08:44:06 AM UTC 24 |
| Peak memory | 250924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372193467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.372193467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.4029454895 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 14213865091 ps |
| CPU time | 187.82 seconds |
| Started | Sep 04 08:44:04 AM UTC 24 |
| Finished | Sep 04 08:47:15 AM UTC 24 |
| Peak memory | 290288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029454895 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.4029454895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.373431339 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1189341372 ps |
| CPU time | 17.51 seconds |
| Started | Sep 04 08:44:04 AM UTC 24 |
| Finished | Sep 04 08:44:23 AM UTC 24 |
| Peak memory | 251668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373431339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.373431339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.3482281712 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 51904750 ps |
| CPU time | 2.37 seconds |
| Started | Sep 04 08:44:14 AM UTC 24 |
| Finished | Sep 04 08:44:17 AM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482281712 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.3482281712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.3719521805 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 932927733 ps |
| CPU time | 10.17 seconds |
| Started | Sep 04 08:44:10 AM UTC 24 |
| Finished | Sep 04 08:44:21 AM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719521805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.3719521805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.1422281789 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 910551537 ps |
| CPU time | 13.99 seconds |
| Started | Sep 04 08:44:10 AM UTC 24 |
| Finished | Sep 04 08:44:25 AM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422281789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.1422281789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.311334509 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 704601555 ps |
| CPU time | 11.43 seconds |
| Started | Sep 04 08:44:10 AM UTC 24 |
| Finished | Sep 04 08:44:22 AM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311334509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.311334509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.1011495164 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 261413718 ps |
| CPU time | 4.08 seconds |
| Started | Sep 04 08:44:10 AM UTC 24 |
| Finished | Sep 04 08:44:15 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011495164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.1011495164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.2387822994 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 5370788019 ps |
| CPU time | 19.31 seconds |
| Started | Sep 04 08:44:10 AM UTC 24 |
| Finished | Sep 04 08:44:30 AM UTC 24 |
| Peak memory | 253392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387822994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.2387822994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.3530053268 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 1173204423 ps |
| CPU time | 28.06 seconds |
| Started | Sep 04 08:44:10 AM UTC 24 |
| Finished | Sep 04 08:44:39 AM UTC 24 |
| Peak memory | 251496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530053268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.3530053268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.3441775115 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 300865575 ps |
| CPU time | 6.11 seconds |
| Started | Sep 04 08:44:10 AM UTC 24 |
| Finished | Sep 04 08:44:17 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441775115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.3441775115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.3739468237 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 625543024 ps |
| CPU time | 10.72 seconds |
| Started | Sep 04 08:44:10 AM UTC 24 |
| Finished | Sep 04 08:44:21 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739468237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.3739468237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.2602095815 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 561258623 ps |
| CPU time | 11.86 seconds |
| Started | Sep 04 08:44:10 AM UTC 24 |
| Finished | Sep 04 08:44:23 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602095815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2602095815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.1465184046 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 245406221 ps |
| CPU time | 4.45 seconds |
| Started | Sep 04 08:44:10 AM UTC 24 |
| Finished | Sep 04 08:44:15 AM UTC 24 |
| Peak memory | 257372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465184046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1465184046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.781815612 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 16201263295 ps |
| CPU time | 145.04 seconds |
| Started | Sep 04 08:44:14 AM UTC 24 |
| Finished | Sep 04 08:46:41 AM UTC 24 |
| Peak memory | 267720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781815612 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.781815612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.2279144073 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3479288867 ps |
| CPU time | 63.68 seconds |
| Started | Sep 04 08:44:14 AM UTC 24 |
| Finished | Sep 04 08:45:19 AM UTC 24 |
| Peak memory | 259760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2279144073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.otp_ctrl_stress_all_with_rand_reset.2279144073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.169955365 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 1302560278 ps |
| CPU time | 24.73 seconds |
| Started | Sep 04 08:44:10 AM UTC 24 |
| Finished | Sep 04 08:44:36 AM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169955365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.169955365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.2253794264 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 52642139 ps |
| CPU time | 2.14 seconds |
| Started | Sep 04 08:44:19 AM UTC 24 |
| Finished | Sep 04 08:44:22 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253794264 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.2253794264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.2255896091 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 567644225 ps |
| CPU time | 22.35 seconds |
| Started | Sep 04 08:44:18 AM UTC 24 |
| Finished | Sep 04 08:44:42 AM UTC 24 |
| Peak memory | 251108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255896091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.2255896091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.834204985 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 164032531 ps |
| CPU time | 5.37 seconds |
| Started | Sep 04 08:44:18 AM UTC 24 |
| Finished | Sep 04 08:44:25 AM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834204985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.834204985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.826768582 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 490164477 ps |
| CPU time | 4.94 seconds |
| Started | Sep 04 08:44:14 AM UTC 24 |
| Finished | Sep 04 08:44:20 AM UTC 24 |
| Peak memory | 253532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826768582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.826768582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.2124922286 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 2265193892 ps |
| CPU time | 19.49 seconds |
| Started | Sep 04 08:44:19 AM UTC 24 |
| Finished | Sep 04 08:44:39 AM UTC 24 |
| Peak memory | 253492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124922286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.2124922286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.1815551258 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 473767762 ps |
| CPU time | 12.08 seconds |
| Started | Sep 04 08:44:19 AM UTC 24 |
| Finished | Sep 04 08:44:32 AM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815551258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1815551258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.1160136536 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 539214491 ps |
| CPU time | 8.3 seconds |
| Started | Sep 04 08:44:14 AM UTC 24 |
| Finished | Sep 04 08:44:23 AM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160136536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.1160136536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.3288985023 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 4516989429 ps |
| CPU time | 14.15 seconds |
| Started | Sep 04 08:44:14 AM UTC 24 |
| Finished | Sep 04 08:44:29 AM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288985023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.3288985023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.2685944492 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 269724395 ps |
| CPU time | 4.66 seconds |
| Started | Sep 04 08:44:19 AM UTC 24 |
| Finished | Sep 04 08:44:24 AM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685944492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.2685944492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.3589741110 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 383234113 ps |
| CPU time | 7.09 seconds |
| Started | Sep 04 08:44:14 AM UTC 24 |
| Finished | Sep 04 08:44:22 AM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589741110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.3589741110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.652122851 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 26925917549 ps |
| CPU time | 147.8 seconds |
| Started | Sep 04 08:44:19 AM UTC 24 |
| Finished | Sep 04 08:46:49 AM UTC 24 |
| Peak memory | 269756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652122851 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.652122851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.1709623451 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3336607970 ps |
| CPU time | 35.14 seconds |
| Started | Sep 04 08:44:19 AM UTC 24 |
| Finished | Sep 04 08:44:55 AM UTC 24 |
| Peak memory | 257584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1709623451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.otp_ctrl_stress_all_with_rand_reset.1709623451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.69836 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 1051026196 ps |
| CPU time | 19.32 seconds |
| Started | Sep 04 08:44:19 AM UTC 24 |
| Finished | Sep 04 08:44:39 AM UTC 24 |
| Peak memory | 251580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ =otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.69836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.1518188917 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 180916350 ps |
| CPU time | 2.95 seconds |
| Started | Sep 04 08:44:27 AM UTC 24 |
| Finished | Sep 04 08:44:31 AM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518188917 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.1518188917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.1706673345 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 6582787791 ps |
| CPU time | 16.29 seconds |
| Started | Sep 04 08:44:23 AM UTC 24 |
| Finished | Sep 04 08:44:40 AM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706673345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.1706673345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.2449295570 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 426850120 ps |
| CPU time | 14.47 seconds |
| Started | Sep 04 08:44:22 AM UTC 24 |
| Finished | Sep 04 08:44:38 AM UTC 24 |
| Peak memory | 251364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449295570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.2449295570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.2855012640 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 794695638 ps |
| CPU time | 13.04 seconds |
| Started | Sep 04 08:44:22 AM UTC 24 |
| Finished | Sep 04 08:44:37 AM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855012640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.2855012640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.3886529112 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 107256030 ps |
| CPU time | 4.09 seconds |
| Started | Sep 04 08:44:22 AM UTC 24 |
| Finished | Sep 04 08:44:28 AM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886529112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.3886529112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.775003131 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 573218748 ps |
| CPU time | 7.32 seconds |
| Started | Sep 04 08:44:23 AM UTC 24 |
| Finished | Sep 04 08:44:31 AM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775003131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.775003131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.758125714 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 1551664793 ps |
| CPU time | 33.88 seconds |
| Started | Sep 04 08:44:23 AM UTC 24 |
| Finished | Sep 04 08:44:58 AM UTC 24 |
| Peak memory | 253332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758125714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.758125714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.3160324702 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1596654334 ps |
| CPU time | 17.62 seconds |
| Started | Sep 04 08:44:22 AM UTC 24 |
| Finished | Sep 04 08:44:41 AM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160324702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.3160324702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.2908675892 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 1665076811 ps |
| CPU time | 22.34 seconds |
| Started | Sep 04 08:44:22 AM UTC 24 |
| Finished | Sep 04 08:44:46 AM UTC 24 |
| Peak memory | 257364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908675892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.2908675892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.3337472781 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 707001552 ps |
| CPU time | 10.99 seconds |
| Started | Sep 04 08:44:24 AM UTC 24 |
| Finished | Sep 04 08:44:36 AM UTC 24 |
| Peak memory | 251052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337472781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.3337472781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.1294641511 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 437786578 ps |
| CPU time | 7.07 seconds |
| Started | Sep 04 08:44:19 AM UTC 24 |
| Finished | Sep 04 08:44:27 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294641511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.1294641511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.3313056197 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 440954065 ps |
| CPU time | 11.53 seconds |
| Started | Sep 04 08:44:24 AM UTC 24 |
| Finished | Sep 04 08:44:37 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313056197 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.3313056197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.989142882 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 1660255175 ps |
| CPU time | 22.48 seconds |
| Started | Sep 04 08:44:24 AM UTC 24 |
| Finished | Sep 04 08:44:48 AM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989142882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.989142882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.1222358164 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 180087222 ps |
| CPU time | 2.36 seconds |
| Started | Sep 04 08:44:38 AM UTC 24 |
| Finished | Sep 04 08:44:41 AM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222358164 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.1222358164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.1202209558 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 1882757227 ps |
| CPU time | 17.01 seconds |
| Started | Sep 04 08:44:31 AM UTC 24 |
| Finished | Sep 04 08:44:50 AM UTC 24 |
| Peak memory | 253400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202209558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.1202209558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.525508808 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 3651674714 ps |
| CPU time | 29.61 seconds |
| Started | Sep 04 08:44:31 AM UTC 24 |
| Finished | Sep 04 08:45:02 AM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525508808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.525508808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.1467932021 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 1138499964 ps |
| CPU time | 13.23 seconds |
| Started | Sep 04 08:44:27 AM UTC 24 |
| Finished | Sep 04 08:44:41 AM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467932021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.1467932021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.1381148113 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 115706260 ps |
| CPU time | 3.36 seconds |
| Started | Sep 04 08:44:27 AM UTC 24 |
| Finished | Sep 04 08:44:31 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381148113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.1381148113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.1987429488 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 930495934 ps |
| CPU time | 9.14 seconds |
| Started | Sep 04 08:44:31 AM UTC 24 |
| Finished | Sep 04 08:44:42 AM UTC 24 |
| Peak memory | 251584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987429488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.1987429488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.3671656712 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1195040427 ps |
| CPU time | 26.4 seconds |
| Started | Sep 04 08:44:31 AM UTC 24 |
| Finished | Sep 04 08:44:59 AM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671656712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.3671656712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.147083899 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 884942004 ps |
| CPU time | 10.6 seconds |
| Started | Sep 04 08:44:27 AM UTC 24 |
| Finished | Sep 04 08:44:39 AM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147083899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.147083899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.2474418767 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 10690853156 ps |
| CPU time | 35.18 seconds |
| Started | Sep 04 08:44:27 AM UTC 24 |
| Finished | Sep 04 08:45:04 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474418767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.2474418767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.3478220315 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 204608040 ps |
| CPU time | 8.99 seconds |
| Started | Sep 04 08:44:31 AM UTC 24 |
| Finished | Sep 04 08:44:42 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478220315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.3478220315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.787835978 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1551222549 ps |
| CPU time | 6.29 seconds |
| Started | Sep 04 08:44:27 AM UTC 24 |
| Finished | Sep 04 08:44:34 AM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787835978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.787835978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.4034205855 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 7346515625 ps |
| CPU time | 53.91 seconds |
| Started | Sep 04 08:44:32 AM UTC 24 |
| Finished | Sep 04 08:45:27 AM UTC 24 |
| Peak memory | 255676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034205855 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.4034205855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.247642704 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 4685725121 ps |
| CPU time | 45.87 seconds |
| Started | Sep 04 08:44:31 AM UTC 24 |
| Finished | Sep 04 08:45:19 AM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247642704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.247642704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.1416508925 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 205236492 ps |
| CPU time | 3.76 seconds |
| Started | Sep 04 08:44:41 AM UTC 24 |
| Finished | Sep 04 08:44:46 AM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416508925 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.1416508925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.2928939914 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 454144061 ps |
| CPU time | 8.78 seconds |
| Started | Sep 04 08:44:38 AM UTC 24 |
| Finished | Sep 04 08:44:48 AM UTC 24 |
| Peak memory | 253688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928939914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.2928939914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.876120859 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 1541977816 ps |
| CPU time | 20.11 seconds |
| Started | Sep 04 08:44:38 AM UTC 24 |
| Finished | Sep 04 08:44:59 AM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876120859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.876120859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.2523028594 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 7437744440 ps |
| CPU time | 45.85 seconds |
| Started | Sep 04 08:44:38 AM UTC 24 |
| Finished | Sep 04 08:45:25 AM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523028594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.2523028594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.3591012197 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 1435198736 ps |
| CPU time | 4.03 seconds |
| Started | Sep 04 08:44:38 AM UTC 24 |
| Finished | Sep 04 08:44:43 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591012197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.3591012197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.3305944590 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 2994717518 ps |
| CPU time | 16.46 seconds |
| Started | Sep 04 08:44:38 AM UTC 24 |
| Finished | Sep 04 08:44:56 AM UTC 24 |
| Peak memory | 257740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305944590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.3305944590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.1429987966 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 7374504174 ps |
| CPU time | 22.23 seconds |
| Started | Sep 04 08:44:38 AM UTC 24 |
| Finished | Sep 04 08:45:02 AM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429987966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.1429987966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.2497318215 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 279522115 ps |
| CPU time | 12.58 seconds |
| Started | Sep 04 08:44:38 AM UTC 24 |
| Finished | Sep 04 08:44:52 AM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497318215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.2497318215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.4074844882 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 4494255964 ps |
| CPU time | 17.16 seconds |
| Started | Sep 04 08:44:38 AM UTC 24 |
| Finished | Sep 04 08:44:56 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074844882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.4074844882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.4052628626 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 3464667458 ps |
| CPU time | 9.68 seconds |
| Started | Sep 04 08:44:38 AM UTC 24 |
| Finished | Sep 04 08:44:49 AM UTC 24 |
| Peak memory | 253392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052628626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.4052628626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.2214481764 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 1441438721 ps |
| CPU time | 7.55 seconds |
| Started | Sep 04 08:44:38 AM UTC 24 |
| Finished | Sep 04 08:44:46 AM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214481764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.2214481764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.164211085 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 18770298202 ps |
| CPU time | 121.69 seconds |
| Started | Sep 04 08:44:41 AM UTC 24 |
| Finished | Sep 04 08:46:46 AM UTC 24 |
| Peak memory | 267756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164211085 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.164211085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.120466416 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1840999792 ps |
| CPU time | 18.08 seconds |
| Started | Sep 04 08:44:41 AM UTC 24 |
| Finished | Sep 04 08:45:01 AM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120466416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.120466416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.1602607072 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 116154385 ps |
| CPU time | 2.85 seconds |
| Started | Sep 04 08:44:53 AM UTC 24 |
| Finished | Sep 04 08:44:57 AM UTC 24 |
| Peak memory | 251132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602607072 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.1602607072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.4152422146 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 1141570791 ps |
| CPU time | 16.95 seconds |
| Started | Sep 04 08:44:44 AM UTC 24 |
| Finished | Sep 04 08:45:03 AM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152422146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.4152422146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.2127395865 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 316457249 ps |
| CPU time | 16.8 seconds |
| Started | Sep 04 08:44:44 AM UTC 24 |
| Finished | Sep 04 08:45:03 AM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127395865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.2127395865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.1126438144 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 662853943 ps |
| CPU time | 20.67 seconds |
| Started | Sep 04 08:44:44 AM UTC 24 |
| Finished | Sep 04 08:45:06 AM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126438144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.1126438144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.2759435660 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 1982103680 ps |
| CPU time | 5.26 seconds |
| Started | Sep 04 08:44:41 AM UTC 24 |
| Finished | Sep 04 08:44:48 AM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759435660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.2759435660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.1579674104 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 1538831298 ps |
| CPU time | 12.82 seconds |
| Started | Sep 04 08:44:44 AM UTC 24 |
| Finished | Sep 04 08:44:59 AM UTC 24 |
| Peak memory | 253332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579674104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.1579674104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.2309423425 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 5757346978 ps |
| CPU time | 18.73 seconds |
| Started | Sep 04 08:44:45 AM UTC 24 |
| Finished | Sep 04 08:45:05 AM UTC 24 |
| Peak memory | 253624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309423425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.2309423425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.4057635299 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 1133271044 ps |
| CPU time | 25.75 seconds |
| Started | Sep 04 08:44:44 AM UTC 24 |
| Finished | Sep 04 08:45:12 AM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057635299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.4057635299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.2859590187 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 591285583 ps |
| CPU time | 16.98 seconds |
| Started | Sep 04 08:44:42 AM UTC 24 |
| Finished | Sep 04 08:45:00 AM UTC 24 |
| Peak memory | 257496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859590187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.2859590187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.1219896871 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 126147393 ps |
| CPU time | 5.54 seconds |
| Started | Sep 04 08:44:45 AM UTC 24 |
| Finished | Sep 04 08:44:51 AM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219896871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.1219896871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.2522669728 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 143496240 ps |
| CPU time | 6.03 seconds |
| Started | Sep 04 08:44:41 AM UTC 24 |
| Finished | Sep 04 08:44:49 AM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522669728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.2522669728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.3331488322 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3042239566 ps |
| CPU time | 15.92 seconds |
| Started | Sep 04 08:44:46 AM UTC 24 |
| Finished | Sep 04 08:45:03 AM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331488322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.3331488322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.517536387 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 50975384 ps |
| CPU time | 2.77 seconds |
| Started | Sep 04 08:39:46 AM UTC 24 |
| Finished | Sep 04 08:39:50 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517536387 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.517536387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.2469065154 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 735240143 ps |
| CPU time | 17.64 seconds |
| Started | Sep 04 08:39:32 AM UTC 24 |
| Finished | Sep 04 08:39:51 AM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469065154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.2469065154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.2247532134 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 6185906404 ps |
| CPU time | 38.15 seconds |
| Started | Sep 04 08:39:36 AM UTC 24 |
| Finished | Sep 04 08:40:15 AM UTC 24 |
| Peak memory | 253348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247532134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.2247532134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.1666081045 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 1840124609 ps |
| CPU time | 25.54 seconds |
| Started | Sep 04 08:39:36 AM UTC 24 |
| Finished | Sep 04 08:40:03 AM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666081045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.1666081045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.1934038466 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 142507856 ps |
| CPU time | 5.32 seconds |
| Started | Sep 04 08:39:30 AM UTC 24 |
| Finished | Sep 04 08:39:37 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934038466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.1934038466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.280464080 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1957287822 ps |
| CPU time | 14.8 seconds |
| Started | Sep 04 08:39:38 AM UTC 24 |
| Finished | Sep 04 08:39:54 AM UTC 24 |
| Peak memory | 255516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280464080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.280464080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.2100437820 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 7849878136 ps |
| CPU time | 38.11 seconds |
| Started | Sep 04 08:39:38 AM UTC 24 |
| Finished | Sep 04 08:40:17 AM UTC 24 |
| Peak memory | 253404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100437820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.2100437820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.2793302829 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 857920308 ps |
| CPU time | 16.89 seconds |
| Started | Sep 04 08:39:34 AM UTC 24 |
| Finished | Sep 04 08:39:52 AM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793302829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2793302829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.1409172369 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 165231825579 ps |
| CPU time | 249.7 seconds |
| Started | Sep 04 08:39:43 AM UTC 24 |
| Finished | Sep 04 08:43:56 AM UTC 24 |
| Peak memory | 289916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409172369 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.1409172369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.2967373883 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 1042538004 ps |
| CPU time | 7.36 seconds |
| Started | Sep 04 08:39:30 AM UTC 24 |
| Finished | Sep 04 08:39:39 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967373883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.2967373883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.1469157781 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 446421158 ps |
| CPU time | 16.1 seconds |
| Started | Sep 04 08:39:39 AM UTC 24 |
| Finished | Sep 04 08:39:56 AM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469157781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.1469157781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.3663898857 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 593769823 ps |
| CPU time | 2.69 seconds |
| Started | Sep 04 08:44:57 AM UTC 24 |
| Finished | Sep 04 08:45:00 AM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663898857 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.3663898857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.1478285100 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 4161627805 ps |
| CPU time | 26.82 seconds |
| Started | Sep 04 08:44:53 AM UTC 24 |
| Finished | Sep 04 08:45:21 AM UTC 24 |
| Peak memory | 255472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478285100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1478285100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.360711198 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 956018786 ps |
| CPU time | 27.56 seconds |
| Started | Sep 04 08:44:53 AM UTC 24 |
| Finished | Sep 04 08:45:22 AM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360711198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.360711198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.3145769184 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 816103234 ps |
| CPU time | 12.84 seconds |
| Started | Sep 04 08:44:53 AM UTC 24 |
| Finished | Sep 04 08:45:07 AM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145769184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.3145769184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.3358100228 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 124888738 ps |
| CPU time | 5.27 seconds |
| Started | Sep 04 08:44:53 AM UTC 24 |
| Finished | Sep 04 08:44:59 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358100228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.3358100228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.2003729330 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 3626362179 ps |
| CPU time | 10.4 seconds |
| Started | Sep 04 08:44:53 AM UTC 24 |
| Finished | Sep 04 08:45:05 AM UTC 24 |
| Peak memory | 253408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003729330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.2003729330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.1871056957 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 3465871561 ps |
| CPU time | 25.49 seconds |
| Started | Sep 04 08:44:53 AM UTC 24 |
| Finished | Sep 04 08:45:20 AM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871056957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.1871056957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.1522303752 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 617679270 ps |
| CPU time | 8.48 seconds |
| Started | Sep 04 08:44:53 AM UTC 24 |
| Finished | Sep 04 08:45:02 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522303752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.1522303752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.2509158999 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 1218739249 ps |
| CPU time | 16.05 seconds |
| Started | Sep 04 08:44:53 AM UTC 24 |
| Finished | Sep 04 08:45:10 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509158999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.2509158999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.2252398042 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 1084997115 ps |
| CPU time | 8.52 seconds |
| Started | Sep 04 08:44:53 AM UTC 24 |
| Finished | Sep 04 08:45:03 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252398042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.2252398042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.797550067 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 206338576 ps |
| CPU time | 7.2 seconds |
| Started | Sep 04 08:44:53 AM UTC 24 |
| Finished | Sep 04 08:45:01 AM UTC 24 |
| Peak memory | 257888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797550067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.797550067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.3134825290 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 1513128878 ps |
| CPU time | 26.09 seconds |
| Started | Sep 04 08:44:53 AM UTC 24 |
| Finished | Sep 04 08:45:21 AM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134825290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.3134825290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.3615584492 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 602523057 ps |
| CPU time | 3.34 seconds |
| Started | Sep 04 08:45:06 AM UTC 24 |
| Finished | Sep 04 08:45:11 AM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615584492 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.3615584492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.4186521611 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 12543973598 ps |
| CPU time | 32.93 seconds |
| Started | Sep 04 08:45:03 AM UTC 24 |
| Finished | Sep 04 08:45:38 AM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186521611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.4186521611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.274564439 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 284144618 ps |
| CPU time | 13.23 seconds |
| Started | Sep 04 08:45:03 AM UTC 24 |
| Finished | Sep 04 08:45:18 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274564439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.274564439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.3112495794 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4523990792 ps |
| CPU time | 17.25 seconds |
| Started | Sep 04 08:45:03 AM UTC 24 |
| Finished | Sep 04 08:45:22 AM UTC 24 |
| Peak memory | 257128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112495794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.3112495794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.4190073479 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 1524811187 ps |
| CPU time | 5.49 seconds |
| Started | Sep 04 08:44:58 AM UTC 24 |
| Finished | Sep 04 08:45:05 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190073479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.4190073479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.3798086933 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 2391840613 ps |
| CPU time | 7.13 seconds |
| Started | Sep 04 08:45:03 AM UTC 24 |
| Finished | Sep 04 08:45:12 AM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798086933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.3798086933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.883729629 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 796992640 ps |
| CPU time | 11.24 seconds |
| Started | Sep 04 08:45:03 AM UTC 24 |
| Finished | Sep 04 08:45:16 AM UTC 24 |
| Peak memory | 251608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883729629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.883729629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.1506994243 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 1039152669 ps |
| CPU time | 14.11 seconds |
| Started | Sep 04 08:45:03 AM UTC 24 |
| Finished | Sep 04 08:45:18 AM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506994243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.1506994243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.1500909152 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1289219426 ps |
| CPU time | 15.22 seconds |
| Started | Sep 04 08:44:58 AM UTC 24 |
| Finished | Sep 04 08:45:15 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500909152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.1500909152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.240750278 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 2098791392 ps |
| CPU time | 5.78 seconds |
| Started | Sep 04 08:45:03 AM UTC 24 |
| Finished | Sep 04 08:45:10 AM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240750278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.240750278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.1958293733 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 198723580 ps |
| CPU time | 5.56 seconds |
| Started | Sep 04 08:44:58 AM UTC 24 |
| Finished | Sep 04 08:45:05 AM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958293733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.1958293733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.25582205 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 10103208459 ps |
| CPU time | 87.32 seconds |
| Started | Sep 04 08:45:04 AM UTC 24 |
| Finished | Sep 04 08:46:33 AM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25582205 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.25582205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.3458740781 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 1805409983 ps |
| CPU time | 21.89 seconds |
| Started | Sep 04 08:45:03 AM UTC 24 |
| Finished | Sep 04 08:45:27 AM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458740781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.3458740781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.3608041831 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 50839268 ps |
| CPU time | 1.77 seconds |
| Started | Sep 04 08:45:12 AM UTC 24 |
| Finished | Sep 04 08:45:15 AM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608041831 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.3608041831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.1461301830 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 2419310867 ps |
| CPU time | 11.27 seconds |
| Started | Sep 04 08:45:07 AM UTC 24 |
| Finished | Sep 04 08:45:19 AM UTC 24 |
| Peak memory | 251268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461301830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.1461301830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.2836160686 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 1001232016 ps |
| CPU time | 29.29 seconds |
| Started | Sep 04 08:45:07 AM UTC 24 |
| Finished | Sep 04 08:45:37 AM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836160686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.2836160686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.266108034 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 12429030953 ps |
| CPU time | 22.56 seconds |
| Started | Sep 04 08:45:07 AM UTC 24 |
| Finished | Sep 04 08:45:31 AM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266108034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.266108034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.3775377109 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 514934089 ps |
| CPU time | 4.84 seconds |
| Started | Sep 04 08:45:07 AM UTC 24 |
| Finished | Sep 04 08:45:12 AM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775377109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.3775377109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.1538783460 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 528616984 ps |
| CPU time | 13.3 seconds |
| Started | Sep 04 08:45:07 AM UTC 24 |
| Finished | Sep 04 08:45:21 AM UTC 24 |
| Peak memory | 251392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538783460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.1538783460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.1962912368 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 663237164 ps |
| CPU time | 11.01 seconds |
| Started | Sep 04 08:45:07 AM UTC 24 |
| Finished | Sep 04 08:45:19 AM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962912368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.1962912368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.4279635464 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 230053754 ps |
| CPU time | 6.38 seconds |
| Started | Sep 04 08:45:07 AM UTC 24 |
| Finished | Sep 04 08:45:14 AM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279635464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.4279635464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.118419381 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 5460281027 ps |
| CPU time | 17.1 seconds |
| Started | Sep 04 08:45:07 AM UTC 24 |
| Finished | Sep 04 08:45:25 AM UTC 24 |
| Peak memory | 257428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118419381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.118419381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.2365110106 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 287022441 ps |
| CPU time | 9.75 seconds |
| Started | Sep 04 08:45:07 AM UTC 24 |
| Finished | Sep 04 08:45:18 AM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365110106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.2365110106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.2364781786 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 170736492 ps |
| CPU time | 3.83 seconds |
| Started | Sep 04 08:45:07 AM UTC 24 |
| Finished | Sep 04 08:45:11 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364781786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.2364781786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.1352068994 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 13052441308 ps |
| CPU time | 204.78 seconds |
| Started | Sep 04 08:45:09 AM UTC 24 |
| Finished | Sep 04 08:48:37 AM UTC 24 |
| Peak memory | 257728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352068994 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.1352068994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.1922417809 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 332242995 ps |
| CPU time | 10.84 seconds |
| Started | Sep 04 08:45:09 AM UTC 24 |
| Finished | Sep 04 08:45:21 AM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922417809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.1922417809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.1684246332 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 303143783 ps |
| CPU time | 3.32 seconds |
| Started | Sep 04 08:45:20 AM UTC 24 |
| Finished | Sep 04 08:45:24 AM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684246332 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.1684246332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.1907541398 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 311689100 ps |
| CPU time | 9.66 seconds |
| Started | Sep 04 08:45:15 AM UTC 24 |
| Finished | Sep 04 08:45:26 AM UTC 24 |
| Peak memory | 257784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907541398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.1907541398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.3551340106 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 1742605381 ps |
| CPU time | 14.25 seconds |
| Started | Sep 04 08:45:15 AM UTC 24 |
| Finished | Sep 04 08:45:31 AM UTC 24 |
| Peak memory | 251132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551340106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.3551340106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.3240261699 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 964531822 ps |
| CPU time | 14.95 seconds |
| Started | Sep 04 08:45:15 AM UTC 24 |
| Finished | Sep 04 08:45:31 AM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240261699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.3240261699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.3805821483 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 463620968 ps |
| CPU time | 5.03 seconds |
| Started | Sep 04 08:45:12 AM UTC 24 |
| Finished | Sep 04 08:45:18 AM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805821483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.3805821483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.3760737761 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 1879856238 ps |
| CPU time | 19.86 seconds |
| Started | Sep 04 08:45:15 AM UTC 24 |
| Finished | Sep 04 08:45:36 AM UTC 24 |
| Peak memory | 255480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760737761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.3760737761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.1992077243 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 15563866952 ps |
| CPU time | 28.37 seconds |
| Started | Sep 04 08:45:15 AM UTC 24 |
| Finished | Sep 04 08:45:45 AM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992077243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.1992077243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.721112006 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 1521834694 ps |
| CPU time | 12.63 seconds |
| Started | Sep 04 08:45:12 AM UTC 24 |
| Finished | Sep 04 08:45:26 AM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721112006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.721112006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.1421894750 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 1538243791 ps |
| CPU time | 21.07 seconds |
| Started | Sep 04 08:45:12 AM UTC 24 |
| Finished | Sep 04 08:45:34 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421894750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.1421894750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.3163826118 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 4501345827 ps |
| CPU time | 10.03 seconds |
| Started | Sep 04 08:45:15 AM UTC 24 |
| Finished | Sep 04 08:45:27 AM UTC 24 |
| Peak memory | 253396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163826118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.3163826118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.4129471142 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 2299022298 ps |
| CPU time | 4.69 seconds |
| Started | Sep 04 08:45:12 AM UTC 24 |
| Finished | Sep 04 08:45:18 AM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129471142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.4129471142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.546616779 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 36260674065 ps |
| CPU time | 243.37 seconds |
| Started | Sep 04 08:45:20 AM UTC 24 |
| Finished | Sep 04 08:49:27 AM UTC 24 |
| Peak memory | 273936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546616779 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.546616779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.3355598639 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 26777691365 ps |
| CPU time | 108.91 seconds |
| Started | Sep 04 08:45:20 AM UTC 24 |
| Finished | Sep 04 08:47:11 AM UTC 24 |
| Peak memory | 257276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3355598639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 43.otp_ctrl_stress_all_with_rand_reset.3355598639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.974728148 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 946243605 ps |
| CPU time | 8.84 seconds |
| Started | Sep 04 08:45:20 AM UTC 24 |
| Finished | Sep 04 08:45:30 AM UTC 24 |
| Peak memory | 251400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974728148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.974728148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.865555420 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 138479708 ps |
| CPU time | 2.57 seconds |
| Started | Sep 04 08:45:25 AM UTC 24 |
| Finished | Sep 04 08:45:29 AM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865555420 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.865555420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.3251128788 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1603051416 ps |
| CPU time | 17.55 seconds |
| Started | Sep 04 08:45:25 AM UTC 24 |
| Finished | Sep 04 08:45:44 AM UTC 24 |
| Peak memory | 248540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251128788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.3251128788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.3705113901 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 861240183 ps |
| CPU time | 9.74 seconds |
| Started | Sep 04 08:45:25 AM UTC 24 |
| Finished | Sep 04 08:45:36 AM UTC 24 |
| Peak memory | 248468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705113901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.3705113901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.1665013810 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 555635649 ps |
| CPU time | 10.93 seconds |
| Started | Sep 04 08:45:25 AM UTC 24 |
| Finished | Sep 04 08:45:37 AM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665013810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.1665013810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.706549095 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 248648407 ps |
| CPU time | 4.09 seconds |
| Started | Sep 04 08:45:20 AM UTC 24 |
| Finished | Sep 04 08:45:25 AM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706549095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.706549095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.589440230 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 30246418498 ps |
| CPU time | 71.52 seconds |
| Started | Sep 04 08:45:25 AM UTC 24 |
| Finished | Sep 04 08:46:38 AM UTC 24 |
| Peak memory | 273912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589440230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.589440230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.4251773039 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 1655885659 ps |
| CPU time | 12.62 seconds |
| Started | Sep 04 08:45:25 AM UTC 24 |
| Finished | Sep 04 08:45:39 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251773039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.4251773039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.1600697698 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1803478301 ps |
| CPU time | 7.61 seconds |
| Started | Sep 04 08:45:20 AM UTC 24 |
| Finished | Sep 04 08:45:29 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600697698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.1600697698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.1030675255 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 7205897862 ps |
| CPU time | 14.88 seconds |
| Started | Sep 04 08:45:20 AM UTC 24 |
| Finished | Sep 04 08:45:36 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030675255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.1030675255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.3918027543 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 132630945 ps |
| CPU time | 4.65 seconds |
| Started | Sep 04 08:45:25 AM UTC 24 |
| Finished | Sep 04 08:45:31 AM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918027543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.3918027543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.1000080453 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 1413833190 ps |
| CPU time | 12.5 seconds |
| Started | Sep 04 08:45:20 AM UTC 24 |
| Finished | Sep 04 08:45:34 AM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000080453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1000080453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2784709481 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 24635590345 ps |
| CPU time | 84.36 seconds |
| Started | Sep 04 08:45:25 AM UTC 24 |
| Finished | Sep 04 08:46:51 AM UTC 24 |
| Peak memory | 267836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2784709481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.otp_ctrl_stress_all_with_rand_reset.2784709481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.1132293924 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 1210180223 ps |
| CPU time | 15.23 seconds |
| Started | Sep 04 08:45:25 AM UTC 24 |
| Finished | Sep 04 08:45:42 AM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132293924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.1132293924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.3925346900 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 55341332 ps |
| CPU time | 2.01 seconds |
| Started | Sep 04 08:45:31 AM UTC 24 |
| Finished | Sep 04 08:45:34 AM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925346900 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.3925346900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.2351936532 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 447996707 ps |
| CPU time | 11.95 seconds |
| Started | Sep 04 08:45:29 AM UTC 24 |
| Finished | Sep 04 08:45:42 AM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351936532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.2351936532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.213396530 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 661409577 ps |
| CPU time | 21.87 seconds |
| Started | Sep 04 08:45:29 AM UTC 24 |
| Finished | Sep 04 08:45:52 AM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213396530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.213396530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.3187779206 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 1340425383 ps |
| CPU time | 19.57 seconds |
| Started | Sep 04 08:45:28 AM UTC 24 |
| Finished | Sep 04 08:45:49 AM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187779206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.3187779206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.2548302678 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 230294107 ps |
| CPU time | 3.59 seconds |
| Started | Sep 04 08:45:25 AM UTC 24 |
| Finished | Sep 04 08:45:30 AM UTC 24 |
| Peak memory | 250704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548302678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.2548302678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.859213297 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 2598624701 ps |
| CPU time | 21.07 seconds |
| Started | Sep 04 08:45:29 AM UTC 24 |
| Finished | Sep 04 08:45:51 AM UTC 24 |
| Peak memory | 257504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859213297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.859213297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.1165386659 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2217643046 ps |
| CPU time | 21.07 seconds |
| Started | Sep 04 08:45:29 AM UTC 24 |
| Finished | Sep 04 08:45:51 AM UTC 24 |
| Peak memory | 257500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165386659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.1165386659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.2479287490 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 224791719 ps |
| CPU time | 5.27 seconds |
| Started | Sep 04 08:45:28 AM UTC 24 |
| Finished | Sep 04 08:45:35 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479287490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.2479287490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.562503916 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 1177580816 ps |
| CPU time | 9.43 seconds |
| Started | Sep 04 08:45:25 AM UTC 24 |
| Finished | Sep 04 08:45:36 AM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562503916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.562503916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.2699827223 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 128822984 ps |
| CPU time | 4.01 seconds |
| Started | Sep 04 08:45:29 AM UTC 24 |
| Finished | Sep 04 08:45:34 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699827223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2699827223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.421239574 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 232812870 ps |
| CPU time | 7.56 seconds |
| Started | Sep 04 08:45:25 AM UTC 24 |
| Finished | Sep 04 08:45:34 AM UTC 24 |
| Peak memory | 250816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421239574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.421239574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.3055282734 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 10312415239 ps |
| CPU time | 78.99 seconds |
| Started | Sep 04 08:45:31 AM UTC 24 |
| Finished | Sep 04 08:46:52 AM UTC 24 |
| Peak memory | 255568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055282734 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.3055282734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.4147796626 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2329983955 ps |
| CPU time | 29.04 seconds |
| Started | Sep 04 08:45:29 AM UTC 24 |
| Finished | Sep 04 08:45:59 AM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147796626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.4147796626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.2733132059 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 153035104 ps |
| CPU time | 2.64 seconds |
| Started | Sep 04 08:45:39 AM UTC 24 |
| Finished | Sep 04 08:45:43 AM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733132059 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.2733132059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.3673656194 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 1326651103 ps |
| CPU time | 12.6 seconds |
| Started | Sep 04 08:45:39 AM UTC 24 |
| Finished | Sep 04 08:45:53 AM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673656194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.3673656194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.3932726873 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 3033492441 ps |
| CPU time | 21.86 seconds |
| Started | Sep 04 08:45:34 AM UTC 24 |
| Finished | Sep 04 08:45:57 AM UTC 24 |
| Peak memory | 253496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932726873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.3932726873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.3303174937 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 2163397802 ps |
| CPU time | 6.41 seconds |
| Started | Sep 04 08:45:34 AM UTC 24 |
| Finished | Sep 04 08:45:41 AM UTC 24 |
| Peak memory | 251708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303174937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.3303174937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.2906449883 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 2011794745 ps |
| CPU time | 5.18 seconds |
| Started | Sep 04 08:45:31 AM UTC 24 |
| Finished | Sep 04 08:45:38 AM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906449883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.2906449883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.135947106 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1062274262 ps |
| CPU time | 10.34 seconds |
| Started | Sep 04 08:45:39 AM UTC 24 |
| Finished | Sep 04 08:45:50 AM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135947106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.135947106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.3286255864 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 2341608869 ps |
| CPU time | 20.03 seconds |
| Started | Sep 04 08:45:39 AM UTC 24 |
| Finished | Sep 04 08:46:00 AM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286255864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.3286255864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.3185231427 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 499709765 ps |
| CPU time | 15.49 seconds |
| Started | Sep 04 08:45:34 AM UTC 24 |
| Finished | Sep 04 08:45:50 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185231427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.3185231427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.3577219823 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 331941502 ps |
| CPU time | 7.47 seconds |
| Started | Sep 04 08:45:34 AM UTC 24 |
| Finished | Sep 04 08:45:42 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577219823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.3577219823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.1208052686 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 881778777 ps |
| CPU time | 7.9 seconds |
| Started | Sep 04 08:45:31 AM UTC 24 |
| Finished | Sep 04 08:45:40 AM UTC 24 |
| Peak memory | 257756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208052686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.1208052686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.1918194400 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 140170741360 ps |
| CPU time | 362.89 seconds |
| Started | Sep 04 08:45:39 AM UTC 24 |
| Finished | Sep 04 08:51:47 AM UTC 24 |
| Peak memory | 356020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918194400 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.1918194400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.1161222036 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 11311459172 ps |
| CPU time | 122.28 seconds |
| Started | Sep 04 08:45:39 AM UTC 24 |
| Finished | Sep 04 08:47:44 AM UTC 24 |
| Peak memory | 267800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1161222036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.otp_ctrl_stress_all_with_rand_reset.1161222036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.399950084 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 624027777 ps |
| CPU time | 13.06 seconds |
| Started | Sep 04 08:45:39 AM UTC 24 |
| Finished | Sep 04 08:45:53 AM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399950084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.399950084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.3494967228 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 100841893 ps |
| CPU time | 3.16 seconds |
| Started | Sep 04 08:45:44 AM UTC 24 |
| Finished | Sep 04 08:45:48 AM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494967228 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.3494967228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.3274382393 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 246254982 ps |
| CPU time | 6.08 seconds |
| Started | Sep 04 08:45:44 AM UTC 24 |
| Finished | Sep 04 08:45:51 AM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274382393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.3274382393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.194378041 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 534790136 ps |
| CPU time | 16.42 seconds |
| Started | Sep 04 08:45:44 AM UTC 24 |
| Finished | Sep 04 08:46:02 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194378041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.194378041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.2404383833 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 1392851049 ps |
| CPU time | 8.87 seconds |
| Started | Sep 04 08:45:40 AM UTC 24 |
| Finished | Sep 04 08:45:49 AM UTC 24 |
| Peak memory | 257400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404383833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.2404383833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.824674989 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 130769357 ps |
| CPU time | 4.07 seconds |
| Started | Sep 04 08:45:44 AM UTC 24 |
| Finished | Sep 04 08:45:49 AM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824674989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.824674989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.303788014 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1301347709 ps |
| CPU time | 28.7 seconds |
| Started | Sep 04 08:45:44 AM UTC 24 |
| Finished | Sep 04 08:46:14 AM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303788014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.303788014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.4157391682 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 494291645 ps |
| CPU time | 9.47 seconds |
| Started | Sep 04 08:45:39 AM UTC 24 |
| Finished | Sep 04 08:45:50 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157391682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.4157391682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.1720184972 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 935266782 ps |
| CPU time | 8.4 seconds |
| Started | Sep 04 08:45:39 AM UTC 24 |
| Finished | Sep 04 08:45:49 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720184972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.1720184972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.1760834926 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 2074687164 ps |
| CPU time | 5.26 seconds |
| Started | Sep 04 08:45:44 AM UTC 24 |
| Finished | Sep 04 08:45:51 AM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760834926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.1760834926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.3886607751 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 218661342 ps |
| CPU time | 4.89 seconds |
| Started | Sep 04 08:45:39 AM UTC 24 |
| Finished | Sep 04 08:45:45 AM UTC 24 |
| Peak memory | 257820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886607751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.3886607751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.2994465710 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 61642105537 ps |
| CPU time | 362.58 seconds |
| Started | Sep 04 08:45:44 AM UTC 24 |
| Finished | Sep 04 08:51:52 AM UTC 24 |
| Peak memory | 306712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994465710 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.2994465710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.2844033991 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 13448952544 ps |
| CPU time | 122.63 seconds |
| Started | Sep 04 08:45:44 AM UTC 24 |
| Finished | Sep 04 08:47:49 AM UTC 24 |
| Peak memory | 274264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2844033991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 47.otp_ctrl_stress_all_with_rand_reset.2844033991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.4056714637 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 3330450063 ps |
| CPU time | 30.91 seconds |
| Started | Sep 04 08:45:44 AM UTC 24 |
| Finished | Sep 04 08:46:16 AM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056714637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.4056714637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.931041775 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 61043044 ps |
| CPU time | 2.89 seconds |
| Started | Sep 04 08:45:57 AM UTC 24 |
| Finished | Sep 04 08:46:01 AM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931041775 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.931041775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.552682147 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 244555933 ps |
| CPU time | 4.29 seconds |
| Started | Sep 04 08:45:52 AM UTC 24 |
| Finished | Sep 04 08:45:57 AM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552682147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.552682147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.4067843264 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 1543570788 ps |
| CPU time | 22.21 seconds |
| Started | Sep 04 08:45:49 AM UTC 24 |
| Finished | Sep 04 08:46:12 AM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067843264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.4067843264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.2353295172 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 2359132235 ps |
| CPU time | 41.29 seconds |
| Started | Sep 04 08:45:48 AM UTC 24 |
| Finished | Sep 04 08:46:31 AM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353295172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.2353295172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.2088049134 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 201564620 ps |
| CPU time | 5.23 seconds |
| Started | Sep 04 08:45:46 AM UTC 24 |
| Finished | Sep 04 08:45:53 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088049134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.2088049134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.3685590253 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 2718365105 ps |
| CPU time | 18.06 seconds |
| Started | Sep 04 08:45:52 AM UTC 24 |
| Finished | Sep 04 08:46:12 AM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685590253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.3685590253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.384685675 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 120490105 ps |
| CPU time | 4.8 seconds |
| Started | Sep 04 08:45:52 AM UTC 24 |
| Finished | Sep 04 08:45:58 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384685675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.384685675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.2368087249 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 3215288141 ps |
| CPU time | 13.04 seconds |
| Started | Sep 04 08:45:47 AM UTC 24 |
| Finished | Sep 04 08:46:01 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368087249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2368087249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.100328470 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 7866251740 ps |
| CPU time | 20.92 seconds |
| Started | Sep 04 08:45:46 AM UTC 24 |
| Finished | Sep 04 08:46:09 AM UTC 24 |
| Peak memory | 253324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100328470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.100328470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.2798391989 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 646542589 ps |
| CPU time | 9.42 seconds |
| Started | Sep 04 08:45:52 AM UTC 24 |
| Finished | Sep 04 08:46:03 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798391989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.2798391989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.3681167902 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 462199008 ps |
| CPU time | 5.73 seconds |
| Started | Sep 04 08:45:44 AM UTC 24 |
| Finished | Sep 04 08:45:51 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681167902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.3681167902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.3098882085 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 194014528246 ps |
| CPU time | 356.68 seconds |
| Started | Sep 04 08:45:52 AM UTC 24 |
| Finished | Sep 04 08:51:54 AM UTC 24 |
| Peak memory | 284120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098882085 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.3098882085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.4077377673 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 14362384477 ps |
| CPU time | 155.38 seconds |
| Started | Sep 04 08:45:52 AM UTC 24 |
| Finished | Sep 04 08:48:31 AM UTC 24 |
| Peak memory | 269908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4077377673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.otp_ctrl_stress_all_with_rand_reset.4077377673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.3681750638 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 562924813 ps |
| CPU time | 5.4 seconds |
| Started | Sep 04 08:45:52 AM UTC 24 |
| Finished | Sep 04 08:45:59 AM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681750638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.3681750638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.394783387 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 183916945 ps |
| CPU time | 2.55 seconds |
| Started | Sep 04 08:46:08 AM UTC 24 |
| Finished | Sep 04 08:46:12 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394783387 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.394783387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.925579551 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 306246880 ps |
| CPU time | 10.48 seconds |
| Started | Sep 04 08:45:57 AM UTC 24 |
| Finished | Sep 04 08:46:09 AM UTC 24 |
| Peak memory | 253752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925579551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.925579551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.1858998432 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 16460495305 ps |
| CPU time | 39.53 seconds |
| Started | Sep 04 08:45:57 AM UTC 24 |
| Finished | Sep 04 08:46:39 AM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858998432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.1858998432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.2176163309 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 418431414 ps |
| CPU time | 11.73 seconds |
| Started | Sep 04 08:45:57 AM UTC 24 |
| Finished | Sep 04 08:46:10 AM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176163309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.2176163309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.3940510840 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 202596676 ps |
| CPU time | 5.02 seconds |
| Started | Sep 04 08:45:57 AM UTC 24 |
| Finished | Sep 04 08:46:03 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940510840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.3940510840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.1806613674 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 936527243 ps |
| CPU time | 11.63 seconds |
| Started | Sep 04 08:45:57 AM UTC 24 |
| Finished | Sep 04 08:46:11 AM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806613674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.1806613674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.1100574995 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 3023740520 ps |
| CPU time | 30.31 seconds |
| Started | Sep 04 08:45:58 AM UTC 24 |
| Finished | Sep 04 08:46:29 AM UTC 24 |
| Peak memory | 257784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100574995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.1100574995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.118388265 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 214505477 ps |
| CPU time | 3.85 seconds |
| Started | Sep 04 08:45:57 AM UTC 24 |
| Finished | Sep 04 08:46:02 AM UTC 24 |
| Peak memory | 251088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118388265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.118388265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.1300816357 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 11004655102 ps |
| CPU time | 28.28 seconds |
| Started | Sep 04 08:45:57 AM UTC 24 |
| Finished | Sep 04 08:46:27 AM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300816357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.1300816357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.2976710469 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 1168434814 ps |
| CPU time | 11.43 seconds |
| Started | Sep 04 08:45:59 AM UTC 24 |
| Finished | Sep 04 08:46:12 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976710469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.2976710469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.3988151721 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 1990438157 ps |
| CPU time | 4.25 seconds |
| Started | Sep 04 08:45:57 AM UTC 24 |
| Finished | Sep 04 08:46:03 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988151721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.3988151721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.3134088854 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 170549051785 ps |
| CPU time | 341.21 seconds |
| Started | Sep 04 08:46:08 AM UTC 24 |
| Finished | Sep 04 08:51:54 AM UTC 24 |
| Peak memory | 300916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134088854 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.3134088854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.1140237016 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 4559366265 ps |
| CPU time | 130.05 seconds |
| Started | Sep 04 08:46:00 AM UTC 24 |
| Finished | Sep 04 08:48:12 AM UTC 24 |
| Peak memory | 274416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1140237016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 49.otp_ctrl_stress_all_with_rand_reset.1140237016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.4138871253 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 6394254843 ps |
| CPU time | 15.54 seconds |
| Started | Sep 04 08:45:59 AM UTC 24 |
| Finished | Sep 04 08:46:16 AM UTC 24 |
| Peak memory | 253744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138871253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.4138871253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.3056075794 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 171567777 ps |
| CPU time | 2.9 seconds |
| Started | Sep 04 08:39:55 AM UTC 24 |
| Finished | Sep 04 08:39:59 AM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056075794 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.3056075794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.2242812725 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 7050133304 ps |
| CPU time | 74.51 seconds |
| Started | Sep 04 08:39:46 AM UTC 24 |
| Finished | Sep 04 08:41:02 AM UTC 24 |
| Peak memory | 257780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242812725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.2242812725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.2830997022 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 449991250 ps |
| CPU time | 14.19 seconds |
| Started | Sep 04 08:39:51 AM UTC 24 |
| Finished | Sep 04 08:40:06 AM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830997022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.2830997022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.3463035717 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 735100380 ps |
| CPU time | 24.49 seconds |
| Started | Sep 04 08:39:51 AM UTC 24 |
| Finished | Sep 04 08:40:16 AM UTC 24 |
| Peak memory | 257372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463035717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.3463035717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.1375923944 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 832547831 ps |
| CPU time | 15.85 seconds |
| Started | Sep 04 08:39:49 AM UTC 24 |
| Finished | Sep 04 08:40:06 AM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375923944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.1375923944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.850610409 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1220330847 ps |
| CPU time | 16.23 seconds |
| Started | Sep 04 08:39:52 AM UTC 24 |
| Finished | Sep 04 08:40:09 AM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850610409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.850610409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.3776494474 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 314446534 ps |
| CPU time | 12.65 seconds |
| Started | Sep 04 08:39:55 AM UTC 24 |
| Finished | Sep 04 08:40:08 AM UTC 24 |
| Peak memory | 257436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776494474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.3776494474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.4086957953 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 235024681 ps |
| CPU time | 6.46 seconds |
| Started | Sep 04 08:39:48 AM UTC 24 |
| Finished | Sep 04 08:39:55 AM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086957953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.4086957953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.1026347967 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 136089113 ps |
| CPU time | 5.48 seconds |
| Started | Sep 04 08:39:55 AM UTC 24 |
| Finished | Sep 04 08:40:01 AM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026347967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.1026347967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.4231606174 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 3228059987 ps |
| CPU time | 6.58 seconds |
| Started | Sep 04 08:39:46 AM UTC 24 |
| Finished | Sep 04 08:39:54 AM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231606174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.4231606174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.531869162 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 1614989345 ps |
| CPU time | 46.52 seconds |
| Started | Sep 04 08:39:55 AM UTC 24 |
| Finished | Sep 04 08:40:43 AM UTC 24 |
| Peak memory | 257648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=531869162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.531869162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.4204241194 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 1868390183 ps |
| CPU time | 19.37 seconds |
| Started | Sep 04 08:39:55 AM UTC 24 |
| Finished | Sep 04 08:40:15 AM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204241194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.4204241194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.2891430588 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 253682970 ps |
| CPU time | 4.46 seconds |
| Started | Sep 04 08:46:08 AM UTC 24 |
| Finished | Sep 04 08:46:14 AM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891430588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.2891430588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.481814584 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 178327226 ps |
| CPU time | 6.52 seconds |
| Started | Sep 04 08:46:08 AM UTC 24 |
| Finished | Sep 04 08:46:16 AM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481814584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.481814584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.2968814700 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 5897898726 ps |
| CPU time | 124.57 seconds |
| Started | Sep 04 08:46:08 AM UTC 24 |
| Finished | Sep 04 08:48:15 AM UTC 24 |
| Peak memory | 257708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2968814700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 50.otp_ctrl_stress_all_with_rand_reset.2968814700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.3522342989 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 313870083 ps |
| CPU time | 5.4 seconds |
| Started | Sep 04 08:46:08 AM UTC 24 |
| Finished | Sep 04 08:46:15 AM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522342989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.3522342989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.2253199160 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 217663346 ps |
| CPU time | 5.81 seconds |
| Started | Sep 04 08:46:08 AM UTC 24 |
| Finished | Sep 04 08:46:15 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253199160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.2253199160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.710944450 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 13721144084 ps |
| CPU time | 68.08 seconds |
| Started | Sep 04 08:46:08 AM UTC 24 |
| Finished | Sep 04 08:47:18 AM UTC 24 |
| Peak memory | 271988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=710944450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.710944450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.959540080 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 305185108 ps |
| CPU time | 4.82 seconds |
| Started | Sep 04 08:46:08 AM UTC 24 |
| Finished | Sep 04 08:46:14 AM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959540080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.959540080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.3438526013 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 192787965 ps |
| CPU time | 6.11 seconds |
| Started | Sep 04 08:46:08 AM UTC 24 |
| Finished | Sep 04 08:46:16 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438526013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.3438526013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.2569085337 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 180351807 ps |
| CPU time | 4.08 seconds |
| Started | Sep 04 08:46:08 AM UTC 24 |
| Finished | Sep 04 08:46:14 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569085337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.2569085337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.3631805513 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 1521312520 ps |
| CPU time | 6.26 seconds |
| Started | Sep 04 08:46:08 AM UTC 24 |
| Finished | Sep 04 08:46:16 AM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631805513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.3631805513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.3160484944 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 19147420218 ps |
| CPU time | 171.62 seconds |
| Started | Sep 04 08:46:10 AM UTC 24 |
| Finished | Sep 04 08:49:05 AM UTC 24 |
| Peak memory | 284188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3160484944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 53.otp_ctrl_stress_all_with_rand_reset.3160484944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.501821841 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 445810306 ps |
| CPU time | 4.94 seconds |
| Started | Sep 04 08:46:10 AM UTC 24 |
| Finished | Sep 04 08:46:16 AM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501821841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.501821841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.3051326190 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 158810626 ps |
| CPU time | 4.03 seconds |
| Started | Sep 04 08:46:12 AM UTC 24 |
| Finished | Sep 04 08:46:18 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051326190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.3051326190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.765200107 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 134514064 ps |
| CPU time | 6.13 seconds |
| Started | Sep 04 08:46:12 AM UTC 24 |
| Finished | Sep 04 08:46:20 AM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765200107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.765200107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.3164732629 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 103379376 ps |
| CPU time | 3.66 seconds |
| Started | Sep 04 08:46:12 AM UTC 24 |
| Finished | Sep 04 08:46:17 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164732629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.3164732629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.520386370 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 621337027 ps |
| CPU time | 7.03 seconds |
| Started | Sep 04 08:46:15 AM UTC 24 |
| Finished | Sep 04 08:46:23 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520386370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.520386370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.1176374729 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 86178926 ps |
| CPU time | 3.95 seconds |
| Started | Sep 04 08:46:15 AM UTC 24 |
| Finished | Sep 04 08:46:20 AM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176374729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.1176374729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.2347647907 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2220448604 ps |
| CPU time | 63.32 seconds |
| Started | Sep 04 08:46:15 AM UTC 24 |
| Finished | Sep 04 08:47:20 AM UTC 24 |
| Peak memory | 257592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2347647907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 56.otp_ctrl_stress_all_with_rand_reset.2347647907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.2869141203 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 855863753 ps |
| CPU time | 4.96 seconds |
| Started | Sep 04 08:46:17 AM UTC 24 |
| Finished | Sep 04 08:46:23 AM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869141203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.2869141203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.2165503009 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 571449458 ps |
| CPU time | 4.97 seconds |
| Started | Sep 04 08:46:17 AM UTC 24 |
| Finished | Sep 04 08:46:23 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165503009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.2165503009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.1038869191 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 703655841 ps |
| CPU time | 12.81 seconds |
| Started | Sep 04 08:46:17 AM UTC 24 |
| Finished | Sep 04 08:46:31 AM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038869191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.1038869191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.303069260 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 97748813132 ps |
| CPU time | 233.15 seconds |
| Started | Sep 04 08:46:17 AM UTC 24 |
| Finished | Sep 04 08:50:14 AM UTC 24 |
| Peak memory | 267892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=303069260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.303069260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.2789192339 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 102712729 ps |
| CPU time | 5.16 seconds |
| Started | Sep 04 08:46:17 AM UTC 24 |
| Finished | Sep 04 08:46:23 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789192339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.2789192339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.3293282904 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 3795775586 ps |
| CPU time | 20.79 seconds |
| Started | Sep 04 08:46:17 AM UTC 24 |
| Finished | Sep 04 08:46:39 AM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293282904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.3293282904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.113585212 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 127237697 ps |
| CPU time | 2.29 seconds |
| Started | Sep 04 08:40:08 AM UTC 24 |
| Finished | Sep 04 08:40:11 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113585212 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.113585212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.3923069829 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 10938070891 ps |
| CPU time | 22.16 seconds |
| Started | Sep 04 08:39:57 AM UTC 24 |
| Finished | Sep 04 08:40:20 AM UTC 24 |
| Peak memory | 253492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923069829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.3923069829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.3282377081 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 139907043 ps |
| CPU time | 4.49 seconds |
| Started | Sep 04 08:40:02 AM UTC 24 |
| Finished | Sep 04 08:40:08 AM UTC 24 |
| Peak memory | 257288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282377081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.3282377081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.997864665 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 315604950 ps |
| CPU time | 19.1 seconds |
| Started | Sep 04 08:40:02 AM UTC 24 |
| Finished | Sep 04 08:40:23 AM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997864665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.997864665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.244926639 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 3622120088 ps |
| CPU time | 34.76 seconds |
| Started | Sep 04 08:40:00 AM UTC 24 |
| Finished | Sep 04 08:40:36 AM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244926639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.244926639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.3307581863 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 146846274 ps |
| CPU time | 6.9 seconds |
| Started | Sep 04 08:39:57 AM UTC 24 |
| Finished | Sep 04 08:40:05 AM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307581863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.3307581863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.2332891019 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 519201419 ps |
| CPU time | 14.84 seconds |
| Started | Sep 04 08:40:02 AM UTC 24 |
| Finished | Sep 04 08:40:18 AM UTC 24 |
| Peak memory | 253364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332891019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.2332891019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.3727247426 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1351158133 ps |
| CPU time | 15.32 seconds |
| Started | Sep 04 08:40:05 AM UTC 24 |
| Finished | Sep 04 08:40:21 AM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727247426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.3727247426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.3204497932 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 128419613 ps |
| CPU time | 3.49 seconds |
| Started | Sep 04 08:39:57 AM UTC 24 |
| Finished | Sep 04 08:40:01 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204497932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.3204497932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.2271766772 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2598323498 ps |
| CPU time | 9.76 seconds |
| Started | Sep 04 08:39:57 AM UTC 24 |
| Finished | Sep 04 08:40:08 AM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271766772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.2271766772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.3334779805 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 4300756183 ps |
| CPU time | 84.92 seconds |
| Started | Sep 04 08:40:06 AM UTC 24 |
| Finished | Sep 04 08:41:33 AM UTC 24 |
| Peak memory | 267828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3334779805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.otp_ctrl_stress_all_with_rand_reset.3334779805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.316796579 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 2913209257 ps |
| CPU time | 24.48 seconds |
| Started | Sep 04 08:40:05 AM UTC 24 |
| Finished | Sep 04 08:40:31 AM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316796579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.316796579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.3177717674 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 198649580 ps |
| CPU time | 6.59 seconds |
| Started | Sep 04 08:46:22 AM UTC 24 |
| Finished | Sep 04 08:46:29 AM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177717674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.3177717674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.119323165 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 1672467226 ps |
| CPU time | 5.53 seconds |
| Started | Sep 04 08:46:22 AM UTC 24 |
| Finished | Sep 04 08:46:28 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119323165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.119323165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.3574972480 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 93106847 ps |
| CPU time | 3.1 seconds |
| Started | Sep 04 08:46:22 AM UTC 24 |
| Finished | Sep 04 08:46:26 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574972480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.3574972480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.1368270508 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 11755099068 ps |
| CPU time | 111.03 seconds |
| Started | Sep 04 08:46:22 AM UTC 24 |
| Finished | Sep 04 08:48:15 AM UTC 24 |
| Peak memory | 274092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1368270508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 61.otp_ctrl_stress_all_with_rand_reset.1368270508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.2309766664 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 202278878 ps |
| CPU time | 4.55 seconds |
| Started | Sep 04 08:46:22 AM UTC 24 |
| Finished | Sep 04 08:46:28 AM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309766664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.2309766664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.3465939062 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 11689591996 ps |
| CPU time | 25.68 seconds |
| Started | Sep 04 08:46:22 AM UTC 24 |
| Finished | Sep 04 08:46:49 AM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465939062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.3465939062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.1550488611 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 8787904649 ps |
| CPU time | 127.71 seconds |
| Started | Sep 04 08:46:22 AM UTC 24 |
| Finished | Sep 04 08:48:32 AM UTC 24 |
| Peak memory | 274072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1550488611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 62.otp_ctrl_stress_all_with_rand_reset.1550488611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.998102470 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 98531940 ps |
| CPU time | 3.59 seconds |
| Started | Sep 04 08:46:25 AM UTC 24 |
| Finished | Sep 04 08:46:29 AM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998102470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.998102470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.270648346 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 1147466670 ps |
| CPU time | 6.16 seconds |
| Started | Sep 04 08:46:25 AM UTC 24 |
| Finished | Sep 04 08:46:32 AM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270648346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.270648346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.1453787922 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 269485831 ps |
| CPU time | 6.49 seconds |
| Started | Sep 04 08:46:25 AM UTC 24 |
| Finished | Sep 04 08:46:33 AM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453787922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.1453787922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.3236123789 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 195633866 ps |
| CPU time | 3.56 seconds |
| Started | Sep 04 08:46:27 AM UTC 24 |
| Finished | Sep 04 08:46:32 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236123789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.3236123789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.2993031447 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 7163732646 ps |
| CPU time | 93.56 seconds |
| Started | Sep 04 08:46:29 AM UTC 24 |
| Finished | Sep 04 08:48:05 AM UTC 24 |
| Peak memory | 257596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2993031447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 64.otp_ctrl_stress_all_with_rand_reset.2993031447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.499351234 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 405363994 ps |
| CPU time | 4.25 seconds |
| Started | Sep 04 08:46:29 AM UTC 24 |
| Finished | Sep 04 08:46:35 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499351234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.499351234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.2316017854 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 5826375681 ps |
| CPU time | 12.34 seconds |
| Started | Sep 04 08:46:29 AM UTC 24 |
| Finished | Sep 04 08:46:43 AM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316017854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.2316017854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.1829123169 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 291142649 ps |
| CPU time | 7.02 seconds |
| Started | Sep 04 08:46:31 AM UTC 24 |
| Finished | Sep 04 08:46:39 AM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829123169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.1829123169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.1649743192 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 6937877293 ps |
| CPU time | 15.82 seconds |
| Started | Sep 04 08:46:31 AM UTC 24 |
| Finished | Sep 04 08:46:49 AM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649743192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.1649743192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.1603979433 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 2992104345 ps |
| CPU time | 56.89 seconds |
| Started | Sep 04 08:46:31 AM UTC 24 |
| Finished | Sep 04 08:47:30 AM UTC 24 |
| Peak memory | 267796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1603979433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 66.otp_ctrl_stress_all_with_rand_reset.1603979433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.1143532514 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 274579452 ps |
| CPU time | 4.4 seconds |
| Started | Sep 04 08:46:31 AM UTC 24 |
| Finished | Sep 04 08:46:37 AM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143532514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.1143532514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.2327390333 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 19638769778 ps |
| CPU time | 84.84 seconds |
| Started | Sep 04 08:46:34 AM UTC 24 |
| Finished | Sep 04 08:48:01 AM UTC 24 |
| Peak memory | 267800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2327390333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 67.otp_ctrl_stress_all_with_rand_reset.2327390333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/67.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.3847442526 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 136986713 ps |
| CPU time | 6.28 seconds |
| Started | Sep 04 08:46:34 AM UTC 24 |
| Finished | Sep 04 08:46:42 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847442526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.3847442526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.3573027250 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 428476572 ps |
| CPU time | 6.43 seconds |
| Started | Sep 04 08:46:34 AM UTC 24 |
| Finished | Sep 04 08:46:42 AM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573027250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.3573027250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.1468602795 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 3087617567 ps |
| CPU time | 126.78 seconds |
| Started | Sep 04 08:46:34 AM UTC 24 |
| Finished | Sep 04 08:48:43 AM UTC 24 |
| Peak memory | 267888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1468602795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 68.otp_ctrl_stress_all_with_rand_reset.1468602795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.2487649745 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 277138358 ps |
| CPU time | 5.22 seconds |
| Started | Sep 04 08:46:34 AM UTC 24 |
| Finished | Sep 04 08:46:41 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487649745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.2487649745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.1234856739 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 3095634341 ps |
| CPU time | 22.82 seconds |
| Started | Sep 04 08:46:37 AM UTC 24 |
| Finished | Sep 04 08:47:01 AM UTC 24 |
| Peak memory | 257396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234856739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.1234856739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.1638283577 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 315378716 ps |
| CPU time | 3.21 seconds |
| Started | Sep 04 08:40:20 AM UTC 24 |
| Finished | Sep 04 08:40:25 AM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638283577 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.1638283577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.610449427 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 3079336924 ps |
| CPU time | 39.92 seconds |
| Started | Sep 04 08:40:09 AM UTC 24 |
| Finished | Sep 04 08:40:50 AM UTC 24 |
| Peak memory | 253488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610449427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.610449427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.552310981 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 15035422544 ps |
| CPU time | 69.51 seconds |
| Started | Sep 04 08:40:12 AM UTC 24 |
| Finished | Sep 04 08:41:23 AM UTC 24 |
| Peak memory | 253684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552310981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.552310981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.894005506 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 759150989 ps |
| CPU time | 25.21 seconds |
| Started | Sep 04 08:40:12 AM UTC 24 |
| Finished | Sep 04 08:40:39 AM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894005506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.894005506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.2310041633 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 22437568326 ps |
| CPU time | 32.7 seconds |
| Started | Sep 04 08:40:11 AM UTC 24 |
| Finished | Sep 04 08:40:45 AM UTC 24 |
| Peak memory | 253468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310041633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.2310041633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.865717291 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 198419197 ps |
| CPU time | 5.74 seconds |
| Started | Sep 04 08:40:09 AM UTC 24 |
| Finished | Sep 04 08:40:16 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865717291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.865717291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.2888743628 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1407025888 ps |
| CPU time | 15 seconds |
| Started | Sep 04 08:40:15 AM UTC 24 |
| Finished | Sep 04 08:40:31 AM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888743628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.2888743628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.2723727318 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2588891587 ps |
| CPU time | 10.73 seconds |
| Started | Sep 04 08:40:11 AM UTC 24 |
| Finished | Sep 04 08:40:23 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723727318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.2723727318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.1367121749 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 2051462341 ps |
| CPU time | 18.06 seconds |
| Started | Sep 04 08:40:11 AM UTC 24 |
| Finished | Sep 04 08:40:30 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367121749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.1367121749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.593248331 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 801143563 ps |
| CPU time | 9.33 seconds |
| Started | Sep 04 08:40:16 AM UTC 24 |
| Finished | Sep 04 08:40:26 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593248331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.593248331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.2996482333 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 431012212 ps |
| CPU time | 11.46 seconds |
| Started | Sep 04 08:40:08 AM UTC 24 |
| Finished | Sep 04 08:40:20 AM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996482333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.2996482333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.2798167509 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 26646947643 ps |
| CPU time | 208.52 seconds |
| Started | Sep 04 08:40:20 AM UTC 24 |
| Finished | Sep 04 08:43:52 AM UTC 24 |
| Peak memory | 267732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798167509 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.2798167509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.2683767992 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 336709082 ps |
| CPU time | 10.13 seconds |
| Started | Sep 04 08:40:16 AM UTC 24 |
| Finished | Sep 04 08:40:27 AM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683767992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2683767992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.1921187365 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 333690150 ps |
| CPU time | 4.14 seconds |
| Started | Sep 04 08:46:37 AM UTC 24 |
| Finished | Sep 04 08:46:42 AM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921187365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.1921187365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.2170419493 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 864567814 ps |
| CPU time | 6.54 seconds |
| Started | Sep 04 08:46:37 AM UTC 24 |
| Finished | Sep 04 08:46:45 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170419493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.2170419493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.96427195 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 10718432148 ps |
| CPU time | 80.27 seconds |
| Started | Sep 04 08:46:38 AM UTC 24 |
| Finished | Sep 04 08:48:01 AM UTC 24 |
| Peak memory | 268116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=96427195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.96427195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/70.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.252040804 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 1859890409 ps |
| CPU time | 7.99 seconds |
| Started | Sep 04 08:46:46 AM UTC 24 |
| Finished | Sep 04 08:46:55 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252040804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.252040804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.1226180500 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 926079432 ps |
| CPU time | 12.23 seconds |
| Started | Sep 04 08:46:46 AM UTC 24 |
| Finished | Sep 04 08:46:59 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226180500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.1226180500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.2130791208 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 2486478702 ps |
| CPU time | 81.36 seconds |
| Started | Sep 04 08:46:46 AM UTC 24 |
| Finished | Sep 04 08:48:09 AM UTC 24 |
| Peak memory | 267952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2130791208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 71.otp_ctrl_stress_all_with_rand_reset.2130791208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.4238870609 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 229891357 ps |
| CPU time | 4.97 seconds |
| Started | Sep 04 08:46:46 AM UTC 24 |
| Finished | Sep 04 08:46:52 AM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238870609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.4238870609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.302669749 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 335748562 ps |
| CPU time | 9.45 seconds |
| Started | Sep 04 08:46:46 AM UTC 24 |
| Finished | Sep 04 08:46:57 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302669749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.302669749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.2348945942 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 166361194 ps |
| CPU time | 4.63 seconds |
| Started | Sep 04 08:46:46 AM UTC 24 |
| Finished | Sep 04 08:46:52 AM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348945942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.2348945942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.1517134756 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 266184545 ps |
| CPU time | 7.39 seconds |
| Started | Sep 04 08:46:46 AM UTC 24 |
| Finished | Sep 04 08:46:55 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517134756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.1517134756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.4191077318 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 6275254049 ps |
| CPU time | 98.26 seconds |
| Started | Sep 04 08:46:46 AM UTC 24 |
| Finished | Sep 04 08:48:27 AM UTC 24 |
| Peak memory | 274068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4191077318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 73.otp_ctrl_stress_all_with_rand_reset.4191077318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.3193744624 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 552912735 ps |
| CPU time | 6.32 seconds |
| Started | Sep 04 08:46:46 AM UTC 24 |
| Finished | Sep 04 08:46:54 AM UTC 24 |
| Peak memory | 253272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193744624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.3193744624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.3607623268 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 309329439 ps |
| CPU time | 4.98 seconds |
| Started | Sep 04 08:46:46 AM UTC 24 |
| Finished | Sep 04 08:46:52 AM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607623268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.3607623268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.3378158409 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 10617966796 ps |
| CPU time | 92.69 seconds |
| Started | Sep 04 08:46:46 AM UTC 24 |
| Finished | Sep 04 08:48:21 AM UTC 24 |
| Peak memory | 267856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3378158409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 74.otp_ctrl_stress_all_with_rand_reset.3378158409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.1935929141 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 476928480 ps |
| CPU time | 4.61 seconds |
| Started | Sep 04 08:46:46 AM UTC 24 |
| Finished | Sep 04 08:46:52 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935929141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.1935929141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.3832250653 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 10499277870 ps |
| CPU time | 30.6 seconds |
| Started | Sep 04 08:46:46 AM UTC 24 |
| Finished | Sep 04 08:47:18 AM UTC 24 |
| Peak memory | 251240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832250653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.3832250653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.4278941672 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 225288050 ps |
| CPU time | 3.85 seconds |
| Started | Sep 04 08:46:49 AM UTC 24 |
| Finished | Sep 04 08:46:54 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278941672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.4278941672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.3850032485 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 2260145060 ps |
| CPU time | 18.9 seconds |
| Started | Sep 04 08:46:49 AM UTC 24 |
| Finished | Sep 04 08:47:09 AM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850032485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.3850032485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.1851172124 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 17250958694 ps |
| CPU time | 120.82 seconds |
| Started | Sep 04 08:46:49 AM UTC 24 |
| Finished | Sep 04 08:48:52 AM UTC 24 |
| Peak memory | 267952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1851172124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 76.otp_ctrl_stress_all_with_rand_reset.1851172124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.3666208964 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2271079158 ps |
| CPU time | 9.13 seconds |
| Started | Sep 04 08:46:59 AM UTC 24 |
| Finished | Sep 04 08:47:09 AM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666208964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.3666208964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.104022816 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 110910581 ps |
| CPU time | 5.51 seconds |
| Started | Sep 04 08:46:59 AM UTC 24 |
| Finished | Sep 04 08:47:05 AM UTC 24 |
| Peak memory | 250928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104022816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.104022816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.3332572983 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 102874948 ps |
| CPU time | 4.63 seconds |
| Started | Sep 04 08:46:59 AM UTC 24 |
| Finished | Sep 04 08:47:04 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332572983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.3332572983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.3317550519 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 75971425 ps |
| CPU time | 2.64 seconds |
| Started | Sep 04 08:46:59 AM UTC 24 |
| Finished | Sep 04 08:47:03 AM UTC 24 |
| Peak memory | 251124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317550519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.3317550519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.2512486127 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 2467297529 ps |
| CPU time | 6.18 seconds |
| Started | Sep 04 08:46:59 AM UTC 24 |
| Finished | Sep 04 08:47:06 AM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512486127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2512486127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.2225656471 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 228574010 ps |
| CPU time | 6.08 seconds |
| Started | Sep 04 08:46:59 AM UTC 24 |
| Finished | Sep 04 08:47:06 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225656471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.2225656471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.4130775722 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 14046890900 ps |
| CPU time | 143.2 seconds |
| Started | Sep 04 08:46:59 AM UTC 24 |
| Finished | Sep 04 08:49:25 AM UTC 24 |
| Peak memory | 274096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4130775722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 79.otp_ctrl_stress_all_with_rand_reset.4130775722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.3869164013 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 95552483 ps |
| CPU time | 3.11 seconds |
| Started | Sep 04 08:40:27 AM UTC 24 |
| Finished | Sep 04 08:40:32 AM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869164013 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.3869164013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.1257890277 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 951061450 ps |
| CPU time | 21.45 seconds |
| Started | Sep 04 08:40:20 AM UTC 24 |
| Finished | Sep 04 08:40:43 AM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257890277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.1257890277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.720680457 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 499884850 ps |
| CPU time | 8.65 seconds |
| Started | Sep 04 08:40:23 AM UTC 24 |
| Finished | Sep 04 08:40:33 AM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720680457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.720680457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.209922588 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2612992429 ps |
| CPU time | 26.28 seconds |
| Started | Sep 04 08:40:23 AM UTC 24 |
| Finished | Sep 04 08:40:50 AM UTC 24 |
| Peak memory | 253624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209922588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.209922588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.299191420 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 281823763 ps |
| CPU time | 7.25 seconds |
| Started | Sep 04 08:40:23 AM UTC 24 |
| Finished | Sep 04 08:40:31 AM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299191420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.299191420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.169896735 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 286358295 ps |
| CPU time | 4.75 seconds |
| Started | Sep 04 08:40:20 AM UTC 24 |
| Finished | Sep 04 08:40:26 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169896735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.169896735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.2811607007 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 28164845364 ps |
| CPU time | 24.43 seconds |
| Started | Sep 04 08:40:25 AM UTC 24 |
| Finished | Sep 04 08:40:50 AM UTC 24 |
| Peak memory | 253532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811607007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.2811607007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.738205524 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1782436778 ps |
| CPU time | 18.09 seconds |
| Started | Sep 04 08:40:25 AM UTC 24 |
| Finished | Sep 04 08:40:44 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738205524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.738205524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.919791890 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 689257928 ps |
| CPU time | 2.73 seconds |
| Started | Sep 04 08:40:23 AM UTC 24 |
| Finished | Sep 04 08:40:26 AM UTC 24 |
| Peak memory | 251120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919791890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.919791890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.2166775431 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 148853040 ps |
| CPU time | 6.14 seconds |
| Started | Sep 04 08:40:26 AM UTC 24 |
| Finished | Sep 04 08:40:33 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166775431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.2166775431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.697639045 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 625859550 ps |
| CPU time | 7.93 seconds |
| Started | Sep 04 08:40:20 AM UTC 24 |
| Finished | Sep 04 08:40:29 AM UTC 24 |
| Peak memory | 257504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697639045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.697639045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.3938092870 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1022914139 ps |
| CPU time | 38.15 seconds |
| Started | Sep 04 08:40:26 AM UTC 24 |
| Finished | Sep 04 08:41:06 AM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3938092870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.otp_ctrl_stress_all_with_rand_reset.3938092870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.1180921808 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1283297009 ps |
| CPU time | 18.35 seconds |
| Started | Sep 04 08:40:26 AM UTC 24 |
| Finished | Sep 04 08:40:46 AM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180921808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.1180921808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.692988405 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 152342896 ps |
| CPU time | 6.09 seconds |
| Started | Sep 04 08:46:59 AM UTC 24 |
| Finished | Sep 04 08:47:06 AM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692988405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.692988405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.2514635753 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 235720986 ps |
| CPU time | 4.94 seconds |
| Started | Sep 04 08:46:59 AM UTC 24 |
| Finished | Sep 04 08:47:05 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514635753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.2514635753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.1990927789 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 2928394791 ps |
| CPU time | 8.17 seconds |
| Started | Sep 04 08:46:59 AM UTC 24 |
| Finished | Sep 04 08:47:09 AM UTC 24 |
| Peak memory | 251268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990927789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.1990927789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.1541701617 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 327468938 ps |
| CPU time | 4.92 seconds |
| Started | Sep 04 08:46:59 AM UTC 24 |
| Finished | Sep 04 08:47:05 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541701617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.1541701617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.911327357 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 33558856960 ps |
| CPU time | 122.86 seconds |
| Started | Sep 04 08:46:59 AM UTC 24 |
| Finished | Sep 04 08:49:05 AM UTC 24 |
| Peak memory | 274092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=911327357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.911327357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.2403764383 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 674371617 ps |
| CPU time | 7.45 seconds |
| Started | Sep 04 08:46:59 AM UTC 24 |
| Finished | Sep 04 08:47:08 AM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403764383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.2403764383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.1740859243 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 157864471 ps |
| CPU time | 5.51 seconds |
| Started | Sep 04 08:46:59 AM UTC 24 |
| Finished | Sep 04 08:47:06 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740859243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.1740859243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.1657474690 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 147840285 ps |
| CPU time | 4.91 seconds |
| Started | Sep 04 08:47:01 AM UTC 24 |
| Finished | Sep 04 08:47:07 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657474690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.1657474690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.3936616413 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1452005981 ps |
| CPU time | 5.72 seconds |
| Started | Sep 04 08:47:02 AM UTC 24 |
| Finished | Sep 04 08:47:09 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936616413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.3936616413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.400778276 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 163499922 ps |
| CPU time | 5.37 seconds |
| Started | Sep 04 08:47:07 AM UTC 24 |
| Finished | Sep 04 08:47:13 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400778276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.400778276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.2921043570 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 2106129961 ps |
| CPU time | 29.6 seconds |
| Started | Sep 04 08:47:07 AM UTC 24 |
| Finished | Sep 04 08:47:38 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921043570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.2921043570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.1438413071 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 2700117803 ps |
| CPU time | 80.48 seconds |
| Started | Sep 04 08:47:07 AM UTC 24 |
| Finished | Sep 04 08:48:29 AM UTC 24 |
| Peak memory | 267948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1438413071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 84.otp_ctrl_stress_all_with_rand_reset.1438413071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.905733711 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 86518331 ps |
| CPU time | 3.83 seconds |
| Started | Sep 04 08:47:07 AM UTC 24 |
| Finished | Sep 04 08:47:12 AM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905733711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.905733711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.787549546 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 521919969 ps |
| CPU time | 11.03 seconds |
| Started | Sep 04 08:47:07 AM UTC 24 |
| Finished | Sep 04 08:47:19 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787549546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.787549546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.356553668 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 36604708805 ps |
| CPU time | 95.03 seconds |
| Started | Sep 04 08:47:10 AM UTC 24 |
| Finished | Sep 04 08:48:47 AM UTC 24 |
| Peak memory | 267952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=356553668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.356553668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.2666017674 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 430196697 ps |
| CPU time | 4.89 seconds |
| Started | Sep 04 08:47:10 AM UTC 24 |
| Finished | Sep 04 08:47:16 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666017674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.2666017674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.2765361933 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 635900197 ps |
| CPU time | 8.62 seconds |
| Started | Sep 04 08:47:10 AM UTC 24 |
| Finished | Sep 04 08:47:20 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765361933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.2765361933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.2124685695 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 19320353974 ps |
| CPU time | 92.95 seconds |
| Started | Sep 04 08:47:10 AM UTC 24 |
| Finished | Sep 04 08:48:45 AM UTC 24 |
| Peak memory | 267948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2124685695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 86.otp_ctrl_stress_all_with_rand_reset.2124685695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/86.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.2892558912 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 1851665238 ps |
| CPU time | 6.17 seconds |
| Started | Sep 04 08:47:10 AM UTC 24 |
| Finished | Sep 04 08:47:17 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892558912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.2892558912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.1255544994 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 222237288 ps |
| CPU time | 6.82 seconds |
| Started | Sep 04 08:47:10 AM UTC 24 |
| Finished | Sep 04 08:47:18 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255544994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.1255544994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.2907512885 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 1232950633 ps |
| CPU time | 32.57 seconds |
| Started | Sep 04 08:47:10 AM UTC 24 |
| Finished | Sep 04 08:47:44 AM UTC 24 |
| Peak memory | 257620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2907512885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 87.otp_ctrl_stress_all_with_rand_reset.2907512885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/87.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.4053857809 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 497579337 ps |
| CPU time | 5.65 seconds |
| Started | Sep 04 08:47:10 AM UTC 24 |
| Finished | Sep 04 08:47:17 AM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053857809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.4053857809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.2823794991 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 200496466 ps |
| CPU time | 12.32 seconds |
| Started | Sep 04 08:47:13 AM UTC 24 |
| Finished | Sep 04 08:47:26 AM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823794991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.2823794991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.2322253834 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 152819163 ps |
| CPU time | 4.77 seconds |
| Started | Sep 04 08:47:13 AM UTC 24 |
| Finished | Sep 04 08:47:19 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322253834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.2322253834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.2163386316 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 259661428 ps |
| CPU time | 3.44 seconds |
| Started | Sep 04 08:47:13 AM UTC 24 |
| Finished | Sep 04 08:47:18 AM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163386316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.2163386316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.411616420 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 99970231 ps |
| CPU time | 3.23 seconds |
| Started | Sep 04 08:40:40 AM UTC 24 |
| Finished | Sep 04 08:40:44 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411616420 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.411616420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.2528067789 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 519859651 ps |
| CPU time | 7.66 seconds |
| Started | Sep 04 08:40:30 AM UTC 24 |
| Finished | Sep 04 08:40:39 AM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528067789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.2528067789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.1233894338 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 656856634 ps |
| CPU time | 12.88 seconds |
| Started | Sep 04 08:40:33 AM UTC 24 |
| Finished | Sep 04 08:40:47 AM UTC 24 |
| Peak memory | 253620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233894338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.1233894338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.234566746 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 1490421771 ps |
| CPU time | 30.99 seconds |
| Started | Sep 04 08:40:33 AM UTC 24 |
| Finished | Sep 04 08:41:05 AM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234566746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.234566746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.2153608624 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 14188067060 ps |
| CPU time | 31.66 seconds |
| Started | Sep 04 08:40:31 AM UTC 24 |
| Finished | Sep 04 08:41:04 AM UTC 24 |
| Peak memory | 253468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153608624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.2153608624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.1148832965 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 200966164 ps |
| CPU time | 5.13 seconds |
| Started | Sep 04 08:40:29 AM UTC 24 |
| Finished | Sep 04 08:40:35 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148832965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.1148832965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.722538729 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 879237928 ps |
| CPU time | 11.09 seconds |
| Started | Sep 04 08:40:33 AM UTC 24 |
| Finished | Sep 04 08:40:45 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722538729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.722538729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.1545710698 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2819222736 ps |
| CPU time | 20.48 seconds |
| Started | Sep 04 08:40:33 AM UTC 24 |
| Finished | Sep 04 08:40:55 AM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545710698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.1545710698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.2851776108 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 776539021 ps |
| CPU time | 20.19 seconds |
| Started | Sep 04 08:40:31 AM UTC 24 |
| Finished | Sep 04 08:40:53 AM UTC 24 |
| Peak memory | 257360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851776108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.2851776108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.2170291765 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 4901598375 ps |
| CPU time | 12.72 seconds |
| Started | Sep 04 08:40:27 AM UTC 24 |
| Finished | Sep 04 08:40:41 AM UTC 24 |
| Peak memory | 253532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170291765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.2170291765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.1645264199 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 4771902614 ps |
| CPU time | 59.51 seconds |
| Started | Sep 04 08:40:38 AM UTC 24 |
| Finished | Sep 04 08:41:40 AM UTC 24 |
| Peak memory | 257464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645264199 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.1645264199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.3439877114 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 16298188775 ps |
| CPU time | 152.22 seconds |
| Started | Sep 04 08:40:35 AM UTC 24 |
| Finished | Sep 04 08:43:11 AM UTC 24 |
| Peak memory | 274008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3439877114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.otp_ctrl_stress_all_with_rand_reset.3439877114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.965626543 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1217865728 ps |
| CPU time | 10.77 seconds |
| Started | Sep 04 08:40:34 AM UTC 24 |
| Finished | Sep 04 08:40:46 AM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965626543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.965626543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.1416063354 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 288554813 ps |
| CPU time | 4.76 seconds |
| Started | Sep 04 08:47:24 AM UTC 24 |
| Finished | Sep 04 08:47:30 AM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416063354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.1416063354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.253974521 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 1950546522 ps |
| CPU time | 5.44 seconds |
| Started | Sep 04 08:47:24 AM UTC 24 |
| Finished | Sep 04 08:47:31 AM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253974521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.253974521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.2240933434 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 237706244 ps |
| CPU time | 5.58 seconds |
| Started | Sep 04 08:47:24 AM UTC 24 |
| Finished | Sep 04 08:47:31 AM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240933434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.2240933434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.3662412927 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 658085223 ps |
| CPU time | 11.81 seconds |
| Started | Sep 04 08:47:24 AM UTC 24 |
| Finished | Sep 04 08:47:38 AM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662412927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.3662412927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.1639703800 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 164784323 ps |
| CPU time | 6.63 seconds |
| Started | Sep 04 08:47:25 AM UTC 24 |
| Finished | Sep 04 08:47:33 AM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639703800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.1639703800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.2711242532 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 495842494 ps |
| CPU time | 16.21 seconds |
| Started | Sep 04 08:47:25 AM UTC 24 |
| Finished | Sep 04 08:47:42 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711242532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.2711242532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.634070239 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 328288735 ps |
| CPU time | 5.99 seconds |
| Started | Sep 04 08:47:25 AM UTC 24 |
| Finished | Sep 04 08:47:32 AM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634070239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.634070239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.3800472183 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 579136375 ps |
| CPU time | 20.22 seconds |
| Started | Sep 04 08:47:25 AM UTC 24 |
| Finished | Sep 04 08:47:46 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800472183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.3800472183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.2102146858 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 38273255554 ps |
| CPU time | 103.55 seconds |
| Started | Sep 04 08:47:25 AM UTC 24 |
| Finished | Sep 04 08:49:11 AM UTC 24 |
| Peak memory | 267860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2102146858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 93.otp_ctrl_stress_all_with_rand_reset.2102146858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/93.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.977775949 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 241626897 ps |
| CPU time | 6.34 seconds |
| Started | Sep 04 08:47:25 AM UTC 24 |
| Finished | Sep 04 08:47:32 AM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977775949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.977775949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.2907465269 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 3019579235 ps |
| CPU time | 24.88 seconds |
| Started | Sep 04 08:47:25 AM UTC 24 |
| Finished | Sep 04 08:47:51 AM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907465269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.2907465269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.3346284577 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 6380572053 ps |
| CPU time | 58.04 seconds |
| Started | Sep 04 08:47:31 AM UTC 24 |
| Finished | Sep 04 08:48:30 AM UTC 24 |
| Peak memory | 267860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3346284577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 94.otp_ctrl_stress_all_with_rand_reset.3346284577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.4011579431 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 507547942 ps |
| CPU time | 5.67 seconds |
| Started | Sep 04 08:47:31 AM UTC 24 |
| Finished | Sep 04 08:47:37 AM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011579431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.4011579431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.1222499759 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 404657344 ps |
| CPU time | 13.58 seconds |
| Started | Sep 04 08:47:31 AM UTC 24 |
| Finished | Sep 04 08:47:45 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222499759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.1222499759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.268651990 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 13608107187 ps |
| CPU time | 30.8 seconds |
| Started | Sep 04 08:47:34 AM UTC 24 |
| Finished | Sep 04 08:48:07 AM UTC 24 |
| Peak memory | 257472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=268651990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.268651990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/95.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.18240063 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 133571699 ps |
| CPU time | 4.9 seconds |
| Started | Sep 04 08:47:34 AM UTC 24 |
| Finished | Sep 04 08:47:40 AM UTC 24 |
| Peak memory | 251396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18240063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.18240063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.3241292043 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 263547395 ps |
| CPU time | 6.92 seconds |
| Started | Sep 04 08:47:34 AM UTC 24 |
| Finished | Sep 04 08:47:43 AM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241292043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.3241292043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.3707640823 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 128613487 ps |
| CPU time | 6.64 seconds |
| Started | Sep 04 08:47:34 AM UTC 24 |
| Finished | Sep 04 08:47:42 AM UTC 24 |
| Peak memory | 253276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707640823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.3707640823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.3971727663 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 2719579118 ps |
| CPU time | 27.89 seconds |
| Started | Sep 04 08:47:34 AM UTC 24 |
| Finished | Sep 04 08:48:04 AM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971727663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.3971727663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.3518197634 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 492886788 ps |
| CPU time | 5.28 seconds |
| Started | Sep 04 08:47:36 AM UTC 24 |
| Finished | Sep 04 08:47:43 AM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518197634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.3518197634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.533400547 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 491934396 ps |
| CPU time | 8.42 seconds |
| Started | Sep 04 08:47:39 AM UTC 24 |
| Finished | Sep 04 08:47:48 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533400547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.533400547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.3279596595 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 463556176 ps |
| CPU time | 3.8 seconds |
| Started | Sep 04 08:47:40 AM UTC 24 |
| Finished | Sep 04 08:47:45 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279596595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.3279596595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.3420422418 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 597927194 ps |
| CPU time | 9.4 seconds |
| Started | Sep 04 08:47:42 AM UTC 24 |
| Finished | Sep 04 08:47:52 AM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420422418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3420422418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest |
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