Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_unbuf_access_lock_cg_wrap::unbuf_access_lock_cg

Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_access_lock_cg_wrap::unbuf_access_lock_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

5 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
buf_err_code_cg_wrap[CreatorSwCfgIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[OwnerSwCfgIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[RotCreatorAuthStateIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[VendorTestIdx]	100.00	1	100	1	64	64

---

Group Instance : buf_err_code_cg_wrap[CreatorSwCfgIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OwnerSwCfgIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[VendorTestIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

21149

1

T3

6

T6

2

T4

5

write_op

5153

1

T3

3

T4

3

T11

3

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10082

1

T3

9

T4

2

T11

9

auto[1]

16220

1

T6

2

T4

6

T95

4

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19048

1

T3

9

T6

2

T4

8

auto[1]

7254

1

T95

15

T129

12

T20

8

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	4695	1			T3	6		T11	6		T5	3
auto[0]	auto[0]	write_op	2576	1			T3	3		T4	2		T11	3
auto[0]	auto[1]	read_op	2127	1			T95	8		T129	2		T20	2
auto[0]	auto[1]	write_op	684	1			T95	4		T36	1		T89	1
auto[1]	auto[0]	read_op	10572	1			T6	2		T4	5		T95	1
auto[1]	auto[0]	write_op	1205	1			T4	1		T20	1		T128	1
auto[1]	auto[1]	read_op	3755	1			T95	3		T129	8		T20	6
auto[1]	auto[1]	write_op	688	1			T129	2		T128	2		T36	2

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

22750

1

T3

10

T6

4

T4

2

write_op

5231

1

T3

4

T6

1

T4

1

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10582

1

T3

14

T6

1

T4

3

auto[1]

17399

1

T6

4

T14

2

T34

2

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22890

1

T3

14

T6

5

T4

3

auto[1]

5091

1

T95

5

T129

5

T89

11

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	5666	1			T3	10		T4	2		T11	12
auto[0]	auto[0]	write_op	2844	1			T3	4		T6	1		T4	1
auto[0]	auto[1]	read_op	1544	1			T95	4		T89	6		T119	5
auto[0]	auto[1]	write_op	528	1			T95	1		T89	2		T119	1
auto[1]	auto[0]	read_op	13023	1			T6	4		T14	2		T34	2
auto[1]	auto[0]	write_op	1357	1			T128	2		T36	3		T89	1
auto[1]	auto[1]	read_op	2517	1			T129	3		T89	2		T119	5
auto[1]	auto[1]	write_op	502	1			T129	2		T89	1		T119	1

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

21418

1

T2

1

T3

10

T6

2

write_op

5315

1

T3

4

T4

2

T11

4

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10104

1

T2

1

T3

14

T4

1

auto[1]

16629

1

T6

2

T4

7

T95

4

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19392

1

T2

1

T3

14

T6

2

auto[1]

7341

1

T129

1

T20

17

T128

8

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	4712	1			T2	1		T3	10		T4	1
auto[0]	auto[0]	write_op	2572	1			T3	4		T11	4		T13	2
auto[0]	auto[1]	read_op	2079	1			T20	11		T128	1		T89	9
auto[0]	auto[1]	write_op	741	1			T20	6		T89	4		T21	2
auto[1]	auto[0]	read_op	10839	1			T6	2		T4	5		T95	3
auto[1]	auto[0]	write_op	1269	1			T4	2		T95	1		T129	1
auto[1]	auto[1]	read_op	3788	1			T129	1		T128	6		T89	2
auto[1]	auto[1]	write_op	733	1			T128	1		T119	1		T18	2

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

20488

1

T2

1

T3

4

T4

5

write_op

3734

1

T2

1

T3

2

T4

5

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9225

1

T2

2

T3

6

T4

10

auto[1]

14997

1

T95

12

T34

4

T7

12

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21503

1

T2

2

T3

6

T4

10

auto[1]

2719

1

T20

8

T128

10

T99

12

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	5867	1			T2	1		T3	4		T4	5
auto[0]	auto[0]	write_op	2295	1			T2	1		T3	2		T4	5
auto[0]	auto[1]	read_op	873	1			T20	6		T124	10		T130	9
auto[0]	auto[1]	write_op	190	1			T20	2		T124	2		T97	2
auto[1]	auto[0]	read_op	12258	1			T95	10		T34	4		T7	11
auto[1]	auto[0]	write_op	1083	1			T95	2		T7	1		T128	1
auto[1]	auto[1]	read_op	1490	1			T128	8		T99	10		T124	11
auto[1]	auto[1]	write_op	166	1			T128	2		T99	2		T124	2

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

20532

1

T3

14

T6

6

T4

5

write_op

4776

1

T3

5

T4

3

T11

4

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9809

1

T3

19

T4

5

T11

16

auto[1]

15499

1

T6

6

T4

3

T95

2

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18345

1

T3

19

T6

6

T4

8

auto[1]

6963

1

T95

7

T129

9

T20

12

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	4563	1			T3	14		T4	3		T11	12
auto[0]	auto[0]	write_op	2460	1			T3	5		T4	2		T11	4
auto[0]	auto[1]	read_op	2176	1			T95	5		T129	4		T20	8
auto[0]	auto[1]	write_op	610	1			T95	2		T129	1		T20	4
auto[1]	auto[0]	read_op	10234	1			T6	6		T4	2		T95	2
auto[1]	auto[0]	write_op	1088	1			T4	1		T129	2		T89	1
auto[1]	auto[1]	read_op	3559	1			T129	3		T89	6		T119	1
auto[1]	auto[1]	write_op	618	1			T129	1		T119	1		T22	1