Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5235663

1

T1

13

T2

517

T3

490

full_word

2495458

1

T1

6

T2

74

T3

221

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7730801	1			T1	19		T2	591		T3	711
auto[TlIntgErrCmd]	102	1			T302	3		T303	9		T304	4
auto[TlIntgErrData]	111	1			T302	2		T303	8		T304	3
auto[TlIntgErrBoth]	107	1			T302	5		T303	3		T304	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5862973

1

T1

4

T2

566

T3

454

auto[1]

1868148

1

T1

15

T2

25

T3

257

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3925292	1			T1	2		T2	500		T3	336
auto[TlIntgErrNone]	partial	auto[1]	1310078	1			T1	11		T2	17		T3	154
auto[TlIntgErrNone]	full_word	auto[0]	1937522	1			T1	2		T2	66		T3	118
auto[TlIntgErrNone]	full_word	auto[1]	557909	1			T1	4		T2	8		T3	103
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T303	3		T304	3		T407	6
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T302	3		T303	6		T304	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T311	1		T408	2		-	-
auto[TlIntgErrData]	partial	auto[0]	51	1			T302	1		T303	5		T304	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T303	3		T304	2		T409	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T410	1		T311	1		T411	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T302	1		T412	2		T413	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T302	4		T303	1		T304	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T302	1		T303	1		T304	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T407	1		T409	1		T410	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T303	1		T410	2		T414	1