Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	94.16	95.24	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	83832030	368318	0	0
check_regwen_rd_A	83832030	1658	0	0
check_timeout_rd_A	83832030	617	0	0
check_trigger_regwen_rd_A	83832030	1841	0	0
consistency_check_period_rd_A	83832030	1720	0	0
creator_sw_cfg_read_lock_rd_A	83832030	666	0	0
direct_access_address_rd_A	83832030	352	0	0
direct_access_wdata_0_rd_A	83832030	37	0	0
direct_access_wdata_1_rd_A	83832030	60	0	0
integrity_check_period_rd_A	83832030	1875	0	0
intr_enable_rd_A	83832030	2377	0	0
owner_sw_cfg_read_lock_rd_A	83832030	520	0	0
rot_creator_auth_codesign_read_lock_rd_A	83832030	457	0	0
rot_creator_auth_state_read_lock_rd_A	83832030	555	0	0
vendor_test_read_lock_rd_A	83832030	565	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	368318	0	0
T15	201751	6850	0	0
T16	0	6186	0	0
T17	0	4432	0	0
T23	0	6860	0	0
T25	0	10350	0	0
T55	12037	0	0	0
T91	0	7685	0	0
T94	0	2476	0	0
T179	0	5751	0	0
T305	6654	0	0	0
T321	0	9745	0	0
T322	0	11112	0	0
T323	87909	0	0	0
T324	7429	0	0	0
T325	69229	0	0	0
T326	34592	0	0	0
T327	28155	0	0	0
T328	21924	0	0	0
T329	35309	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	1658	0	0
T30	8947	0	0	0
T165	0	20	0	0
T215	0	16	0	0
T216	0	8	0	0
T284	235169	20	0	0
T285	0	19	0	0
T364	0	43	0	0
T365	0	10	0	0
T366	0	18	0	0
T367	0	30	0	0
T368	0	3	0	0
T369	13999	0	0	0
T370	43150	0	0	0
T371	559251	0	0	0
T372	33282	0	0	0
T373	3692	0	0	0
T374	38682	0	0	0
T375	131997	0	0	0
T376	32810	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	617	0	0
T30	8947	0	0	0
T165	0	28	0	0
T215	0	30	0	0
T216	0	9	0	0
T284	235169	35	0	0
T285	0	9	0	0
T364	0	36	0	0
T365	0	22	0	0
T366	0	19	0	0
T367	0	14	0	0
T368	0	6	0	0
T369	13999	0	0	0
T370	43150	0	0	0
T371	559251	0	0	0
T372	33282	0	0	0
T373	3692	0	0	0
T374	38682	0	0	0
T375	131997	0	0	0
T376	32810	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	1841	0	0
T30	8947	0	0	0
T165	0	19	0	0
T215	0	19	0	0
T216	0	21	0	0
T284	235169	25	0	0
T285	0	34	0	0
T364	0	46	0	0
T365	0	21	0	0
T366	0	13	0	0
T367	0	31	0	0
T368	0	29	0	0
T369	13999	0	0	0
T370	43150	0	0	0
T371	559251	0	0	0
T372	33282	0	0	0
T373	3692	0	0	0
T374	38682	0	0	0
T375	131997	0	0	0
T376	32810	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	1720	0	0
T30	8947	0	0	0
T165	0	27	0	0
T215	0	20	0	0
T216	0	26	0	0
T284	235169	23	0	0
T285	0	34	0	0
T364	0	32	0	0
T365	0	13	0	0
T366	0	16	0	0
T367	0	4	0	0
T369	13999	0	0	0
T370	43150	0	0	0
T371	559251	0	0	0
T372	33282	0	0	0
T373	3692	0	0	0
T374	38682	0	0	0
T375	131997	0	0	0
T376	32810	0	0	0
T377	0	29	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	666	0	0
T30	8947	0	0	0
T165	0	33	0	0
T215	0	4	0	0
T216	0	7	0	0
T284	235169	20	0	0
T285	0	34	0	0
T364	0	46	0	0
T365	0	27	0	0
T366	0	11	0	0
T367	0	29	0	0
T368	0	21	0	0
T369	13999	0	0	0
T370	43150	0	0	0
T371	559251	0	0	0
T372	33282	0	0	0
T373	3692	0	0	0
T374	38682	0	0	0
T375	131997	0	0	0
T376	32810	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	352	0	0
T30	8947	0	0	0
T165	0	15	0	0
T215	0	25	0	0
T216	0	12	0	0
T284	235169	33	0	0
T285	0	15	0	0
T364	0	61	0	0
T365	0	14	0	0
T366	0	4	0	0
T367	0	22	0	0
T368	0	7	0	0
T369	13999	0	0	0
T370	43150	0	0	0
T371	559251	0	0	0
T372	33282	0	0	0
T373	3692	0	0	0
T374	38682	0	0	0
T375	131997	0	0	0
T376	32810	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	37	0	0
T59	13379	0	0	0
T165	159720	6	0	0
T168	58915	0	0	0
T170	21506	0	0	0
T285	0	2	0	0
T364	0	2	0	0
T365	0	9	0	0
T367	0	7	0	0
T378	0	11	0	0
T379	62027	0	0	0
T380	29624	0	0	0
T381	91472	0	0	0
T382	4382	0	0	0
T383	32572	0	0	0
T384	67010	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	60	0	0
T59	13379	0	0	0
T165	159720	10	0	0
T168	58915	0	0	0
T170	21506	0	0	0
T215	0	7	0	0
T285	0	3	0	0
T364	0	17	0	0
T365	0	9	0	0
T378	0	5	0	0
T379	62027	0	0	0
T380	29624	0	0	0
T381	91472	0	0	0
T382	4382	0	0	0
T383	32572	0	0	0
T384	67010	0	0	0
T385	0	9	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	1875	0	0
T30	8947	0	0	0
T165	0	26	0	0
T215	0	31	0	0
T216	0	14	0	0
T284	235169	20	0	0
T285	0	18	0	0
T364	0	39	0	0
T365	0	27	0	0
T366	0	6	0	0
T367	0	19	0	0
T368	0	13	0	0
T369	13999	0	0	0
T370	43150	0	0	0
T371	559251	0	0	0
T372	33282	0	0	0
T373	3692	0	0	0
T374	38682	0	0	0
T375	131997	0	0	0
T376	32810	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	2377	0	0
T56	12680	0	0	0
T105	0	10	0	0
T155	0	5	0	0
T165	0	32	0	0
T279	31367	0	0	0
T284	0	22	0	0
T285	0	63	0	0
T296	24321	0	0	0
T305	6654	10	0	0
T327	28155	0	0	0
T328	21924	0	0	0
T329	35309	0	0	0
T364	0	76	0	0
T365	0	46	0	0
T386	0	7	0	0
T387	0	22	0	0
T388	44484	0	0	0
T389	18032	0	0	0
T390	146477	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	520	0	0
T30	8947	0	0	0
T165	0	23	0	0
T215	0	26	0	0
T216	0	14	0	0
T284	235169	9	0	0
T285	0	22	0	0
T364	0	84	0	0
T365	0	22	0	0
T366	0	6	0	0
T367	0	26	0	0
T368	0	25	0	0
T369	13999	0	0	0
T370	43150	0	0	0
T371	559251	0	0	0
T372	33282	0	0	0
T373	3692	0	0	0
T374	38682	0	0	0
T375	131997	0	0	0
T376	32810	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	457	0	0
T30	8947	0	0	0
T165	0	20	0	0
T215	0	12	0	0
T216	0	14	0	0
T284	235169	22	0	0
T285	0	17	0	0
T364	0	39	0	0
T365	0	30	0	0
T366	0	22	0	0
T367	0	22	0	0
T368	0	6	0	0
T369	13999	0	0	0
T370	43150	0	0	0
T371	559251	0	0	0
T372	33282	0	0	0
T373	3692	0	0	0
T374	38682	0	0	0
T375	131997	0	0	0
T376	32810	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	555	0	0
T30	8947	0	0	0
T165	0	17	0	0
T215	0	21	0	0
T216	0	26	0	0
T284	235169	26	0	0
T285	0	37	0	0
T364	0	31	0	0
T365	0	17	0	0
T366	0	9	0	0
T367	0	19	0	0
T368	0	10	0	0
T369	13999	0	0	0
T370	43150	0	0	0
T371	559251	0	0	0
T372	33282	0	0	0
T373	3692	0	0	0
T374	38682	0	0	0
T375	131997	0	0	0
T376	32810	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	565	0	0
T30	8947	0	0	0
T165	0	14	0	0
T215	0	11	0	0
T216	0	15	0	0
T284	235169	24	0	0
T285	0	23	0	0
T364	0	56	0	0
T365	0	17	0	0
T366	0	19	0	0
T367	0	18	0	0
T368	0	14	0	0
T369	13999	0	0	0
T370	43150	0	0	0
T371	559251	0	0	0
T372	33282	0	0	0
T373	3692	0	0	0
T374	38682	0	0	0
T375	131997	0	0	0
T376	32810	0	0	0