Unified Coverage Report :: Module :: otp_ctrl_core_reg_top

Module : otp_ctrl_core_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.69	100.00	94.75			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core	98.69	100.00	94.75			100.00	100.00

---

Module Instance : tb.dut.u_reg_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.69	100.00	94.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	99.65	96.31	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	94.16	95.24	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_bus_integ_error	100.00	100.00
u_alert_test_fatal_check_error	100.00	100.00
u_alert_test_fatal_macro_error	100.00	100.00
u_alert_test_fatal_prim_otp_alert	100.00	100.00
u_alert_test_recov_prim_otp_alert	100.00	100.00
u_check_regwen	100.00	100.00	100.00			100.00
u_check_timeout	100.00	100.00	100.00			100.00
u_check_trigger_consistency	100.00	100.00
u_check_trigger_integrity	100.00	100.00
u_check_trigger_regwen	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_consistency_check_period	100.00	100.00	100.00			100.00
u_creator_sw_cfg_digest_0	100.00	100.00
u_creator_sw_cfg_digest_1	100.00	100.00
u_creator_sw_cfg_read_lock	100.00	100.00	100.00			100.00
u_direct_access_address	100.00	100.00	100.00			100.00
u_direct_access_cmd_digest	100.00	100.00
u_direct_access_cmd_rd	100.00	100.00
u_direct_access_cmd_wr	100.00	100.00
u_direct_access_rdata_0	100.00	100.00
u_direct_access_rdata_1	100.00	100.00
u_direct_access_regwen	100.00	100.00
u_direct_access_wdata_0	100.00	100.00	100.00			100.00
u_direct_access_wdata_1	100.00	100.00	100.00			100.00
u_err_code_0	100.00	100.00
u_err_code_1	100.00	100.00
u_err_code_10	100.00	100.00
u_err_code_11	100.00	100.00
u_err_code_12	100.00	100.00
u_err_code_2	100.00	100.00
u_err_code_3	100.00	100.00
u_err_code_4	100.00	100.00
u_err_code_5	100.00	100.00
u_err_code_6	100.00	100.00
u_err_code_7	100.00	100.00
u_err_code_8	100.00	100.00
u_err_code_9	100.00	100.00
u_hw_cfg0_digest_0	100.00	100.00
u_hw_cfg0_digest_1	100.00	100.00
u_hw_cfg1_digest_0	100.00	100.00
u_hw_cfg1_digest_1	100.00	100.00
u_integrity_check_period	100.00	100.00	100.00			100.00
u_intr_enable_otp_error	100.00	100.00	100.00			100.00
u_intr_enable_otp_operation_done	100.00	100.00	100.00			100.00
u_intr_state_otp_error	100.00	100.00	100.00			100.00
u_intr_state_otp_operation_done	100.00	100.00	100.00			100.00
u_intr_test_otp_error	100.00	100.00
u_intr_test_otp_operation_done	100.00	100.00
u_owner_sw_cfg_digest_0	100.00	100.00
u_owner_sw_cfg_digest_1	100.00	100.00
u_owner_sw_cfg_read_lock	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.97	97.14	98.75			100.00	100.00
u_rot_creator_auth_codesign_digest_0	100.00	100.00
u_rot_creator_auth_codesign_digest_1	100.00	100.00
u_rot_creator_auth_codesign_read_lock	100.00	100.00	100.00			100.00
u_rot_creator_auth_state_digest_0	100.00	100.00
u_rot_creator_auth_state_digest_1	100.00	100.00
u_rot_creator_auth_state_read_lock	100.00	100.00	100.00			100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_secret0_digest_0	100.00	100.00
u_secret0_digest_1	100.00	100.00
u_secret1_digest_0	100.00	100.00
u_secret1_digest_1	100.00	100.00
u_secret2_digest_0	100.00	100.00
u_secret2_digest_1	100.00	100.00
u_socket	99.69	98.75	100.00			100.00	100.00
u_status_bus_integ_error	100.00	100.00
u_status_check_pending	100.00	100.00
u_status_creator_sw_cfg_error	100.00	100.00
u_status_dai_error	100.00	100.00
u_status_dai_idle	100.00	100.00
u_status_hw_cfg0_error	100.00	100.00
u_status_hw_cfg1_error	100.00	100.00
u_status_key_deriv_fsm_error	100.00	100.00
u_status_lci_error	100.00	100.00
u_status_lfsr_fsm_error	100.00	100.00
u_status_life_cycle_error	100.00	100.00
u_status_owner_sw_cfg_error	100.00	100.00
u_status_rot_creator_auth_codesign_error	100.00	100.00
u_status_rot_creator_auth_state_error	100.00	100.00
u_status_scrambling_fsm_error	100.00	100.00
u_status_secret0_error	100.00	100.00
u_status_secret1_error	100.00	100.00
u_status_secret2_error	100.00	100.00
u_status_timeout_error	100.00	100.00
u_status_vendor_test_error	100.00	100.00
u_vendor_test_digest_0	100.00	100.00
u_vendor_test_digest_1	100.00	100.00
u_vendor_test_read_lock	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : otp_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
TOTAL		337	337	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	566	1	1	100.00
CONT_ASSIGN	1095	1	1	100.00
CONT_ASSIGN	1109	1	1	100.00
CONT_ASSIGN	1115	1	1	100.00
CONT_ASSIGN	1118	1	1	100.00
CONT_ASSIGN	1133	1	1	100.00
CONT_ASSIGN	1149	1	1	100.00
CONT_ASSIGN	1165	1	1	100.00
CONT_ASSIGN	1171	1	1	100.00
CONT_ASSIGN	1203	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1328	1	1	100.00
CONT_ASSIGN	1331	1	1	100.00
CONT_ASSIGN	1346	1	1	100.00
CONT_ASSIGN	1362	1	1	100.00
CONT_ASSIGN	1396	1	1	100.00
CONT_ASSIGN	1427	1	1	100.00
CONT_ASSIGN	1458	1	1	100.00
CONT_ASSIGN	1489	1	1	100.00
CONT_ASSIGN	1520	1	1	100.00
CONT_ASSIGN	1551	1	1	100.00
CONT_ASSIGN	1582	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
ALWAYS	1986	57	57	100.00
CONT_ASSIGN	2045	1	1	100.00
ALWAYS	2049	1	1	100.00
CONT_ASSIGN	2109	1	1	100.00
CONT_ASSIGN	2111	1	1	100.00
CONT_ASSIGN	2113	1	1	100.00
CONT_ASSIGN	2114	1	1	100.00
CONT_ASSIGN	2116	1	1	100.00
CONT_ASSIGN	2118	1	1	100.00
CONT_ASSIGN	2119	1	1	100.00
CONT_ASSIGN	2121	1	1	100.00
CONT_ASSIGN	2123	1	1	100.00
CONT_ASSIGN	2124	1	1	100.00
CONT_ASSIGN	2126	1	1	100.00
CONT_ASSIGN	2128	1	1	100.00
CONT_ASSIGN	2130	1	1	100.00
CONT_ASSIGN	2132	1	1	100.00
CONT_ASSIGN	2134	1	1	100.00
CONT_ASSIGN	2135	1	1	100.00
CONT_ASSIGN	2136	1	1	100.00
CONT_ASSIGN	2137	1	1	100.00
CONT_ASSIGN	2138	1	1	100.00
CONT_ASSIGN	2139	1	1	100.00
CONT_ASSIGN	2140	1	1	100.00
CONT_ASSIGN	2141	1	1	100.00
CONT_ASSIGN	2142	1	1	100.00
CONT_ASSIGN	2143	1	1	100.00
CONT_ASSIGN	2144	1	1	100.00
CONT_ASSIGN	2145	1	1	100.00
CONT_ASSIGN	2146	1	1	100.00
CONT_ASSIGN	2147	1	1	100.00
CONT_ASSIGN	2148	1	1	100.00
CONT_ASSIGN	2149	1	1	100.00
CONT_ASSIGN	2150	1	1	100.00
CONT_ASSIGN	2152	1	1	100.00
CONT_ASSIGN	2153	1	1	100.00
CONT_ASSIGN	2155	1	1	100.00
CONT_ASSIGN	2157	1	1	100.00
CONT_ASSIGN	2159	1	1	100.00
CONT_ASSIGN	2160	1	1	100.00
CONT_ASSIGN	2162	1	1	100.00
CONT_ASSIGN	2163	1	1	100.00
CONT_ASSIGN	2165	1	1	100.00
CONT_ASSIGN	2166	1	1	100.00
CONT_ASSIGN	2168	1	1	100.00
CONT_ASSIGN	2169	1	1	100.00
CONT_ASSIGN	2170	1	1	100.00
CONT_ASSIGN	2171	1	1	100.00
CONT_ASSIGN	2173	1	1	100.00
CONT_ASSIGN	2174	1	1	100.00
CONT_ASSIGN	2176	1	1	100.00
CONT_ASSIGN	2178	1	1	100.00
CONT_ASSIGN	2179	1	1	100.00
CONT_ASSIGN	2181	1	1	100.00
CONT_ASSIGN	2182	1	1	100.00
CONT_ASSIGN	2184	1	1	100.00
CONT_ASSIGN	2185	1	1	100.00
CONT_ASSIGN	2187	1	1	100.00
CONT_ASSIGN	2188	1	1	100.00
CONT_ASSIGN	2190	1	1	100.00
CONT_ASSIGN	2191	1	1	100.00
CONT_ASSIGN	2193	1	1	100.00
CONT_ASSIGN	2194	1	1	100.00
CONT_ASSIGN	2196	1	1	100.00
CONT_ASSIGN	2197	1	1	100.00
CONT_ASSIGN	2199	1	1	100.00
CONT_ASSIGN	2200	1	1	100.00
CONT_ASSIGN	2202	1	1	100.00
CONT_ASSIGN	2203	1	1	100.00
CONT_ASSIGN	2205	1	1	100.00
CONT_ASSIGN	2206	1	1	100.00
CONT_ASSIGN	2207	1	1	100.00
CONT_ASSIGN	2208	1	1	100.00
CONT_ASSIGN	2209	1	1	100.00
CONT_ASSIGN	2210	1	1	100.00
CONT_ASSIGN	2211	1	1	100.00
CONT_ASSIGN	2212	1	1	100.00
CONT_ASSIGN	2213	1	1	100.00
CONT_ASSIGN	2214	1	1	100.00
CONT_ASSIGN	2215	1	1	100.00
CONT_ASSIGN	2216	1	1	100.00
CONT_ASSIGN	2217	1	1	100.00
CONT_ASSIGN	2218	1	1	100.00
CONT_ASSIGN	2219	1	1	100.00
CONT_ASSIGN	2220	1	1	100.00
CONT_ASSIGN	2221	1	1	100.00
CONT_ASSIGN	2222	1	1	100.00
CONT_ASSIGN	2223	1	1	100.00
CONT_ASSIGN	2224	1	1	100.00
CONT_ASSIGN	2225	1	1	100.00
ALWAYS	2229	57	57	100.00
ALWAYS	2290	87	87	100.00
CONT_ASSIGN	2556	0	0
CONT_ASSIGN	2564	1	1	100.00
CONT_ASSIGN	2565	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : otp_ctrl_core_reg_top

	Total	Covered	Percent
Conditions	628	595	94.75
Logical	628	595	94.75
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
63-2049	100.00
2049-2225	89.81

---

Branch Coverage for Module : otp_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
Branches		66	66	100.00
TERNARY	2045	2	2	100.00
IF	73	3	3	100.00
TERNARY	130	2	2	100.00
IF	136	2	2	100.00
CASE	2291	57	57	100.00

2045         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

73             if (!rst_ni) begin
               -1-  
74               err_q <= '0;
                 ==>
75             end else if (intg_err || reg_we_err) begin
                        -2-  
76               err_q <= 1'b1;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
0	0	Covered	T1,T2,T3

130            reg_steer =
                          
131                tl_i.a_address[AW-1:0] inside {[2048:4095]} ? 1'd0 :
                                                               -1-  
                                                               ==>  
                                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

136            if (intg_err) begin
               -1-  
137              reg_steer = 1'd1;
                 ==>
138            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T302,T303,T304
0	Covered	T1,T2,T3

2291           unique case (1'b1)
                      -1-  
2292             addr_hit[0]: begin
2293               reg_rdata_next[0] = intr_state_otp_operation_done_qs;
                   ==>
2294               reg_rdata_next[1] = intr_state_otp_error_qs;
2295             end
2296       
2297             addr_hit[1]: begin
2298               reg_rdata_next[0] = intr_enable_otp_operation_done_qs;
                   ==>
2299               reg_rdata_next[1] = intr_enable_otp_error_qs;
2300             end
2301       
2302             addr_hit[2]: begin
2303               reg_rdata_next[0] = '0;
                   ==>
2304               reg_rdata_next[1] = '0;
2305             end
2306       
2307             addr_hit[3]: begin
2308               reg_rdata_next[0] = '0;
                   ==>
2309               reg_rdata_next[1] = '0;
2310               reg_rdata_next[2] = '0;
2311               reg_rdata_next[3] = '0;
2312               reg_rdata_next[4] = '0;
2313             end
2314       
2315             addr_hit[4]: begin
2316               reg_rdata_next[0] = status_vendor_test_error_qs;
                   ==>
2317               reg_rdata_next[1] = status_creator_sw_cfg_error_qs;
2318               reg_rdata_next[2] = status_owner_sw_cfg_error_qs;
2319               reg_rdata_next[3] = status_rot_creator_auth_codesign_error_qs;
2320               reg_rdata_next[4] = status_rot_creator_auth_state_error_qs;
2321               reg_rdata_next[5] = status_hw_cfg0_error_qs;
2322               reg_rdata_next[6] = status_hw_cfg1_error_qs;
2323               reg_rdata_next[7] = status_secret0_error_qs;
2324               reg_rdata_next[8] = status_secret1_error_qs;
2325               reg_rdata_next[9] = status_secret2_error_qs;
2326               reg_rdata_next[10] = status_life_cycle_error_qs;
2327               reg_rdata_next[11] = status_dai_error_qs;
2328               reg_rdata_next[12] = status_lci_error_qs;
2329               reg_rdata_next[13] = status_timeout_error_qs;
2330               reg_rdata_next[14] = status_lfsr_fsm_error_qs;
2331               reg_rdata_next[15] = status_scrambling_fsm_error_qs;
2332               reg_rdata_next[16] = status_key_deriv_fsm_error_qs;
2333               reg_rdata_next[17] = status_bus_integ_error_qs;
2334               reg_rdata_next[18] = status_dai_idle_qs;
2335               reg_rdata_next[19] = status_check_pending_qs;
2336             end
2337       
2338             addr_hit[5]: begin
2339               reg_rdata_next[2:0] = err_code_0_qs;
                   ==>
2340             end
2341       
2342             addr_hit[6]: begin
2343               reg_rdata_next[2:0] = err_code_1_qs;
                   ==>
2344             end
2345       
2346             addr_hit[7]: begin
2347               reg_rdata_next[2:0] = err_code_2_qs;
                   ==>
2348             end
2349       
2350             addr_hit[8]: begin
2351               reg_rdata_next[2:0] = err_code_3_qs;
                   ==>
2352             end
2353       
2354             addr_hit[9]: begin
2355               reg_rdata_next[2:0] = err_code_4_qs;
                   ==>
2356             end
2357       
2358             addr_hit[10]: begin
2359               reg_rdata_next[2:0] = err_code_5_qs;
                   ==>
2360             end
2361       
2362             addr_hit[11]: begin
2363               reg_rdata_next[2:0] = err_code_6_qs;
                   ==>
2364             end
2365       
2366             addr_hit[12]: begin
2367               reg_rdata_next[2:0] = err_code_7_qs;
                   ==>
2368             end
2369       
2370             addr_hit[13]: begin
2371               reg_rdata_next[2:0] = err_code_8_qs;
                   ==>
2372             end
2373       
2374             addr_hit[14]: begin
2375               reg_rdata_next[2:0] = err_code_9_qs;
                   ==>
2376             end
2377       
2378             addr_hit[15]: begin
2379               reg_rdata_next[2:0] = err_code_10_qs;
                   ==>
2380             end
2381       
2382             addr_hit[16]: begin
2383               reg_rdata_next[2:0] = err_code_11_qs;
                   ==>
2384             end
2385       
2386             addr_hit[17]: begin
2387               reg_rdata_next[2:0] = err_code_12_qs;
                   ==>
2388             end
2389       
2390             addr_hit[18]: begin
2391               reg_rdata_next[0] = direct_access_regwen_qs;
                   ==>
2392             end
2393       
2394             addr_hit[19]: begin
2395               reg_rdata_next[0] = '0;
                   ==>
2396               reg_rdata_next[1] = '0;
2397               reg_rdata_next[2] = '0;
2398             end
2399       
2400             addr_hit[20]: begin
2401               reg_rdata_next[10:0] = direct_access_address_qs;
                   ==>
2402             end
2403       
2404             addr_hit[21]: begin
2405               reg_rdata_next[31:0] = direct_access_wdata_0_qs;
                   ==>
2406             end
2407       
2408             addr_hit[22]: begin
2409               reg_rdata_next[31:0] = direct_access_wdata_1_qs;
                   ==>
2410             end
2411       
2412             addr_hit[23]: begin
2413               reg_rdata_next[31:0] = direct_access_rdata_0_qs;
                   ==>
2414             end
2415       
2416             addr_hit[24]: begin
2417               reg_rdata_next[31:0] = direct_access_rdata_1_qs;
                   ==>
2418             end
2419       
2420             addr_hit[25]: begin
2421               reg_rdata_next[0] = check_trigger_regwen_qs;
                   ==>
2422             end
2423       
2424             addr_hit[26]: begin
2425               reg_rdata_next[0] = '0;
                   ==>
2426               reg_rdata_next[1] = '0;
2427             end
2428       
2429             addr_hit[27]: begin
2430               reg_rdata_next[0] = check_regwen_qs;
                   ==>
2431             end
2432       
2433             addr_hit[28]: begin
2434               reg_rdata_next[31:0] = check_timeout_qs;
                   ==>
2435             end
2436       
2437             addr_hit[29]: begin
2438               reg_rdata_next[31:0] = integrity_check_period_qs;
                   ==>
2439             end
2440       
2441             addr_hit[30]: begin
2442               reg_rdata_next[31:0] = consistency_check_period_qs;
                   ==>
2443             end
2444       
2445             addr_hit[31]: begin
2446               reg_rdata_next[0] = vendor_test_read_lock_qs;
                   ==>
2447             end
2448       
2449             addr_hit[32]: begin
2450               reg_rdata_next[0] = creator_sw_cfg_read_lock_qs;
                   ==>
2451             end
2452       
2453             addr_hit[33]: begin
2454               reg_rdata_next[0] = owner_sw_cfg_read_lock_qs;
                   ==>
2455             end
2456       
2457             addr_hit[34]: begin
2458               reg_rdata_next[0] = rot_creator_auth_codesign_read_lock_qs;
                   ==>
2459             end
2460       
2461             addr_hit[35]: begin
2462               reg_rdata_next[0] = rot_creator_auth_state_read_lock_qs;
                   ==>
2463             end
2464       
2465             addr_hit[36]: begin
2466               reg_rdata_next[31:0] = vendor_test_digest_0_qs;
                   ==>
2467             end
2468       
2469             addr_hit[37]: begin
2470               reg_rdata_next[31:0] = vendor_test_digest_1_qs;
                   ==>
2471             end
2472       
2473             addr_hit[38]: begin
2474               reg_rdata_next[31:0] = creator_sw_cfg_digest_0_qs;
                   ==>
2475             end
2476       
2477             addr_hit[39]: begin
2478               reg_rdata_next[31:0] = creator_sw_cfg_digest_1_qs;
                   ==>
2479             end
2480       
2481             addr_hit[40]: begin
2482               reg_rdata_next[31:0] = owner_sw_cfg_digest_0_qs;
                   ==>
2483             end
2484       
2485             addr_hit[41]: begin
2486               reg_rdata_next[31:0] = owner_sw_cfg_digest_1_qs;
                   ==>
2487             end
2488       
2489             addr_hit[42]: begin
2490               reg_rdata_next[31:0] = rot_creator_auth_codesign_digest_0_qs;
                   ==>
2491             end
2492       
2493             addr_hit[43]: begin
2494               reg_rdata_next[31:0] = rot_creator_auth_codesign_digest_1_qs;
                   ==>
2495             end
2496       
2497             addr_hit[44]: begin
2498               reg_rdata_next[31:0] = rot_creator_auth_state_digest_0_qs;
                   ==>
2499             end
2500       
2501             addr_hit[45]: begin
2502               reg_rdata_next[31:0] = rot_creator_auth_state_digest_1_qs;
                   ==>
2503             end
2504       
2505             addr_hit[46]: begin
2506               reg_rdata_next[31:0] = hw_cfg0_digest_0_qs;
                   ==>
2507             end
2508       
2509             addr_hit[47]: begin
2510               reg_rdata_next[31:0] = hw_cfg0_digest_1_qs;
                   ==>
2511             end
2512       
2513             addr_hit[48]: begin
2514               reg_rdata_next[31:0] = hw_cfg1_digest_0_qs;
                   ==>
2515             end
2516       
2517             addr_hit[49]: begin
2518               reg_rdata_next[31:0] = hw_cfg1_digest_1_qs;
                   ==>
2519             end
2520       
2521             addr_hit[50]: begin
2522               reg_rdata_next[31:0] = secret0_digest_0_qs;
                   ==>
2523             end
2524       
2525             addr_hit[51]: begin
2526               reg_rdata_next[31:0] = secret0_digest_1_qs;
                   ==>
2527             end
2528       
2529             addr_hit[52]: begin
2530               reg_rdata_next[31:0] = secret1_digest_0_qs;
                   ==>
2531             end
2532       
2533             addr_hit[53]: begin
2534               reg_rdata_next[31:0] = secret1_digest_1_qs;
                   ==>
2535             end
2536       
2537             addr_hit[54]: begin
2538               reg_rdata_next[31:0] = secret2_digest_0_qs;
                   ==>
2539             end
2540       
2541             addr_hit[55]: begin
2542               reg_rdata_next[31:0] = secret2_digest_1_qs;
                   ==>
2543             end
2544       
2545             default: begin
2546               reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T10
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T10
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T10
addr_hit[26]	Covered	T1,T2,T10
addr_hit[27]	Covered	T1,T2,T10
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T10
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T10
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T10
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T10
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T1,T2,T3
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T1,T2,T3
addr_hit[43]	Covered	T1,T2,T10
addr_hit[44]	Covered	T1,T2,T3
addr_hit[45]	Covered	T1,T2,T3
addr_hit[46]	Covered	T1,T2,T3
addr_hit[47]	Covered	T1,T2,T10
addr_hit[48]	Covered	T1,T2,T3
addr_hit[49]	Covered	T1,T2,T3
addr_hit[50]	Covered	T1,T2,T3
addr_hit[51]	Covered	T1,T2,T10
addr_hit[52]	Covered	T1,T2,T3
addr_hit[53]	Covered	T1,T2,T10
addr_hit[54]	Covered	T1,T2,T10
addr_hit[55]	Covered	T1,T2,T10
default	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_core_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	83832030	6558108	0	0
reAfterRv	83832030	6558108	0	0
rePulse	83832030	5669915	0	0
wePulse	83832030	888193	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	6558108	0	0
T1	5511	19	0	0
T2	12159	590	0	0
T3	13200	689	0	0
T4	24822	849	0	0
T6	7902	936	0	0
T10	6437	78	0	0
T11	10342	1153	0	0
T12	7144	92	0	0
T13	13944	454	0	0
T14	9797	461	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	6558108	0	0
T1	5511	19	0	0
T2	12159	590	0	0
T3	13200	689	0	0
T4	24822	849	0	0
T6	7902	936	0	0
T10	6437	78	0	0
T11	10342	1153	0	0
T12	7144	92	0	0
T13	13944	454	0	0
T14	9797	461	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	5669915	0	0
T1	5511	4	0	0
T2	12159	565	0	0
T3	13200	432	0	0
T4	24822	746	0	0
T6	7902	762	0	0
T10	6437	1	0	0
T11	10342	875	0	0
T12	7144	1	0	0
T13	13944	395	0	0
T14	9797	381	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	83832030	888193	0	0
T1	5511	15	0	0
T2	12159	25	0	0
T3	13200	257	0	0
T4	24822	103	0	0
T6	7902	174	0	0
T10	6437	77	0	0
T11	10342	278	0	0
T12	7144	91	0	0
T13	13944	59	0	0
T14	9797	80	0	0