Module Definition
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Module : prim_secded_inv_72_64_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 69.12 69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 69.12 69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 69.12 69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 71.32 71.32
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 72.06 72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 74.63 74.63
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 75.00 75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 77.94 77.94
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 77.94 77.94
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 80.88 80.88
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 80.88 80.88
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.32 71.32


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.32 71.32


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.06 72.06


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.06 72.06


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.63 74.63


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.63 74.63


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.94 77.94


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.94 77.94


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.94 77.94


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.94 77.94


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.88 80.88


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.88 80.88


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.88 80.88


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.88 80.88


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T95,T151,T129 Yes T95,T151,T129 INPUT
data_o[63:0] Yes Yes T95,T151,T129 Yes T95,T151,T129 OUTPUT
syndrome_o[2:0] Yes Yes T103,T104,T200 Yes T103,T104,T200 OUTPUT
syndrome_o[7:3] No No No OUTPUT
err_o[0] Yes Yes *T103,*T104,*T200 Yes T103,T104,T200 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 188 69.12
Total Bits 0->1 136 94 69.12
Total Bits 1->0 136 94 69.12

Ports 2 0 0.00
Port Bits 272 188 69.12
Port Bits 0->1 136 94 69.12
Port Bits 1->0 136 94 69.12

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] Yes Yes T95,T129,T89 Yes T95,T129,T89 INPUT
data_i[3:2] No No No INPUT
data_i[8:4] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[9] No No No INPUT
data_i[11:10] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[12] No No No INPUT
data_i[19:13] Yes Yes *T95,*T129,*T89 Yes T95,T129,T89 INPUT
data_i[20] No No No INPUT
data_i[22:21] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[24:23] No No No INPUT
data_i[25] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[26] No No No INPUT
data_i[28:27] Yes Yes T129,T89,*T18 Yes T129,T89,T18 INPUT
data_i[29] No No No INPUT
data_i[30] Yes Yes *T129,*T89,*T18 Yes T129,T89,T18 INPUT
data_i[31] No No No INPUT
data_i[33:32] Yes Yes T95,T129,T89 Yes T95,T129,T89 INPUT
data_i[35:34] No No No INPUT
data_i[39:36] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[43:40] No No No INPUT
data_i[46:44] Yes Yes T95,T129,T89 Yes T95,T129,T89 INPUT
data_i[47] No No No INPUT
data_i[51:48] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[53:52] No No No INPUT
data_i[59:54] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[61:60] No No No INPUT
data_i[71:62] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_o[1:0] Yes Yes T95,T129,T89 Yes T95,T129,T89 OUTPUT
data_o[3:2] No No No OUTPUT
data_o[8:4] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[9] No No No OUTPUT
data_o[11:10] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[12] No No No OUTPUT
data_o[19:13] Yes Yes *T95,*T129,*T89 Yes T95,T129,T89 OUTPUT
data_o[20] No No No OUTPUT
data_o[22:21] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[24:23] No No No OUTPUT
data_o[25] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[26] No No No OUTPUT
data_o[28:27] Yes Yes T129,T89,*T18 Yes T129,T89,T18 OUTPUT
data_o[29] No No No OUTPUT
data_o[30] Yes Yes *T129,*T89,*T18 Yes T129,T89,T18 OUTPUT
data_o[31] No No No OUTPUT
data_o[33:32] Yes Yes T95,T129,T89 Yes T95,T129,T89 OUTPUT
data_o[35:34] No No No OUTPUT
data_o[39:36] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[43:40] No No No OUTPUT
data_o[46:44] Yes Yes T95,T129,T89 Yes T95,T129,T89 OUTPUT
data_o[47] No No No OUTPUT
data_o[51:48] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[53:52] No No No OUTPUT
data_o[59:54] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[61:60] No No No OUTPUT
data_o[63:62] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 188 69.12
Total Bits 0->1 136 94 69.12
Total Bits 1->0 136 94 69.12

Ports 2 0 0.00
Port Bits 272 188 69.12
Port Bits 0->1 136 94 69.12
Port Bits 1->0 136 94 69.12

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[6:0] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[7] No No No INPUT
data_i[10:8] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[13:11] No No No INPUT
data_i[14] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[15] No No No INPUT
data_i[18:16] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[19] No No No INPUT
data_i[22:20] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[23] No No No INPUT
data_i[25:24] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[26] No No No INPUT
data_i[30:27] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[31] No No No INPUT
data_i[33:32] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[34] No No No INPUT
data_i[35] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[36] No No No INPUT
data_i[39:37] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[40] No No No INPUT
data_i[42:41] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[43] No No No INPUT
data_i[44] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[47:45] No No No INPUT
data_i[49:48] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[50] No No No INPUT
data_i[51] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[52] No No No INPUT
data_i[57:53] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[58] No No No INPUT
data_i[59] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[60] No No No INPUT
data_i[61] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[62] No No No INPUT
data_i[71:63] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_o[6:0] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[7] No No No OUTPUT
data_o[10:8] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[13:11] No No No OUTPUT
data_o[14] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[15] No No No OUTPUT
data_o[18:16] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[19] No No No OUTPUT
data_o[22:20] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[23] No No No OUTPUT
data_o[25:24] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[26] No No No OUTPUT
data_o[30:27] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[31] No No No OUTPUT
data_o[33:32] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[34] No No No OUTPUT
data_o[35] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[36] No No No OUTPUT
data_o[39:37] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[40] No No No OUTPUT
data_o[42:41] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[43] No No No OUTPUT
data_o[44] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[47:45] No No No OUTPUT
data_o[49:48] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[50] No No No OUTPUT
data_o[51] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[52] No No No OUTPUT
data_o[57:53] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[58] No No No OUTPUT
data_o[59] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[60] No No No OUTPUT
data_o[61] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[62] No No No OUTPUT
data_o[63] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 188 69.12
Total Bits 0->1 136 94 69.12
Total Bits 1->0 136 94 69.12

Ports 2 0 0.00
Port Bits 272 188 69.12
Port Bits 0->1 136 94 69.12
Port Bits 1->0 136 94 69.12

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[2] No No No INPUT
data_i[5:3] Yes Yes T4,*T13,T5 Yes T4,T13,T5 INPUT
data_i[6] No No No INPUT
data_i[9:7] Yes Yes T4,T5,T95 Yes T4,T5,T95 INPUT
data_i[12:10] No No No INPUT
data_i[13] Yes Yes *T4,*T5,*T95 Yes T4,T5,T95 INPUT
data_i[14] No No No INPUT
data_i[15] Yes Yes *T4,*T5,*T95 Yes T4,T5,T95 INPUT
data_i[16] No No No INPUT
data_i[23:17] Yes Yes T4,*T13,T5 Yes T4,T13,T5 INPUT
data_i[24] No No No INPUT
data_i[26:25] Yes Yes T4,*T13,T5 Yes T4,T13,T5 INPUT
data_i[27] No No No INPUT
data_i[29:28] Yes Yes T4,*T13,T5 Yes T4,T13,T5 INPUT
data_i[30] No No No INPUT
data_i[33:31] Yes Yes T4,T5,T95 Yes T4,T5,T95 INPUT
data_i[34] No No No INPUT
data_i[35] Yes Yes *T4,*T5,*T95 Yes T4,T5,T95 INPUT
data_i[36] No No No INPUT
data_i[37] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[38] No No No INPUT
data_i[40:39] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[41] No No No INPUT
data_i[43:42] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[44] No No No INPUT
data_i[46:45] Yes Yes T4,T5,T95 Yes T4,T5,T95 INPUT
data_i[47] No No No INPUT
data_i[48] Yes Yes *T4,*T5,*T95 Yes T4,T5,T95 INPUT
data_i[49] No No No INPUT
data_i[51:50] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[54:52] No No No INPUT
data_i[57:55] Yes Yes T4,*T13,T5 Yes T4,T13,T5 INPUT
data_i[58] No No No INPUT
data_i[71:59] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_o[1:0] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[2] No No No OUTPUT
data_o[5:3] Yes Yes T4,*T13,T5 Yes T4,T13,T5 OUTPUT
data_o[6] No No No OUTPUT
data_o[9:7] Yes Yes T4,T5,T95 Yes T4,T5,T95 OUTPUT
data_o[12:10] No No No OUTPUT
data_o[13] Yes Yes *T4,*T5,*T95 Yes T4,T5,T95 OUTPUT
data_o[14] No No No OUTPUT
data_o[15] Yes Yes *T4,*T5,*T95 Yes T4,T5,T95 OUTPUT
data_o[16] No No No OUTPUT
data_o[23:17] Yes Yes T4,*T13,T5 Yes T4,T13,T5 OUTPUT
data_o[24] No No No OUTPUT
data_o[26:25] Yes Yes T4,*T13,T5 Yes T4,T13,T5 OUTPUT
data_o[27] No No No OUTPUT
data_o[29:28] Yes Yes T4,*T13,T5 Yes T4,T13,T5 OUTPUT
data_o[30] No No No OUTPUT
data_o[33:31] Yes Yes T4,T5,T95 Yes T4,T5,T95 OUTPUT
data_o[34] No No No OUTPUT
data_o[35] Yes Yes *T4,*T5,*T95 Yes T4,T5,T95 OUTPUT
data_o[36] No No No OUTPUT
data_o[37] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[38] No No No OUTPUT
data_o[40:39] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[41] No No No OUTPUT
data_o[43:42] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[44] No No No OUTPUT
data_o[46:45] Yes Yes T4,T5,T95 Yes T4,T5,T95 OUTPUT
data_o[47] No No No OUTPUT
data_o[48] Yes Yes *T4,*T5,*T95 Yes T4,T5,T95 OUTPUT
data_o[49] No No No OUTPUT
data_o[51:50] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[54:52] No No No OUTPUT
data_o[57:55] Yes Yes T4,*T13,T5 Yes T4,T13,T5 OUTPUT
data_o[58] No No No OUTPUT
data_o[63:59] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 194 71.32
Total Bits 0->1 136 97 71.32
Total Bits 1->0 136 97 71.32

Ports 2 0 0.00
Port Bits 272 194 71.32
Port Bits 0->1 136 97 71.32
Port Bits 1->0 136 97 71.32

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[3:1] No No No INPUT
data_i[11:4] Yes Yes T4,*T13,T5 Yes T4,T13,T5 INPUT
data_i[12] No No No INPUT
data_i[14:13] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[15] No No No INPUT
data_i[16] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[17] No No No INPUT
data_i[22:18] Yes Yes T4,*T13,T5 Yes T4,T13,T5 INPUT
data_i[24:23] No No No INPUT
data_i[27:25] Yes Yes T4,T5,T95 Yes T4,T5,T95 INPUT
data_i[28] No No No INPUT
data_i[32:29] Yes Yes T4,*T13,T5 Yes T4,T13,T5 INPUT
data_i[33] No No No INPUT
data_i[37:34] Yes Yes T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[38] No No No INPUT
data_i[43:39] Yes Yes T4,T95,T92 Yes T4,T95,T92 INPUT
data_i[44] No No No INPUT
data_i[45] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[47:46] No No No INPUT
data_i[48] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[49] No No No INPUT
data_i[50] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[51] No No No INPUT
data_i[52] Yes Yes *T4,*T92,*T93 Yes T4,T92,T93 INPUT
data_i[54:53] No No No INPUT
data_i[59:55] Yes Yes T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[60] No No No INPUT
data_i[67:61] Yes Yes *T4,*T92,*T93 Yes T4,T92,T93 INPUT
data_i[68] No No No INPUT
data_i[71:69] Yes Yes T5,T95,T93 Yes T5,T95,T93 INPUT
data_o[0] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[3:1] No No No OUTPUT
data_o[11:4] Yes Yes T4,*T13,T5 Yes T4,T13,T5 OUTPUT
data_o[12] No No No OUTPUT
data_o[14:13] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[15] No No No OUTPUT
data_o[16] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[17] No No No OUTPUT
data_o[22:18] Yes Yes T4,*T13,T5 Yes T4,T13,T5 OUTPUT
data_o[24:23] No No No OUTPUT
data_o[27:25] Yes Yes T4,T5,T95 Yes T4,T5,T95 OUTPUT
data_o[28] No No No OUTPUT
data_o[32:29] Yes Yes T4,*T13,T5 Yes T4,T13,T5 OUTPUT
data_o[33] No No No OUTPUT
data_o[37:34] Yes Yes T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[38] No No No OUTPUT
data_o[43:39] Yes Yes T4,T95,T92 Yes T4,T95,T92 OUTPUT
data_o[44] No No No OUTPUT
data_o[45] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[47:46] No No No OUTPUT
data_o[48] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[49] No No No OUTPUT
data_o[50] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[51] No No No OUTPUT
data_o[52] Yes Yes *T4,*T92,*T93 Yes T4,T92,T93 OUTPUT
data_o[54:53] No No No OUTPUT
data_o[59:55] Yes Yes T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[60] No No No OUTPUT
data_o[63:61] Yes Yes T4,T92,T93 Yes T4,T92,T93 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 196 72.06
Total Bits 0->1 136 98 72.06
Total Bits 1->0 136 98 72.06

Ports 2 0 0.00
Port Bits 272 196 72.06
Port Bits 0->1 136 98 72.06
Port Bits 1->0 136 98 72.06

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[10:1] Yes Yes T4,T13,*T5 Yes T4,T13,T5 INPUT
data_i[12:11] No No No INPUT
data_i[14:13] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[16:15] No No No INPUT
data_i[20:17] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[22:21] No No No INPUT
data_i[24:23] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[26:25] No No No INPUT
data_i[33:27] Yes Yes *T4,T13,*T5 Yes T4,T13,T5 INPUT
data_i[34] No No No INPUT
data_i[36:35] Yes Yes *T4,T13,*T5 Yes T4,T13,T5 INPUT
data_i[37] No No No INPUT
data_i[38] Yes Yes *T13,*T95,*T92 Yes T13,T5,T95 INPUT
data_i[41:39] No No No INPUT
data_i[48:42] Yes Yes T13,T95,T92 Yes T13,T5,T95 INPUT
data_i[49] No No No INPUT
data_i[50] Yes Yes *T95,*T92,*T129 Yes T95,T92,T129 INPUT
data_i[51] No No No INPUT
data_i[53:52] Yes Yes T95,T92,T129 Yes T95,T92,T129 INPUT
data_i[54] No No No INPUT
data_i[58:55] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[60:59] No No No INPUT
data_i[71:61] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_o[0] No No No OUTPUT
data_o[10:1] Yes Yes T4,T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[12:11] No No No OUTPUT
data_o[14:13] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[16:15] No No No OUTPUT
data_o[20:17] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[22:21] No No No OUTPUT
data_o[24:23] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[26:25] No No No OUTPUT
data_o[33:27] Yes Yes *T4,T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[34] No No No OUTPUT
data_o[36:35] Yes Yes *T4,T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[37] No No No OUTPUT
data_o[38] Yes Yes *T13,*T95,*T92 Yes T13,T5,T95 OUTPUT
data_o[41:39] No No No OUTPUT
data_o[48:42] Yes Yes T13,T95,T92 Yes T13,T5,T95 OUTPUT
data_o[49] No No No OUTPUT
data_o[50] Yes Yes *T95,*T92,*T129 Yes T95,T92,T129 OUTPUT
data_o[51] No No No OUTPUT
data_o[53:52] Yes Yes T95,T92,T129 Yes T95,T92,T129 OUTPUT
data_o[54] No No No OUTPUT
data_o[58:55] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[60:59] No No No OUTPUT
data_o[63:61] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 203 74.63
Total Bits 0->1 136 102 75.00
Total Bits 1->0 136 101 74.26

Ports 2 0 0.00
Port Bits 272 203 74.63
Port Bits 0->1 136 102 75.00
Port Bits 1->0 136 101 74.26

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[2:0] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[3] No No No INPUT
data_i[6:4] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[8:7] No No No INPUT
data_i[12:9] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[13] No No No INPUT
data_i[20:14] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[21] No No No INPUT
data_i[22] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[23] No No No INPUT
data_i[36:24] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[37] No No No INPUT
data_i[38] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[40:39] No No No INPUT
data_i[43:41] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[44] No No No INPUT
data_i[49:45] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[50] No No No INPUT
data_i[51] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[52] No No No INPUT
data_i[53] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[54] No No No INPUT
data_i[55] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[57:56] No No No INPUT
data_i[60:58] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[62:61] No No No INPUT
data_i[65:63] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[66] No No Yes T294 INPUT
data_i[71:67] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_o[2:0] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[3] No No No OUTPUT
data_o[6:4] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[8:7] No No No OUTPUT
data_o[12:9] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[13] No No No OUTPUT
data_o[20:14] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[21] No No No OUTPUT
data_o[22] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[23] No No No OUTPUT
data_o[36:24] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[37] No No No OUTPUT
data_o[38] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[40:39] No No No OUTPUT
data_o[43:41] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[44] No No No OUTPUT
data_o[49:45] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[50] No No No OUTPUT
data_o[51] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[52] No No No OUTPUT
data_o[53] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[54] No No No OUTPUT
data_o[55] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[57:56] No No No OUTPUT
data_o[60:58] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[62:61] No No No OUTPUT
data_o[63] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 204 75.00
Total Bits 0->1 136 102 75.00
Total Bits 1->0 136 102 75.00

Ports 2 0 0.00
Port Bits 272 204 75.00
Port Bits 0->1 136 102 75.00
Port Bits 1->0 136 102 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[4:0] Yes Yes T4,T13,T95 Yes T4,T13,T5 INPUT
data_i[5] No No No INPUT
data_i[7:6] Yes Yes T4,T13,*T5 Yes T4,T13,T5 INPUT
data_i[8] No No No INPUT
data_i[9] Yes Yes *T4,*T13,*T95 Yes T4,T13,T5 INPUT
data_i[10] No No No INPUT
data_i[16:11] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[17] No No No INPUT
data_i[18] Yes Yes *T4,*T13,*T95 Yes T4,T13,T5 INPUT
data_i[19] No No No INPUT
data_i[21:20] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[22] No No No INPUT
data_i[29:23] Yes Yes *T4,*T13,*T95 Yes T4,T13,T5 INPUT
data_i[30] No No No INPUT
data_i[36:31] Yes Yes T4,T13,T95 Yes T4,T13,T5 INPUT
data_i[37] No No No INPUT
data_i[40:38] Yes Yes T4,T13,T95 Yes T4,T13,T5 INPUT
data_i[41] No No No INPUT
data_i[43:42] Yes Yes T4,T13,*T5 Yes T4,T13,T5 INPUT
data_i[45:44] No No No INPUT
data_i[48:46] Yes Yes T4,T13,*T5 Yes T4,T13,T5 INPUT
data_i[49] No No No INPUT
data_i[50] Yes Yes *T4,*T13,*T95 Yes T4,T13,T5 INPUT
data_i[51] No No No INPUT
data_i[52] Yes Yes *T4,*T13,*T95 Yes T4,T13,T5 INPUT
data_i[53] No No No INPUT
data_i[57:54] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[58] No No No INPUT
data_i[60:59] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[61] No No No INPUT
data_i[62] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[63] No No No INPUT
data_i[71:64] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_o[4:0] Yes Yes T4,T13,T95 Yes T4,T13,T5 OUTPUT
data_o[5] No No No OUTPUT
data_o[7:6] Yes Yes T4,T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[8] No No No OUTPUT
data_o[9] Yes Yes *T4,*T13,*T95 Yes T4,T13,T5 OUTPUT
data_o[10] No No No OUTPUT
data_o[16:11] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[17] No No No OUTPUT
data_o[18] Yes Yes *T4,*T13,*T95 Yes T4,T13,T5 OUTPUT
data_o[19] No No No OUTPUT
data_o[21:20] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[22] No No No OUTPUT
data_o[29:23] Yes Yes *T4,*T13,*T95 Yes T4,T13,T5 OUTPUT
data_o[30] No No No OUTPUT
data_o[36:31] Yes Yes T4,T13,T95 Yes T4,T13,T5 OUTPUT
data_o[37] No No No OUTPUT
data_o[40:38] Yes Yes T4,T13,T95 Yes T4,T13,T5 OUTPUT
data_o[41] No No No OUTPUT
data_o[43:42] Yes Yes T4,T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[45:44] No No No OUTPUT
data_o[48:46] Yes Yes T4,T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[49] No No No OUTPUT
data_o[50] Yes Yes *T4,*T13,*T95 Yes T4,T13,T5 OUTPUT
data_o[51] No No No OUTPUT
data_o[52] Yes Yes *T4,*T13,*T95 Yes T4,T13,T5 OUTPUT
data_o[53] No No No OUTPUT
data_o[57:54] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[58] No No No OUTPUT
data_o[60:59] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[61] No No No OUTPUT
data_o[62] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 212 77.94
Total Bits 0->1 136 106 77.94
Total Bits 1->0 136 106 77.94

Ports 2 0 0.00
Port Bits 272 212 77.94
Port Bits 0->1 136 106 77.94
Port Bits 1->0 136 106 77.94

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[5:0] Yes Yes *T108,*T4,*T13 Yes T108,T4,T13 INPUT
data_i[6] No No No INPUT
data_i[9:7] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[10] No No No INPUT
data_i[11] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[12] No No No INPUT
data_i[13] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[14] No No No INPUT
data_i[18:15] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[19] No No No INPUT
data_i[21:20] Yes Yes *T108,*T4,*T13 Yes T108,T4,T13 INPUT
data_i[22] No No No INPUT
data_i[33:23] Yes Yes *T108,*T4,*T13 Yes T108,T4,T13 INPUT
data_i[34] No No No INPUT
data_i[37:35] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[38] No No No INPUT
data_i[39] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[40] No No No INPUT
data_i[47:41] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[48] No No No INPUT
data_i[49] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[50] No No No INPUT
data_i[51] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[55:52] No No No INPUT
data_i[71:56] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_o[5:0] Yes Yes *T108,*T4,*T13 Yes T108,T4,T13 OUTPUT
data_o[6] No No No OUTPUT
data_o[9:7] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[10] No No No OUTPUT
data_o[11] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[12] No No No OUTPUT
data_o[13] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[14] No No No OUTPUT
data_o[18:15] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[19] No No No OUTPUT
data_o[21:20] Yes Yes *T108,*T4,*T13 Yes T108,T4,T13 OUTPUT
data_o[22] No No No OUTPUT
data_o[33:23] Yes Yes *T108,*T4,*T13 Yes T108,T4,T13 OUTPUT
data_o[34] No No No OUTPUT
data_o[37:35] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[38] No No No OUTPUT
data_o[39] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[40] No No No OUTPUT
data_o[47:41] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[48] No No No OUTPUT
data_o[49] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[50] No No No OUTPUT
data_o[51] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[55:52] No No No OUTPUT
data_o[63:56] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 212 77.94
Total Bits 0->1 136 106 77.94
Total Bits 1->0 136 106 77.94

Ports 2 0 0.00
Port Bits 272 212 77.94
Port Bits 0->1 136 106 77.94
Port Bits 1->0 136 106 77.94

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[1] No No No INPUT
data_i[5:2] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[7:6] No No No INPUT
data_i[13:8] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[15:14] No No No INPUT
data_i[16] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[17] No No No INPUT
data_i[19:18] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[20] No No No INPUT
data_i[30:21] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[31] No No No INPUT
data_i[42:32] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[46:43] No No No INPUT
data_i[49:47] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[50] No No No INPUT
data_i[61:51] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[63:62] No No No INPUT
data_i[71:64] Yes Yes T129,T89,T21 Yes T129,T89,T21 INPUT
data_o[0] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[1] No No No OUTPUT
data_o[5:2] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[7:6] No No No OUTPUT
data_o[13:8] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[15:14] No No No OUTPUT
data_o[16] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[17] No No No OUTPUT
data_o[19:18] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[20] No No No OUTPUT
data_o[30:21] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[31] No No No OUTPUT
data_o[42:32] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[46:43] No No No OUTPUT
data_o[49:47] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[50] No No No OUTPUT
data_o[61:51] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[63:62] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 220 80.88
Total Bits 0->1 136 110 80.88
Total Bits 1->0 136 110 80.88

Ports 2 0 0.00
Port Bits 272 220 80.88
Port Bits 0->1 136 110 80.88
Port Bits 1->0 136 110 80.88

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[3:1] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[4] No No No INPUT
data_i[6:5] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[7] No No No INPUT
data_i[8] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[9] No No No INPUT
data_i[19:10] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[20] No No No INPUT
data_i[23:21] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[24] No No No INPUT
data_i[26:25] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[27] No No No INPUT
data_i[32:28] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[35:33] No No No INPUT
data_i[42:36] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[43] No No No INPUT
data_i[48:44] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[49] No No No INPUT
data_i[52:50] Yes Yes *T4,*T13,*T95 Yes T4,T13,T5 INPUT
data_i[53] No No No INPUT
data_i[71:54] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_o[0] No No No OUTPUT
data_o[3:1] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[4] No No No OUTPUT
data_o[6:5] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[7] No No No OUTPUT
data_o[8] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[9] No No No OUTPUT
data_o[19:10] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[20] No No No OUTPUT
data_o[23:21] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[24] No No No OUTPUT
data_o[26:25] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[27] No No No OUTPUT
data_o[32:28] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[35:33] No No No OUTPUT
data_o[42:36] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[43] No No No OUTPUT
data_o[48:44] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[49] No No No OUTPUT
data_o[52:50] Yes Yes *T4,*T13,*T95 Yes T4,T13,T5 OUTPUT
data_o[53] No No No OUTPUT
data_o[63:54] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 220 80.88
Total Bits 0->1 136 110 80.88
Total Bits 1->0 136 110 80.88

Ports 2 0 0.00
Port Bits 272 220 80.88
Port Bits 0->1 136 110 80.88
Port Bits 1->0 136 110 80.88

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[2:1] No No No INPUT
data_i[6:3] Yes Yes T4,T5,T95 Yes T4,T5,T95 INPUT
data_i[7] No No No INPUT
data_i[9:8] Yes Yes T4,T5,T95 Yes T4,T5,T95 INPUT
data_i[10] No No No INPUT
data_i[11] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[13:12] No No No INPUT
data_i[24:14] Yes Yes *T4,*T5,*T95 Yes T4,T5,T95 INPUT
data_i[25] No No No INPUT
data_i[26] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[28:27] No No No INPUT
data_i[32:29] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_i[33] No No No INPUT
data_i[40:34] Yes Yes T4,*T13,T5 Yes T4,T13,T5 INPUT
data_i[41] No No No INPUT
data_i[45:42] Yes Yes *T110,*T4,*T13 Yes T110,T4,T13 INPUT
data_i[46] No No No INPUT
data_i[50:47] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 INPUT
data_i[51] No No No INPUT
data_i[71:52] Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
data_o[0] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[2:1] No No No OUTPUT
data_o[6:3] Yes Yes T4,T5,T95 Yes T4,T5,T95 OUTPUT
data_o[7] No No No OUTPUT
data_o[9:8] Yes Yes T4,T5,T95 Yes T4,T5,T95 OUTPUT
data_o[10] No No No OUTPUT
data_o[11] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[13:12] No No No OUTPUT
data_o[24:14] Yes Yes *T4,*T5,*T95 Yes T4,T5,T95 OUTPUT
data_o[25] No No No OUTPUT
data_o[26] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[28:27] No No No OUTPUT
data_o[32:29] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
data_o[33] No No No OUTPUT
data_o[40:34] Yes Yes T4,*T13,T5 Yes T4,T13,T5 OUTPUT
data_o[41] No No No OUTPUT
data_o[45:42] Yes Yes *T110,*T4,*T13 Yes T110,T4,T13 OUTPUT
data_o[46] No No No OUTPUT
data_o[50:47] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
data_o[51] No No No OUTPUT
data_o[63:52] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T129,T89,T21 Yes T129,T89,T21 INPUT
data_o[63:0] Yes Yes T129,T89,T21 Yes T129,T89,T21 OUTPUT
syndrome_o[2:0] Yes Yes T187 Yes T187 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T187 Yes T187 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T20,T21,T119 Yes T20,T21,T119 INPUT
data_o[63:0] Yes Yes T20,T21,T119 Yes T20,T21,T119 OUTPUT
syndrome_o[2:0] Yes Yes T187,T192 Yes T187,T192 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T187,*T192 Yes T187,T192 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T95,T151,T89 Yes T95,T151,T89 INPUT
data_o[63:0] Yes Yes T95,T151,T89 Yes T95,T151,T89 OUTPUT
syndrome_o[2:0] Yes Yes T187,T193 Yes T187,T193 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T187,*T193 Yes T187,T193 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T128,T89,T166 Yes T128,T89,T166 INPUT
data_o[63:0] Yes Yes T128,T89,T166 Yes T128,T89,T166 OUTPUT
syndrome_o[2:0] Yes Yes T103,T104,T187 Yes T103,T104,T187 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T103,*T104,*T187 Yes T103,T104,T187 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T20,T128,T21 Yes T20,T128,T21 INPUT
data_o[63:0] Yes Yes T20,T128,T21 Yes T20,T128,T21 OUTPUT
syndrome_o[7:0] Excluded Excluded T104,T200,T192 Excluded T104,T200,T192 OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded T104,T200,T192 Excluded T104,T200,T192 OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T102,T149,T263 Yes T102,T149,T263 INPUT
data_o[63:0] Yes Yes T102,T149,T263 Yes T102,T149,T263 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T22,T124,T295 Yes T22,T124,T295 INPUT
data_o[63:0] Yes Yes T22,T124,T295 Yes T22,T124,T295 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T99,T87,T296 Yes T118,T99,T87 INPUT
data_o[63:0] Yes Yes T99,T87,T296 Yes T118,T99,T87 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T95,T20,T89 Yes T95,T20,T89 INPUT
data_o[63:0] Yes Yes T95,T20,T89 Yes T95,T20,T89 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T95,T128,T125 Yes T95,T128,T120 INPUT
data_o[63:0] Yes Yes T95,T128,T125 Yes T95,T128,T120 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T95,T99,T83 Yes T95,T99,T83 INPUT
data_o[63:0] Yes Yes T95,T99,T83 Yes T95,T99,T83 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T130,T261,T297 Yes T130,T231,T298 INPUT
data_o[63:0] Yes Yes T130,T261,T297 Yes T130,T231,T298 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T89,T130,T185 Yes T89,T130,T185 INPUT
data_o[63:0] Yes Yes T89,T130,T185 Yes T89,T130,T185 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T20,T36,T89 Yes T5,T35,T20 INPUT
data_o[63:0] Yes Yes T20,T36,T89 Yes T5,T35,T20 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T5,T95,T20 Yes T5,T95,T20 INPUT
data_o[63:0] Yes Yes T5,T95,T20 Yes T5,T95,T20 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T95,T20,T36 Yes T5,T95,T137 INPUT
data_o[63:0] Yes Yes T95,T20,T36 Yes T5,T95,T137 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T11,T5 Yes T4,T11,T5 INPUT
data_o[63:0] Yes Yes T4,T11,T5 Yes T4,T11,T5 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T11,T20,T36 Yes T11,T20,T36 INPUT
data_o[63:0] Yes Yes T11,T20,T36 Yes T11,T20,T36 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T128,T119,T99 Yes T128,T119,T99 INPUT
data_o[63:0] Yes Yes T128,T119,T99 Yes T128,T119,T99 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T20,T36,T120 Yes T20,T36,T120 INPUT
data_o[63:0] Yes Yes T20,T36,T120 Yes T20,T36,T120 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T5,T119,T99 Yes T5,T128,T119 INPUT
data_o[63:0] Yes Yes T5,T119,T99 Yes T5,T128,T119 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T5,T92 Yes T2,T6,T5 INPUT
data_o[63:0] Yes Yes T2,T5,T92 Yes T2,T6,T5 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T95,T92 Yes T2,T95,T34 INPUT
data_o[63:0] Yes Yes T2,T95,T92 Yes T2,T95,T34 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%