Unified Coverage Report :: Module :: prim_generic_ram_1p

Module : prim_generic_ram_1p

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.85	96.55				100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic	98.85	96.55				100.00	100.00

---

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.85	96.55				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.85	96.55				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_ram_1p

	Line No.	Total	Covered	Percent
TOTAL		29	28	96.55
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         22/22            assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T1 T2 T3 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T1 T2 T3 
66         1/1                    if (wmask[i]) begin
           Tests:       T1 T2 T3 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T1 T2 T3 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T1 T2 T3 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1p

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1p

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	23	23	100.00	23	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	23	23	100.00	23	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1109	1109	0	0
gen_wmask[0].MaskCheck_A	96891327	587318	0	0
gen_wmask[10].MaskCheck_A	96891327	587318	0	0
gen_wmask[11].MaskCheck_A	96891327	587318	0	0
gen_wmask[12].MaskCheck_A	96891327	587318	0	0
gen_wmask[13].MaskCheck_A	96891327	587318	0	0
gen_wmask[14].MaskCheck_A	96891327	587318	0	0
gen_wmask[15].MaskCheck_A	96891327	587318	0	0
gen_wmask[16].MaskCheck_A	96891327	587318	0	0
gen_wmask[17].MaskCheck_A	96891327	587318	0	0
gen_wmask[18].MaskCheck_A	96891327	587318	0	0
gen_wmask[19].MaskCheck_A	96891327	587318	0	0
gen_wmask[1].MaskCheck_A	96891327	587318	0	0
gen_wmask[20].MaskCheck_A	96891327	587318	0	0
gen_wmask[21].MaskCheck_A	96891327	587318	0	0
gen_wmask[2].MaskCheck_A	96891327	587318	0	0
gen_wmask[3].MaskCheck_A	96891327	587318	0	0
gen_wmask[4].MaskCheck_A	96891327	587318	0	0
gen_wmask[5].MaskCheck_A	96891327	587318	0	0
gen_wmask[6].MaskCheck_A	96891327	587318	0	0
gen_wmask[7].MaskCheck_A	96891327	587318	0	0
gen_wmask[8].MaskCheck_A	96891327	587318	0	0
gen_wmask[9].MaskCheck_A	96891327	587318	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109	1109	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[10].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[11].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[12].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[13].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[14].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[15].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[16].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[17].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[18].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[19].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[1].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[20].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[21].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[2].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[3].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[4].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[5].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[6].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[7].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[8].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0

gen_wmask[9].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96891327	587318	0	0
T1	4805	6	0	0
T2	9382	54	0	0
T3	25763	192	0	0
T4	19451	30	0	0
T5	30220	198	0	0
T6	34353	34	0	0
T7	3400	0	0	0
T14	0	64	0	0
T15	0	492	0	0
T22	21489	0	0	0
T23	10982	56	0	0
T24	16454	96	0	0