Unified Coverage Report :: Module :: prim_secded_inv_72_64_dec

Module : prim_secded_inv_72_64_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	69.12			69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	69.12			69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	69.12			69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	70.59			70.59
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	70.59			70.59
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	72.06			72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	72.06			72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	73.53			73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	73.53			73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	77.94			77.94
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	80.88			80.88
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	97.14			97.14
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.12			69.12

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.12			69.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.12			69.12

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.12			69.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.12			69.12

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.12			69.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.94			77.94

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.94			77.94

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.88			80.88

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.88			80.88

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T6,T15,T114	Yes	T6,T15,T114	INPUT
data_o[63:0]	Yes	Yes	T6,T15,T114	Yes	T6,T15,T114	OUTPUT
syndrome_o[2:0]	Yes	Yes	T101,T149,T150	Yes	T101,T149,T150	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T101,*T149,*T150	Yes	T101,T149,T150	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	188	69.12
Total Bits 0->1	136	94	69.12
Total Bits 1->0	136	94	69.12

Ports	2	0	0.00
Port Bits	272	188	69.12
Port Bits 0->1	136	94	69.12
Port Bits 1->0	136	94	69.12

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[3]	No	No		No		INPUT
data_i[6:4]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[7]	No	No		No		INPUT
data_i[11:8]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[12]	No	No		No		INPUT
data_i[13]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[16:14]	No	No		No		INPUT
data_i[18:17]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[19]	No	No		No		INPUT
data_i[23:20]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[24]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T15,*T90,*T94	Yes	T5,T15,T90	INPUT
data_i[26]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T15,T90,T94	Yes	T5,T15,T90	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[31]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[32]	No	No		No		INPUT
data_i[33]	Yes	Yes	*T15,*T9,*T90	Yes	T5,T15,T9	INPUT
data_i[35:34]	No	No		No		INPUT
data_i[42:36]	Yes	Yes	T15,T9,T90	Yes	T5,T15,T9	INPUT
data_i[43]	No	No		No		INPUT
data_i[44]	Yes	Yes	*T15,*T9,*T90	Yes	T5,T15,T9	INPUT
data_i[45]	No	No		No		INPUT
data_i[54:46]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[55]	No	No		No		INPUT
data_i[56]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[59:57]	No	No		No		INPUT
data_i[62:60]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T15,T9,T90	Yes	T5,T15,T9	INPUT
data_o[2:0]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[6:4]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[11:8]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[12]	No	No		No		OUTPUT
data_o[13]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[16:14]	No	No		No		OUTPUT
data_o[18:17]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[23:20]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T15,*T90,*T94	Yes	T5,T15,T90	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T15,T90,T94	Yes	T5,T15,T90	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[31]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[33]	Yes	Yes	*T15,*T9,*T90	Yes	T5,T15,T9	OUTPUT
data_o[35:34]	No	No		No		OUTPUT
data_o[42:36]	Yes	Yes	T15,T9,T90	Yes	T5,T15,T9	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[44]	Yes	Yes	*T15,*T9,*T90	Yes	T5,T15,T9	OUTPUT
data_o[45]	No	No		No		OUTPUT
data_o[54:46]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[56]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[59:57]	No	No		No		OUTPUT
data_o[62:60]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	188	69.12
Total Bits 0->1	136	94	69.12
Total Bits 1->0	136	94	69.12

Ports	2	0	0.00
Port Bits	272	188	69.12
Port Bits 0->1	136	94	69.12
Port Bits 1->0	136	94	69.12

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	INPUT
data_i[2]	No	No		No		INPUT
data_i[6:3]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[12:9]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	INPUT
data_i[13]	No	No		No		INPUT
data_i[14]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[15]	No	No		No		INPUT
data_i[18:16]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[20:19]	No	No		No		INPUT
data_i[22:21]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[23]	No	No		No		INPUT
data_i[28:24]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[29]	No	No		No		INPUT
data_i[30]	Yes	Yes	*T114,*T119,*T85	Yes	T3,T114,T119	INPUT
data_i[31]	No	No		No		INPUT
data_i[37:32]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[40:38]	No	No		No		INPUT
data_i[42:41]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[44:43]	No	No		No		INPUT
data_i[49:45]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[50]	No	No		No		INPUT
data_i[51]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[53:52]	No	No		No		INPUT
data_i[55:54]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	INPUT
data_i[56]	No	No		No		INPUT
data_i[57]	Yes	Yes	*T114,*T119,*T85	Yes	T3,T114,T119	INPUT
data_i[58]	No	No		No		INPUT
data_i[59]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[60]	No	No		No		INPUT
data_i[71:61]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	INPUT
data_o[1:0]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[6:3]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[12:9]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[14]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[18:16]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[20:19]	No	No		No		OUTPUT
data_o[22:21]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[28:24]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[30]	Yes	Yes	*T114,*T119,*T85	Yes	T3,T114,T119	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[37:32]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[40:38]	No	No		No		OUTPUT
data_o[42:41]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[44:43]	No	No		No		OUTPUT
data_o[49:45]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[51]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[53:52]	No	No		No		OUTPUT
data_o[55:54]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[57]	Yes	Yes	*T114,*T119,*T85	Yes	T3,T114,T119	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[59]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[63:61]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	188	69.12
Total Bits 0->1	136	94	69.12
Total Bits 1->0	136	94	69.12

Ports	2	0	0.00
Port Bits	272	188	69.12
Port Bits 0->1	136	94	69.12
Port Bits 1->0	136	94	69.12

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	No	No		No		INPUT
data_i[11:3]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	INPUT
data_i[13:12]	No	No		No		INPUT
data_i[18:14]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[19]	No	No		No		INPUT
data_i[20]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[21]	No	No		No		INPUT
data_i[25:22]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[26]	No	No		No		INPUT
data_i[27]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[28]	No	No		No		INPUT
data_i[33:29]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[34]	No	No		No		INPUT
data_i[41:35]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	INPUT
data_i[43:42]	No	No		No		INPUT
data_i[45:44]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[47:46]	No	No		No		INPUT
data_i[48]	Yes	Yes	*T114,*T119,*T85	Yes	T3,T114,T119	INPUT
data_i[49]	No	No		No		INPUT
data_i[52:50]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[53]	No	No		No		INPUT
data_i[55:54]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	INPUT
data_i[56]	No	No		No		INPUT
data_i[58:57]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	INPUT
data_i[59]	No	No		No		INPUT
data_i[60]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[63:61]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T123,T140,T196	Yes	T123,T140,T196	INPUT
data_o[2:0]	No	No		No		OUTPUT
data_o[11:3]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	OUTPUT
data_o[13:12]	No	No		No		OUTPUT
data_o[18:14]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[20]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[21]	No	No		No		OUTPUT
data_o[25:22]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[27]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[33:29]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[34]	No	No		No		OUTPUT
data_o[41:35]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	OUTPUT
data_o[43:42]	No	No		No		OUTPUT
data_o[45:44]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[47:46]	No	No		No		OUTPUT
data_o[48]	Yes	Yes	*T114,*T119,*T85	Yes	T3,T114,T119	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[52:50]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[55:54]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[58:57]	Yes	Yes	T114,T119,T85	Yes	T3,T114,T119	OUTPUT
data_o[59]	No	No		No		OUTPUT
data_o[60]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[63:61]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	192	70.59
Total Bits 0->1	136	96	70.59
Total Bits 1->0	136	96	70.59

Ports	2	0	0.00
Port Bits	272	192	70.59
Port Bits 0->1	136	96	70.59
Port Bits 1->0	136	96	70.59

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[1]	No	No		No		INPUT
data_i[3:2]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[5:4]	No	No		No		INPUT
data_i[11:6]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[12]	No	No		No		INPUT
data_i[13]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[14]	No	No		No		INPUT
data_i[18:15]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[20:19]	No	No		No		INPUT
data_i[22:21]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[25:23]	No	No		No		INPUT
data_i[27:26]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	INPUT
data_i[29:28]	No	No		No		INPUT
data_i[31:30]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[32]	No	No		No		INPUT
data_i[33]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[34]	No	No		No		INPUT
data_i[37:35]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	INPUT
data_i[38]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[40]	No	No		No		INPUT
data_i[48:41]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[49]	No	No		No		INPUT
data_i[53:50]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	INPUT
data_i[54]	No	No		No		INPUT
data_i[55]	Yes	Yes	*T15,*T114,*T119	Yes	T5,T14,T15	INPUT
data_i[56]	No	No		No		INPUT
data_i[60:57]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	INPUT
data_o[0]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[3:2]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[5:4]	No	No		No		OUTPUT
data_o[11:6]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[12]	No	No		No		OUTPUT
data_o[13]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[18:15]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[20:19]	No	No		No		OUTPUT
data_o[22:21]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[25:23]	No	No		No		OUTPUT
data_o[27:26]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	OUTPUT
data_o[29:28]	No	No		No		OUTPUT
data_o[31:30]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[33]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[34]	No	No		No		OUTPUT
data_o[37:35]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[48:41]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[53:50]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[55]	Yes	Yes	*T15,*T114,*T119	Yes	T5,T14,T15	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[60:57]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	192	70.59
Total Bits 0->1	136	96	70.59
Total Bits 1->0	136	96	70.59

Ports	2	0	0.00
Port Bits	272	192	70.59
Port Bits 0->1	136	96	70.59
Port Bits 1->0	136	96	70.59

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T119,*T85,*T88	Yes	T119,T85,T125	INPUT
data_i[1]	No	No		No		INPUT
data_i[2]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[3]	No	No		No		INPUT
data_i[4]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[5]	No	No		No		INPUT
data_i[11:6]	Yes	Yes	T119,T85,T88	Yes	T119,T85,T125	INPUT
data_i[13:12]	No	No		No		INPUT
data_i[16:14]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[17]	No	No		No		INPUT
data_i[19:18]	Yes	Yes	T85,T88,T9	Yes	T85,T88,T9	INPUT
data_i[20]	No	No		No		INPUT
data_i[21]	Yes	Yes	*T85,*T88,*T9	Yes	T85,T88,T9	INPUT
data_i[22]	No	No		No		INPUT
data_i[23]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[24]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[27:26]	No	No		No		INPUT
data_i[30:28]	Yes	Yes	T85,T88,T9	Yes	T85,T88,T9	INPUT
data_i[31]	No	No		No		INPUT
data_i[32]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[33]	No	No		No		INPUT
data_i[42:34]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[45:43]	No	No		No		INPUT
data_i[48:46]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[50:49]	No	No		No		INPUT
data_i[53:51]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[54]	No	No		No		INPUT
data_i[57:55]	Yes	Yes	T85,T88,T9	Yes	T85,T88,T9	INPUT
data_i[58]	No	No		No		INPUT
data_i[71:59]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_o[0]	Yes	Yes	*T119,*T85,*T88	Yes	T119,T85,T125	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[2]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[4]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[11:6]	Yes	Yes	T119,T85,T88	Yes	T119,T85,T125	OUTPUT
data_o[13:12]	No	No		No		OUTPUT
data_o[16:14]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[19:18]	Yes	Yes	T85,T88,T9	Yes	T85,T88,T9	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[21]	Yes	Yes	*T85,*T88,*T9	Yes	T85,T88,T9	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[23]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[27:26]	No	No		No		OUTPUT
data_o[30:28]	Yes	Yes	T85,T88,T9	Yes	T85,T88,T9	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[32]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[42:34]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[45:43]	No	No		No		OUTPUT
data_o[48:46]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[50:49]	No	No		No		OUTPUT
data_o[53:51]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[57:55]	Yes	Yes	T85,T88,T9	Yes	T85,T88,T9	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[63:59]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	196	72.06
Total Bits 0->1	136	98	72.06
Total Bits 1->0	136	98	72.06

Ports	2	0	0.00
Port Bits	272	196	72.06
Port Bits 0->1	136	98	72.06
Port Bits 1->0	136	98	72.06

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[1]	Yes	Yes	*T15,*T114,*T119	Yes	T5,T14,T15	INPUT
data_i[2]	No	No		No		INPUT
data_i[6:3]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[7]	No	No		No		INPUT
data_i[10:8]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	INPUT
data_i[12:11]	No	No		No		INPUT
data_i[20:13]	Yes	Yes	T15,*T114,T119	Yes	T3,T5,T14	INPUT
data_i[21]	No	No		No		INPUT
data_i[23:22]	Yes	Yes	T15,*T114,T119	Yes	T3,T5,T14	INPUT
data_i[26:24]	No	No		No		INPUT
data_i[27]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[28]	No	No		No		INPUT
data_i[29]	Yes	Yes	*T15,*T119,*T85	Yes	T5,T15,T119	INPUT
data_i[30]	No	No		No		INPUT
data_i[34:31]	Yes	Yes	T15,*T114,T119	Yes	T3,T5,T14	INPUT
data_i[36:35]	No	No		No		INPUT
data_i[40:37]	Yes	Yes	T15,*T114,T119	Yes	T3,T5,T14	INPUT
data_i[41]	No	No		No		INPUT
data_i[42]	Yes	Yes	*T15,*T119,*T85	Yes	T5,T15,T119	INPUT
data_i[44:43]	No	No		No		INPUT
data_i[51:45]	Yes	Yes	T15,*T119,*T85	Yes	T5,T15,T119	INPUT
data_i[52]	No	No		No		INPUT
data_i[56:53]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[57]	No	No		No		INPUT
data_i[60:58]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T15,T9,T90	Yes	T5,T15,T9	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[1]	Yes	Yes	*T15,*T114,*T119	Yes	T5,T14,T15	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[6:3]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[10:8]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	OUTPUT
data_o[12:11]	No	No		No		OUTPUT
data_o[20:13]	Yes	Yes	T15,*T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[21]	No	No		No		OUTPUT
data_o[23:22]	Yes	Yes	T15,*T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[26:24]	No	No		No		OUTPUT
data_o[27]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[29]	Yes	Yes	*T15,*T119,*T85	Yes	T5,T15,T119	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[34:31]	Yes	Yes	T15,*T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[36:35]	No	No		No		OUTPUT
data_o[40:37]	Yes	Yes	T15,*T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[42]	Yes	Yes	*T15,*T119,*T85	Yes	T5,T15,T119	OUTPUT
data_o[44:43]	No	No		No		OUTPUT
data_o[51:45]	Yes	Yes	T15,*T119,*T85	Yes	T5,T15,T119	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[56:53]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[60:58]	Yes	Yes	T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T15,T9,T90	Yes	T5,T15,T9	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	196	72.06
Total Bits 0->1	136	98	72.06
Total Bits 1->0	136	98	72.06

Ports	2	0	0.00
Port Bits	272	196	72.06
Port Bits 0->1	136	98	72.06
Port Bits 1->0	136	98	72.06

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[4:0]	Yes	Yes	T114,T119,T85	Yes	T114,T119,T85	INPUT
data_i[5]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T114,*T119,*T85	Yes	T114,T119,T85	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[9]	Yes	Yes	*T114,*T119,*T85	Yes	T114,T119,T85	INPUT
data_i[11:10]	No	No		No		INPUT
data_i[13:12]	Yes	Yes	T114,T119,T85	Yes	T114,T119,T85	INPUT
data_i[14]	No	No		No		INPUT
data_i[16:15]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[17]	No	No		No		INPUT
data_i[21:18]	Yes	Yes	T119,T85,T125	Yes	T119,T85,T121	INPUT
data_i[22]	No	No		No		INPUT
data_i[24:23]	Yes	Yes	T119,T85,T125	Yes	T119,T85,T121	INPUT
data_i[25]	No	No		No		INPUT
data_i[29:26]	Yes	Yes	*T15,*T114,T119	Yes	T3,T5,T14	INPUT
data_i[31:30]	No	No		No		INPUT
data_i[33:32]	Yes	Yes	*T15,*T114,T119	Yes	T3,T5,T14	INPUT
data_i[34]	No	No		No		INPUT
data_i[36:35]	Yes	Yes	T119,T85,T125	Yes	T119,T85,T121	INPUT
data_i[37]	No	No		No		INPUT
data_i[44:38]	Yes	Yes	*T15,*T114,T119	Yes	T3,T5,T14	INPUT
data_i[46:45]	No	No		No		INPUT
data_i[56:47]	Yes	Yes	*T15,*T114,T119	Yes	T3,T5,T14	INPUT
data_i[59:57]	No	No		No		INPUT
data_i[61:60]	Yes	Yes	*T15,*T114,T119	Yes	T3,T5,T14	INPUT
data_i[62]	No	No		No		INPUT
data_i[71:63]	Yes	Yes	T119,T85,T88	Yes	T119,T85,T121	INPUT
data_o[4:0]	Yes	Yes	T114,T119,T85	Yes	T114,T119,T85	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T114,*T119,*T85	Yes	T114,T119,T85	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[9]	Yes	Yes	*T114,*T119,*T85	Yes	T114,T119,T85	OUTPUT
data_o[11:10]	No	No		No		OUTPUT
data_o[13:12]	Yes	Yes	T114,T119,T85	Yes	T114,T119,T85	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[16:15]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[21:18]	Yes	Yes	T119,T85,T125	Yes	T119,T85,T121	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[24:23]	Yes	Yes	T119,T85,T125	Yes	T119,T85,T121	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[29:26]	Yes	Yes	*T15,*T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[31:30]	No	No		No		OUTPUT
data_o[33:32]	Yes	Yes	*T15,*T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[34]	No	No		No		OUTPUT
data_o[36:35]	Yes	Yes	T119,T85,T125	Yes	T119,T85,T121	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[44:38]	Yes	Yes	*T15,*T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[46:45]	No	No		No		OUTPUT
data_o[56:47]	Yes	Yes	*T15,*T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[59:57]	No	No		No		OUTPUT
data_o[61:60]	Yes	Yes	*T15,*T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[62]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T119,T85,T88	Yes	T119,T85,T121	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	200	73.53
Total Bits 0->1	136	100	73.53
Total Bits 1->0	136	100	73.53

Ports	2	0	0.00
Port Bits	272	200	73.53
Port Bits 0->1	136	100	73.53
Port Bits 1->0	136	100	73.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	No	No		No		INPUT
data_i[2]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[3]	No	No		No		INPUT
data_i[6:4]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[16:9]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[17]	No	No		No		INPUT
data_i[18]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[19]	No	No		No		INPUT
data_i[21:20]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[23:22]	No	No		No		INPUT
data_i[26:24]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[27]	No	No		No		INPUT
data_i[30:28]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[32:31]	No	No		No		INPUT
data_i[37:33]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[38]	No	No		No		INPUT
data_i[40:39]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[41]	No	No		No		INPUT
data_i[44:42]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[45]	No	No		No		INPUT
data_i[46]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[47]	No	No		No		INPUT
data_i[50:48]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[52:51]	No	No		No		INPUT
data_i[71:53]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_o[1:0]	No	No		No		OUTPUT
data_o[2]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[6:4]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[16:9]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[18]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[21:20]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[23:22]	No	No		No		OUTPUT
data_o[26:24]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[30:28]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[32:31]	No	No		No		OUTPUT
data_o[37:33]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[40:39]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[44:42]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[45]	No	No		No		OUTPUT
data_o[46]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[50:48]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[52:51]	No	No		No		OUTPUT
data_o[63:53]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	200	73.53
Total Bits 0->1	136	100	73.53
Total Bits 1->0	136	100	73.53

Ports	2	0	0.00
Port Bits	272	200	73.53
Port Bits 0->1	136	100	73.53
Port Bits 1->0	136	100	73.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[2]	No	No		No		INPUT
data_i[5:3]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[6]	No	No		No		INPUT
data_i[8:7]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[9]	No	No		No		INPUT
data_i[10]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[12:11]	No	No		No		INPUT
data_i[16:13]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[19:17]	No	No		No		INPUT
data_i[26:20]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[27]	No	No		No		INPUT
data_i[29:28]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[30]	No	No		No		INPUT
data_i[33:31]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[35:34]	No	No		No		INPUT
data_i[36]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[38:37]	No	No		No		INPUT
data_i[47:39]	Yes	Yes	T114,T119,T85	Yes	T3,T5,T14	INPUT
data_i[48]	No	No		No		INPUT
data_i[50:49]	Yes	Yes	T114,T119,T85	Yes	T3,T5,T114	INPUT
data_i[51]	No	No		No		INPUT
data_i[55:52]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[56]	No	No		No		INPUT
data_i[57]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[58]	No	No		No		INPUT
data_i[71:59]	Yes	Yes	T114,T119,T85	Yes	T3,T5,T114	INPUT
data_o[1:0]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[5:3]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[8:7]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[10]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[12:11]	No	No		No		OUTPUT
data_o[16:13]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[19:17]	No	No		No		OUTPUT
data_o[26:20]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[29:28]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[33:31]	Yes	Yes	*T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[35:34]	No	No		No		OUTPUT
data_o[36]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[38:37]	No	No		No		OUTPUT
data_o[47:39]	Yes	Yes	T114,T119,T85	Yes	T3,T5,T14	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[50:49]	Yes	Yes	T114,T119,T85	Yes	T3,T5,T114	OUTPUT
data_o[51]	No	No		No		OUTPUT
data_o[55:52]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[57]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[63:59]	Yes	Yes	T114,T119,T85	Yes	T3,T5,T114	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	212	77.94
Total Bits 0->1	136	106	77.94
Total Bits 1->0	136	106	77.94

Ports	2	0	0.00
Port Bits	272	212	77.94
Port Bits 0->1	136	106	77.94
Port Bits 1->0	136	106	77.94

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[3]	No	No		No		INPUT
data_i[9:4]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	INPUT
data_i[10]	No	No		No		INPUT
data_i[12:11]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[13]	No	No		No		INPUT
data_i[17:14]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[19:18]	No	No		No		INPUT
data_i[27:20]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	INPUT
data_i[28]	No	No		No		INPUT
data_i[29]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[30]	No	No		No		INPUT
data_i[31]	Yes	Yes	*T15,*T114,*T119	Yes	T5,T14,T15	INPUT
data_i[33:32]	No	No		No		INPUT
data_i[41:34]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[43:42]	No	No		No		INPUT
data_i[49:44]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	INPUT
data_i[50]	No	No		No		INPUT
data_i[55:51]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	INPUT
data_i[57:56]	No	No		No		INPUT
data_i[62:58]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_o[2:0]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[9:4]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[12:11]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[17:14]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[19:18]	No	No		No		OUTPUT
data_o[27:20]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[29]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[31]	Yes	Yes	*T15,*T114,*T119	Yes	T5,T14,T15	OUTPUT
data_o[33:32]	No	No		No		OUTPUT
data_o[41:34]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[43:42]	No	No		No		OUTPUT
data_o[49:44]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[55:51]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	OUTPUT
data_o[57:56]	No	No		No		OUTPUT
data_o[62:58]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	220	80.88
Total Bits 0->1	136	110	80.88
Total Bits 1->0	136	110	80.88

Ports	2	0	0.00
Port Bits	272	220	80.88
Port Bits 0->1	136	110	80.88
Port Bits 1->0	136	110	80.88

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[4:0]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[5]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[7]	No	No		No		INPUT
data_i[12:8]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[13]	No	No		No		INPUT
data_i[15:14]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[16]	No	No		No		INPUT
data_i[18:17]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[19]	No	No		No		INPUT
data_i[20]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[22:21]	No	No		No		INPUT
data_i[25:23]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	INPUT
data_i[28:26]	No	No		No		INPUT
data_i[40:29]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	INPUT
data_i[41]	No	No		No		INPUT
data_i[42]	Yes	Yes	*T15,*T114,*T119	Yes	T5,T14,T15	INPUT
data_i[43]	No	No		No		INPUT
data_i[60:44]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	INPUT
data_o[4:0]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[12:8]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[15:14]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[18:17]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[20]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[22:21]	No	No		No		OUTPUT
data_o[25:23]	Yes	Yes	T15,T114,T119	Yes	T3,T5,T14	OUTPUT
data_o[28:26]	No	No		No		OUTPUT
data_o[40:29]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[42]	Yes	Yes	*T15,*T114,*T119	Yes	T5,T14,T15	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[60:44]	Yes	Yes	*T15,*T114,*T119	Yes	T3,T5,T14	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T15,T114,T119	Yes	T5,T14,T15	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	280	272	97.14
Total Bits 0->1	140	136	97.14
Total Bits 1->0	140	136	97.14

Ports	4	2	50.00
Port Bits	280	272	97.14
Port Bits 0->1	140	136	97.14
Port Bits 1->0	140	136	97.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T6,T85,T121	Yes	T6,T85,T121	INPUT
data_o[63:0]	Yes	Yes	T6,T85,T121	Yes	T6,T85,T121	OUTPUT
syndrome_o[2:0]	No	No		No		OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	No	No		No		OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T6,T114,T92	Yes	T6,T114,T92	INPUT
data_o[63:0]	Yes	Yes	T6,T114,T92	Yes	T6,T114,T92	OUTPUT
syndrome_o[2:0]	Yes	Yes	T149,T150	Yes	T149,T150	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T149,*T150	Yes	T149,T150	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T15,T115,T97	Yes	T15,T115,T97	INPUT
data_o[63:0]	Yes	Yes	T15,T115,T97	Yes	T15,T115,T97	OUTPUT
syndrome_o[2:0]	Yes	Yes	T149	Yes	T149	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T149	Yes	T149	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T90,T115,T10	Yes	T90,T115,T10	INPUT
data_o[63:0]	Yes	Yes	T90,T115,T10	Yes	T90,T115,T10	OUTPUT
syndrome_o[2:0]	Yes	Yes	T101,T149,T150	Yes	T101,T149,T150	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T101,*T149,*T150	Yes	T101,T149,T150	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T88,T118,T201	Yes	T88,T118,T201	INPUT
data_o[63:0]	Yes	Yes	T88,T118,T201	Yes	T88,T118,T201	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T123,T280,T154	Yes	T123,T280,T154	INPUT
data_o[63:0]	Yes	Yes	T123,T280,T154	Yes	T123,T280,T154	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T10,T94,T34	Yes	T10,T94,T34	INPUT
data_o[63:0]	Yes	Yes	T10,T94,T34	Yes	T10,T94,T34	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T92,T281,T200	Yes	T92,T282,T281	INPUT
data_o[63:0]	Yes	Yes	T92,T281,T200	Yes	T92,T282,T281	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T94,T124,T198	Yes	T125,T94,T124	INPUT
data_o[63:0]	Yes	Yes	T94,T124,T198	Yes	T125,T94,T124	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T92,T169,T253	Yes	T92,T169,T253	INPUT
data_o[63:0]	Yes	Yes	T92,T169,T253	Yes	T92,T169,T253	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T124,T201,T203	Yes	T124,T201,T203	INPUT
data_o[63:0]	Yes	Yes	T124,T201,T203	Yes	T124,T201,T203	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T90,T93	Yes	T3,T90,T93	INPUT
data_o[63:0]	Yes	Yes	T3,T90,T93	Yes	T3,T90,T93	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T124,T228,T145	Yes	T124,T282,T228	INPUT
data_o[63:0]	Yes	Yes	T124,T228,T145	Yes	T124,T282,T228	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T126,T90,T94	Yes	T126,T90,T94	INPUT
data_o[63:0]	Yes	Yes	T126,T90,T94	Yes	T126,T90,T94	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T88,T9	Yes	T2,T3,T88	INPUT
data_o[63:0]	Yes	Yes	T2,T88,T9	Yes	T2,T3,T88	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T15,T119	Yes	T3,T5,T15	INPUT
data_o[63:0]	Yes	Yes	T5,T15,T119	Yes	T3,T5,T15	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T114,T88	Yes	T3,T5,T114	INPUT
data_o[63:0]	Yes	Yes	T5,T114,T88	Yes	T3,T5,T114	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T114,T126,T115	Yes	T5,T114,T126	INPUT
data_o[63:0]	Yes	Yes	T114,T126,T115	Yes	T5,T114,T126	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T24,T85,T126	Yes	T3,T6,T24	INPUT
data_o[63:0]	Yes	Yes	T24,T85,T126	Yes	T3,T6,T24	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T24,T36,T283	Yes	T24,T36,T283	INPUT
data_o[63:0]	Yes	Yes	T24,T36,T283	Yes	T24,T36,T283	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T126,T9	Yes	T3,T24,T126	INPUT
data_o[63:0]	Yes	Yes	T3,T126,T9	Yes	T3,T24,T126	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T121,T9	Yes	T3,T121,T9	INPUT
data_o[63:0]	Yes	Yes	T3,T121,T9	Yes	T3,T121,T9	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T92,T9,T93	Yes	T24,T92,T9	INPUT
data_o[63:0]	Yes	Yes	T92,T9,T93	Yes	T24,T92,T9	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T117,T124,T282	Yes	T117,T124,T282	INPUT
data_o[63:0]	Yes	Yes	T117,T124,T282	Yes	T117,T124,T282	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T10,T124	Yes	T3,T10,T124	INPUT
data_o[63:0]	Yes	Yes	T3,T10,T124	Yes	T3,T10,T124	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T85,T127,T117	Yes	T114,T85,T127	INPUT
data_o[63:0]	Yes	Yes	T85,T127,T117	Yes	T114,T85,T127	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T117,T284,T281	Yes	T283,T117,T284	INPUT
data_o[63:0]	Yes	Yes	T117,T284,T281	Yes	T283,T117,T284	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T126,T116,T117	Yes	T126,T116,T117	INPUT
data_o[63:0]	Yes	Yes	T126,T116,T117	Yes	T126,T116,T117	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T283,T145	Yes	T5,T283,T145	INPUT
data_o[63:0]	Yes	Yes	T5,T283,T145	Yes	T5,T283,T145	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T6,T90	Yes	T3,T6,T90	INPUT
data_o[63:0]	Yes	Yes	T3,T6,T90	Yes	T3,T6,T90	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T94,T153,T282	Yes	T94,T153,T282	INPUT
data_o[63:0]	Yes	Yes	T94,T153,T282	Yes	T94,T153,T282	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T15,T88	Yes	T5,T24,T15	INPUT
data_o[63:0]	Yes	Yes	T5,T15,T88	Yes	T5,T24,T15	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T15,T115	Yes	T3,T15,T115	INPUT
data_o[63:0]	Yes	Yes	T3,T15,T115	Yes	T3,T15,T115	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T126,T94,T117	Yes	T126,T94,T117	INPUT
data_o[63:0]	Yes	Yes	T126,T94,T117	Yes	T126,T94,T117	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T115,T118,T259	Yes	T115,T118,T259	INPUT
data_o[63:0]	Yes	Yes	T115,T118,T259	Yes	T115,T118,T259	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T15,T115	Yes	T3,T15,T115	INPUT
data_o[63:0]	Yes	Yes	T3,T15,T115	Yes	T3,T15,T115	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T92,T121,T36	Yes	T3,T24,T92	INPUT
data_o[63:0]	Yes	Yes	T92,T121,T36	Yes	T3,T24,T92	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T124,T253,T284	Yes	T283,T124,T253	INPUT
data_o[63:0]	Yes	Yes	T124,T253,T284	Yes	T283,T124,T253	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T93,T34,T225	Yes	T93,T34,T259	INPUT
data_o[63:0]	Yes	Yes	T93,T34,T225	Yes	T93,T34,T259	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T93,T153,T282	Yes	T93,T153,T282	INPUT
data_o[63:0]	Yes	Yes	T93,T153,T282	Yes	T93,T153,T282	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T92,T115	Yes	T5,T92,T115	INPUT
data_o[63:0]	Yes	Yes	T5,T92,T115	Yes	T5,T92,T115	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T85,T115	Yes	T5,T85,T115	INPUT
data_o[63:0]	Yes	Yes	T5,T85,T115	Yes	T5,T85,T115	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T88,T126,T90	Yes	T3,T88,T126	INPUT
data_o[63:0]	Yes	Yes	T88,T126,T90	Yes	T3,T88,T126	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR