Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	452830	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

179555

1

T1

10

T2

253

T4

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	358200	1			T1	7		T2	580		T3	1
values[0x0]	135120	1			T1	7		T2	225		T4	17
values[0x1]	139065	1			T1	9		T2	227		T4	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	354210	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

278175

1

T1

11

T2

410

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1550	1			T1	1		T2	7		T8	1
valid_sources[0x01]	3530	1			T2	2		T6	4		T7	9
valid_sources[0x02]	2175	1			T2	10		T8	4		T29	10
valid_sources[0x03]	4450	1			T2	7		T3	1		T6	1
valid_sources[0x04]	4140	1			T2	4		T8	7		T29	4
valid_sources[0x05]	1795	1			T8	11		T13	11		T14	11
valid_sources[0x06]	1910	1			T2	11		T8	12		T29	11
valid_sources[0x07]	2305	1			T13	42		T14	42		T31	4
valid_sources[0x08]	1405	1			T2	1		T6	1		T8	4
valid_sources[0x09]	1760	1			T2	2		T29	2		T13	15
valid_sources[0x0a]	2480	1			T2	6		T8	4		T29	6
valid_sources[0x0b]	1245	1			T13	21		T14	21		T31	2
valid_sources[0x0c]	2105	1			T2	10		T7	1		T8	1
valid_sources[0x0d]	4350	1			T1	5		T6	9		T7	7
valid_sources[0x0e]	3045	1			T2	19		T8	3		T29	19
valid_sources[0x0f]	2565	1			T2	2		T8	2		T29	2
valid_sources[0x10]	3980	1			T2	17		T8	10		T29	17
valid_sources[0x11]	1205	1			T13	14		T14	14		T31	10
valid_sources[0x12]	3205	1			T2	7		T8	14		T29	7
valid_sources[0x13]	2060	1			T2	7		T5	5		T8	5
valid_sources[0x14]	1120	1			T6	1		T8	5		T9	1
valid_sources[0x15]	1280	1			T13	4		T14	4		T48	3
valid_sources[0x16]	2795	1			T1	6		T8	4		T13	30
valid_sources[0x17]	2280	1			T2	4		T8	5		T29	4
valid_sources[0x18]	2390	1			T2	7		T8	5		T29	7
valid_sources[0x19]	2480	1			T6	2		T8	11		T9	2
valid_sources[0x1a]	1960	1			T2	9		T8	16		T29	9
valid_sources[0x1b]	1335	1			T2	7		T8	2		T29	7
valid_sources[0x1c]	3435	1			T7	2		T8	4		T13	31
valid_sources[0x1d]	1000	1			T2	3		T8	3		T29	3
valid_sources[0x1e]	1510	1			T2	5		T8	4		T29	5
valid_sources[0x1f]	2380	1			T2	10		T6	4		T8	10
valid_sources[0x20]	1785	1			T2	3		T8	11		T29	3
valid_sources[0x21]	2205	1			T2	8		T8	3		T29	8
valid_sources[0x22]	1250	1			T4	2		T6	1		T7	1
valid_sources[0x23]	2540	1			T2	7		T8	1		T29	7
valid_sources[0x24]	2840	1			T2	10		T8	2		T29	10
valid_sources[0x25]	2520	1			T2	6		T8	7		T29	6
valid_sources[0x26]	2140	1			T13	30		T14	30		T31	11
valid_sources[0x27]	4175	1			T2	3		T6	6		T7	10
valid_sources[0x28]	1890	1			T8	23		T13	2		T14	2
valid_sources[0x29]	1340	1			T8	8		T13	8		T14	8
valid_sources[0x2a]	855	1			T8	5		T13	3		T14	3
valid_sources[0x2b]	2120	1			T5	1		T13	24		T14	24
valid_sources[0x2c]	4770	1			T2	13		T8	16		T29	13
valid_sources[0x2d]	1765	1			T8	7		T13	19		T14	19
valid_sources[0x2e]	2575	1			T1	1		T2	16		T8	6
valid_sources[0x2f]	2950	1			T2	4		T6	3		T7	5
valid_sources[0x30]	1300	1			T7	3		T13	7		T102	5
valid_sources[0x31]	2730	1			T7	2		T8	3		T13	41
valid_sources[0x32]	1190	1			T8	4		T13	17		T14	17
valid_sources[0x33]	1815	1			T2	1		T8	6		T29	1
valid_sources[0x34]	725	1			T8	3		T13	3		T14	3
valid_sources[0x35]	1990	1			T2	13		T5	4		T8	4
valid_sources[0x36]	1250	1			T2	8		T29	8		T13	12
valid_sources[0x37]	1050	1			T2	4		T7	2		T29	4
valid_sources[0x38]	3360	1			T2	2		T8	2		T29	2
valid_sources[0x39]	3055	1			T1	7		T2	3		T29	3
valid_sources[0x3a]	3305	1			T2	10		T6	5		T9	5
valid_sources[0x3b]	2525	1			T2	1		T8	12		T29	1
valid_sources[0x3c]	900	1			T2	2		T29	2		T13	7
valid_sources[0x3d]	1420	1			T2	1		T5	6		T29	1
valid_sources[0x3e]	2050	1			T2	2		T29	2		T13	22
valid_sources[0x3f]	3110	1			T2	1		T6	1		T7	1
valid_sources[0x40]	2385	1			T2	5		T8	7		T29	5
valid_sources[0x41]	3175	1			T2	3		T8	5		T29	3
valid_sources[0x42]	2310	1			T13	45		T14	45		T18	45
valid_sources[0x43]	2490	1			T8	4		T13	31		T14	31
valid_sources[0x44]	1000	1			T2	2		T8	3		T29	2
valid_sources[0x45]	2695	1			T8	6		T13	12		T14	12
valid_sources[0x46]	1765	1			T2	2		T8	11		T29	2
valid_sources[0x47]	3860	1			T2	5		T6	2		T8	9
valid_sources[0x48]	3030	1			T2	9		T4	7		T5	5
valid_sources[0x49]	1760	1			T2	8		T8	1		T29	8
valid_sources[0x4a]	4845	1			T2	10		T4	3		T8	23
valid_sources[0x4b]	1820	1			T4	3		T8	4		T13	18
valid_sources[0x4c]	1975	1			T6	4		T9	4		T13	16
valid_sources[0x4d]	1080	1			T5	6		T13	5		T14	5
valid_sources[0x4e]	2060	1			T8	12		T13	24		T14	24
valid_sources[0x4f]	3900	1			T2	19		T8	16		T29	19
valid_sources[0x50]	2755	1			T6	3		T7	7		T8	1
valid_sources[0x51]	4065	1			T2	10		T5	4		T8	7
valid_sources[0x52]	2145	1			T2	6		T6	4		T8	8
valid_sources[0x53]	935	1			T2	5		T29	5		T13	10
valid_sources[0x54]	1815	1			T2	2		T29	2		T13	20
valid_sources[0x55]	2915	1			T2	3		T5	2		T8	1
valid_sources[0x56]	4680	1			T13	43		T14	43		T48	6
valid_sources[0x57]	3155	1			T6	17		T9	17		T13	29
valid_sources[0x58]	1885	1			T2	4		T8	5		T29	4
valid_sources[0x59]	1820	1			T6	2		T9	2		T13	21
valid_sources[0x5a]	2240	1			T13	15		T108	9		T14	15
valid_sources[0x5b]	1900	1			T13	27		T14	27		T31	9
valid_sources[0x5c]	2750	1			T2	13		T29	13		T13	37
valid_sources[0x5d]	825	1			T2	6		T5	2		T8	2
valid_sources[0x5e]	865	1			T13	4		T108	2		T102	2
valid_sources[0x5f]	2395	1			T13	29		T102	6		T14	29
valid_sources[0x60]	2325	1			T2	7		T8	8		T29	7
valid_sources[0x61]	2860	1			T2	10		T8	11		T29	10
valid_sources[0x62]	1195	1			T4	1		T13	17		T14	17
valid_sources[0x63]	1175	1			T2	4		T29	4		T13	9
valid_sources[0x64]	2305	1			T2	4		T8	4		T29	4
valid_sources[0x65]	4440	1			T2	21		T6	5		T7	10
valid_sources[0x66]	2245	1			T13	33		T14	33		T31	10
valid_sources[0x67]	2670	1			T2	4		T29	4		T13	24
valid_sources[0x68]	4515	1			T6	12		T7	1		T8	7
valid_sources[0x69]	3795	1			T5	1		T8	15		T13	25
valid_sources[0x6a]	2785	1			T2	5		T4	3		T7	2
valid_sources[0x6b]	2210	1			T2	3		T5	10		T29	3
valid_sources[0x6c]	1910	1			T8	2		T13	10		T14	10
valid_sources[0x6d]	800	1			T2	5		T4	1		T8	4
valid_sources[0x6e]	2745	1			T2	2		T6	7		T9	7
valid_sources[0x6f]	820	1			T2	3		T29	3		T13	5
valid_sources[0x70]	2265	1			T2	1		T8	9		T29	1
valid_sources[0x71]	4255	1			T1	2		T2	2		T6	5
valid_sources[0x72]	4650	1			T2	6		T6	1		T8	11
valid_sources[0x73]	3850	1			T2	13		T5	2		T29	13
valid_sources[0x74]	2420	1			T2	5		T29	5		T13	25
valid_sources[0x75]	4120	1			T2	1		T6	5		T7	3
valid_sources[0x76]	2405	1			T2	2		T8	4		T29	2
valid_sources[0x77]	875	1			T2	1		T8	2		T29	1
valid_sources[0x78]	2700	1			T2	8		T8	13		T29	8
valid_sources[0x79]	1975	1			T13	33		T14	33		T31	1
valid_sources[0x7a]	1985	1			T8	4		T13	17		T14	17
valid_sources[0x7b]	4315	1			T2	1		T6	3		T8	2
valid_sources[0x7c]	3680	1			T2	2		T6	1		T8	6
valid_sources[0x7d]	2865	1			T5	4		T8	7		T13	36
valid_sources[0x7e]	2750	1			T2	1		T4	9		T5	1
valid_sources[0x7f]	2270	1			T13	16		T108	6		T14	16
valid_sources[0x80]	2775	1			T2	1		T8	7		T29	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

104380

1

T1

4

T2

155

T4

20

values[0x0]

all_enables

biggest_size

50155

1

T1

4

T2

69

T4

4

values[0x1]

all_enables

biggest_size

25020

1

T1

2

T2

29

T4

2