SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 33300 | 1 | T2 | 377 | T8 | 289 | T29 | 377 | ||||
others[1] | 33500 | 1 | T2 | 382 | T8 | 288 | T29 | 382 | ||||
others[2] | 36700 | 1 | T2 | 419 | T8 | 315 | T29 | 419 | ||||
others[3] | 58850 | 1 | T2 | 682 | T8 | 495 | T29 | 682 | ||||
false | 17800 | 1 | T2 | 50 | T5 | 4 | T8 | 50 | ||||
true | 26165 | 1 | T1 | 5 | T2 | 102 | T3 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35650 | 1 | T2 | 410 | T8 | 303 | T29 | 410 | ||||
others[1] | 36100 | 1 | T2 | 418 | T5 | 1 | T8 | 303 | ||||
others[2] | 35200 | 1 | T2 | 413 | T8 | 291 | T29 | 413 | ||||
others[3] | 56850 | 1 | T2 | 636 | T8 | 501 | T29 | 636 | ||||
false | 11500 | 1 | T2 | 50 | T5 | 4 | T8 | 50 | ||||
true | 20065 | 1 | T1 | 5 | T2 | 102 | T3 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 850 | 1 | T13 | 5 | T108 | 9 | T14 | 5 | ||||
others[1] | 600 | 1 | T4 | 1 | T13 | 4 | T108 | 4 | ||||
others[2] | 700 | 1 | T4 | 1 | T5 | 1 | T13 | 6 | ||||
others[3] | 700 | 1 | T4 | 1 | T13 | 5 | T108 | 5 | ||||
false | 11715 | 1 | T1 | 5 | T2 | 2 | T3 | 4 | ||||
true | 3800 | 1 | T4 | 8 | T5 | 3 | T13 | 37 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |