Module Definition
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Module : pwrmgr_clock_enables_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_clock_enables_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.pwrmgr_clock_enables_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.pwrmgr_clock_enables_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.84 100.00 80.00 99.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : pwrmgr_clock_enables_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS3011100.00
ALWAYS3711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_clock_enables_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_clock_enables_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
30 1 1
37 1 1


Cond Coverage for Module : pwrmgr_clock_enables_sva_if
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       30
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T6
01CoveredT1,T2,T3
10CoveredT1,T2,T8

 LINE       37
 EXPRESSION (fast_state == FastPwrStateActive)
            -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Module : pwrmgr_clock_enables_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CoreClkPwrDown_A 3599935 12250 0 0
CoreClkPwrUp_A 3599935 114750 0 0
IoClkPwrDown_A 3599935 12250 0 0
IoClkPwrUp_A 3599935 114750 0 0
UsbClkActive_A 3599935 6350 0 0
UsbClkPwrDown_A 3599935 12250 0 0
UsbClkPwrUp_A 3599935 114750 0 0


CoreClkPwrDown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3599935 12250 0 0
T2 6778 26 0 0
T3 276 0 0 0
T4 756 0 0 0
T5 506 0 0 0
T6 2072 8 0 0
T7 363 0 0 0
T8 6435 26 0 0
T9 2072 8 0 0
T10 211 0 0 0
T13 0 103 0 0
T14 0 103 0 0
T29 6778 26 0 0
T30 0 26 0 0
T102 0 9 0 0
T103 0 8 0 0

CoreClkPwrUp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3599935 114750 0 0
T1 349 25 0 0
T2 6778 247 0 0
T3 276 0 0 0
T4 756 0 0 0
T5 506 0 0 0
T6 2072 72 0 0
T7 363 0 0 0
T8 6435 247 0 0
T9 2072 72 0 0
T10 211 0 0 0
T13 0 969 0 0
T29 0 247 0 0
T30 0 247 0 0
T36 0 25 0 0
T102 0 80 0 0

IoClkPwrDown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3599935 12250 0 0
T2 6778 26 0 0
T3 276 0 0 0
T4 756 0 0 0
T5 506 0 0 0
T6 2072 8 0 0
T7 363 0 0 0
T8 6435 26 0 0
T9 2072 8 0 0
T10 211 0 0 0
T13 0 103 0 0
T14 0 103 0 0
T29 6778 26 0 0
T30 0 26 0 0
T102 0 9 0 0
T103 0 8 0 0

IoClkPwrUp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3599935 114750 0 0
T1 349 25 0 0
T2 6778 247 0 0
T3 276 0 0 0
T4 756 0 0 0
T5 506 0 0 0
T6 2072 72 0 0
T7 363 0 0 0
T8 6435 247 0 0
T9 2072 72 0 0
T10 211 0 0 0
T13 0 969 0 0
T29 0 247 0 0
T30 0 247 0 0
T36 0 25 0 0
T102 0 80 0 0

UsbClkActive_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3599935 6350 0 0
T1 349 1 0 0
T2 6778 16 0 0
T3 276 0 0 0
T4 756 0 0 0
T5 506 0 0 0
T6 2072 8 0 0
T7 363 0 0 0
T8 6435 16 0 0
T9 2072 8 0 0
T10 211 0 0 0
T13 0 50 0 0
T29 0 16 0 0
T30 0 16 0 0
T36 0 1 0 0
T102 0 5 0 0

UsbClkPwrDown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3599935 12250 0 0
T2 6778 26 0 0
T3 276 0 0 0
T4 756 0 0 0
T5 506 0 0 0
T6 2072 8 0 0
T7 363 0 0 0
T8 6435 26 0 0
T9 2072 8 0 0
T10 211 0 0 0
T13 0 103 0 0
T14 0 103 0 0
T29 6778 26 0 0
T30 0 26 0 0
T102 0 9 0 0
T103 0 8 0 0

UsbClkPwrUp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3599935 114750 0 0
T1 349 25 0 0
T2 6778 247 0 0
T3 276 0 0 0
T4 756 0 0 0
T5 506 0 0 0
T6 2072 72 0 0
T7 363 0 0 0
T8 6435 247 0 0
T9 2072 72 0 0
T10 211 0 0 0
T13 0 969 0 0
T29 0 247 0 0
T30 0 247 0 0
T36 0 25 0 0
T102 0 80 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%