Line Coverage for Module :
pwrmgr_clock_enables_sva_if
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 30 | 1 | 1 | 100.00 |
ALWAYS | 37 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_clock_enables_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_clock_enables_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
30 |
1 |
1 |
37 |
1 |
1 |
Cond Coverage for Module :
pwrmgr_clock_enables_sva_if
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 30
EXPRESSION (((!rst_ni)) || disable_sva)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T8 |
LINE 37
EXPRESSION (fast_state == FastPwrStateActive)
-----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
pwrmgr_clock_enables_sva_if
Assertion Details
CoreClkPwrDown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3599935 |
12250 |
0 |
0 |
T2 |
6778 |
26 |
0 |
0 |
T3 |
276 |
0 |
0 |
0 |
T4 |
756 |
0 |
0 |
0 |
T5 |
506 |
0 |
0 |
0 |
T6 |
2072 |
8 |
0 |
0 |
T7 |
363 |
0 |
0 |
0 |
T8 |
6435 |
26 |
0 |
0 |
T9 |
2072 |
8 |
0 |
0 |
T10 |
211 |
0 |
0 |
0 |
T13 |
0 |
103 |
0 |
0 |
T14 |
0 |
103 |
0 |
0 |
T29 |
6778 |
26 |
0 |
0 |
T30 |
0 |
26 |
0 |
0 |
T102 |
0 |
9 |
0 |
0 |
T103 |
0 |
8 |
0 |
0 |
CoreClkPwrUp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3599935 |
114750 |
0 |
0 |
T1 |
349 |
25 |
0 |
0 |
T2 |
6778 |
247 |
0 |
0 |
T3 |
276 |
0 |
0 |
0 |
T4 |
756 |
0 |
0 |
0 |
T5 |
506 |
0 |
0 |
0 |
T6 |
2072 |
72 |
0 |
0 |
T7 |
363 |
0 |
0 |
0 |
T8 |
6435 |
247 |
0 |
0 |
T9 |
2072 |
72 |
0 |
0 |
T10 |
211 |
0 |
0 |
0 |
T13 |
0 |
969 |
0 |
0 |
T29 |
0 |
247 |
0 |
0 |
T30 |
0 |
247 |
0 |
0 |
T36 |
0 |
25 |
0 |
0 |
T102 |
0 |
80 |
0 |
0 |
IoClkPwrDown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3599935 |
12250 |
0 |
0 |
T2 |
6778 |
26 |
0 |
0 |
T3 |
276 |
0 |
0 |
0 |
T4 |
756 |
0 |
0 |
0 |
T5 |
506 |
0 |
0 |
0 |
T6 |
2072 |
8 |
0 |
0 |
T7 |
363 |
0 |
0 |
0 |
T8 |
6435 |
26 |
0 |
0 |
T9 |
2072 |
8 |
0 |
0 |
T10 |
211 |
0 |
0 |
0 |
T13 |
0 |
103 |
0 |
0 |
T14 |
0 |
103 |
0 |
0 |
T29 |
6778 |
26 |
0 |
0 |
T30 |
0 |
26 |
0 |
0 |
T102 |
0 |
9 |
0 |
0 |
T103 |
0 |
8 |
0 |
0 |
IoClkPwrUp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3599935 |
114750 |
0 |
0 |
T1 |
349 |
25 |
0 |
0 |
T2 |
6778 |
247 |
0 |
0 |
T3 |
276 |
0 |
0 |
0 |
T4 |
756 |
0 |
0 |
0 |
T5 |
506 |
0 |
0 |
0 |
T6 |
2072 |
72 |
0 |
0 |
T7 |
363 |
0 |
0 |
0 |
T8 |
6435 |
247 |
0 |
0 |
T9 |
2072 |
72 |
0 |
0 |
T10 |
211 |
0 |
0 |
0 |
T13 |
0 |
969 |
0 |
0 |
T29 |
0 |
247 |
0 |
0 |
T30 |
0 |
247 |
0 |
0 |
T36 |
0 |
25 |
0 |
0 |
T102 |
0 |
80 |
0 |
0 |
UsbClkActive_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3599935 |
6350 |
0 |
0 |
T1 |
349 |
1 |
0 |
0 |
T2 |
6778 |
16 |
0 |
0 |
T3 |
276 |
0 |
0 |
0 |
T4 |
756 |
0 |
0 |
0 |
T5 |
506 |
0 |
0 |
0 |
T6 |
2072 |
8 |
0 |
0 |
T7 |
363 |
0 |
0 |
0 |
T8 |
6435 |
16 |
0 |
0 |
T9 |
2072 |
8 |
0 |
0 |
T10 |
211 |
0 |
0 |
0 |
T13 |
0 |
50 |
0 |
0 |
T29 |
0 |
16 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T36 |
0 |
1 |
0 |
0 |
T102 |
0 |
5 |
0 |
0 |
UsbClkPwrDown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3599935 |
12250 |
0 |
0 |
T2 |
6778 |
26 |
0 |
0 |
T3 |
276 |
0 |
0 |
0 |
T4 |
756 |
0 |
0 |
0 |
T5 |
506 |
0 |
0 |
0 |
T6 |
2072 |
8 |
0 |
0 |
T7 |
363 |
0 |
0 |
0 |
T8 |
6435 |
26 |
0 |
0 |
T9 |
2072 |
8 |
0 |
0 |
T10 |
211 |
0 |
0 |
0 |
T13 |
0 |
103 |
0 |
0 |
T14 |
0 |
103 |
0 |
0 |
T29 |
6778 |
26 |
0 |
0 |
T30 |
0 |
26 |
0 |
0 |
T102 |
0 |
9 |
0 |
0 |
T103 |
0 |
8 |
0 |
0 |
UsbClkPwrUp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3599935 |
114750 |
0 |
0 |
T1 |
349 |
25 |
0 |
0 |
T2 |
6778 |
247 |
0 |
0 |
T3 |
276 |
0 |
0 |
0 |
T4 |
756 |
0 |
0 |
0 |
T5 |
506 |
0 |
0 |
0 |
T6 |
2072 |
72 |
0 |
0 |
T7 |
363 |
0 |
0 |
0 |
T8 |
6435 |
247 |
0 |
0 |
T9 |
2072 |
72 |
0 |
0 |
T10 |
211 |
0 |
0 |
0 |
T13 |
0 |
969 |
0 |
0 |
T29 |
0 |
247 |
0 |
0 |
T30 |
0 |
247 |
0 |
0 |
T36 |
0 |
25 |
0 |
0 |
T102 |
0 |
80 |
0 |
0 |