Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.84	100.00	80.00	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22440370	9140	0	0
intr_enable_rd_A	22440370	73380	0	0
reset_en_rd_A	22440370	1680	0	0
reset_en_regwen_rd_A	22440370	1380	0	0
wake_info_capture_dis_rd_A	22440370	1150	0	0
wakeup_en_rd_A	22440370	2695	0	0
wakeup_en_regwen_rd_A	22440370	1840	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22440370	9140	0	0
T13	187951	8	0	0
T14	187951	8	0	0
T18	187951	8	0	0
T30	41652	0	0	0
T36	2182	0	0	0
T42	0	6	0	0
T43	0	6	0	0
T52	0	9	0	0
T101	1689	0	0	0
T102	11723	0	0	0
T103	11653	0	0	0
T104	0	8	0	0
T105	0	8	0	0
T106	0	8	0	0
T107	0	8	0	0
T108	4993	0	0	0
T109	2774	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22440370	73380	0	0
T2	41652	78	0	0
T3	1661	0	0	0
T4	4554	0	0	0
T5	3798	11	0	0
T6	11653	44	0	0
T7	2774	43	0	0
T8	38913	78	0	0
T9	11653	44	0	0
T10	1412	0	0	0
T13	0	598	0	0
T29	41652	78	0	0
T102	0	44	0	0
T108	0	81	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22440370	1680	0	0
T42	5879	28	0	0
T43	5879	28	0	0
T44	5879	28	0	0
T45	5642	2	0	0
T51	2130	13	0	0
T52	1796	6	0	0
T56	1796	6	0	0
T57	1796	6	0	0
T83	1353	7	0	0
T96	2130	13	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22440370	1380	0	0
T42	5879	17	0	0
T43	5879	17	0	0
T44	5879	17	0	0
T45	5642	5	0	0
T51	2130	10	0	0
T58	5879	17	0	0
T62	0	10	0	0
T84	2351	49	0	0
T85	1158	0	0	0
T86	2130	10	0	0
T96	2130	10	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22440370	1150	0	0
T42	5879	20	0	0
T43	5879	20	0	0
T44	5879	20	0	0
T52	1796	2	0	0
T56	1796	2	0	0
T57	1796	2	0	0
T79	1213	2	0	0
T80	1213	2	0	0
T81	1213	2	0	0
T82	1213	2	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22440370	2695	0	0
T42	5879	79	0	0
T43	5879	79	0	0
T44	5879	79	0	0
T51	2130	19	0	0
T52	1796	1	0	0
T56	1796	1	0	0
T57	1796	1	0	0
T79	1213	5	0	0
T80	1213	5	0	0
T96	2130	19	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22440370	1840	0	0
T42	5879	36	0	0
T43	5879	36	0	0
T44	5879	36	0	0
T45	5642	1	0	0
T51	2130	13	0	0
T52	1796	2	0	0
T56	1796	2	0	0
T57	1796	2	0	0
T84	2351	20	0	0
T96	2130	13	0	0