Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.84	100.00	80.00	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	21961730	46300	0	0
IoStatusRise_A	21961730	51055	0	0
MainStatusFall_A	21961730	46300	0	0
MainStatusRise_A	21961730	51055	0	0
UsbStatusFall_A	21961730	35600	0	0
UsbStatusRise_A	21961730	39255	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	46300	0	0
T1	2182	4	0	0
T2	41652	85	0	0
T3	1661	0	0	0
T4	4554	18	0	0
T5	3798	5	0	0
T6	11653	18	0	0
T7	2774	18	0	0
T8	38913	85	0	0
T9	11653	18	0	0
T10	1412	1	0	0
T29	0	85	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	51055	0	0
T1	2182	5	0	0
T2	41652	87	0	0
T3	1661	4	0	0
T4	4554	19	0	0
T5	3798	7	0	0
T6	11653	19	0	0
T7	2774	19	0	0
T8	38913	87	0	0
T9	11653	19	0	0
T10	1412	3	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	46300	0	0
T1	2182	4	0	0
T2	41652	85	0	0
T3	1661	0	0	0
T4	4554	18	0	0
T5	3798	5	0	0
T6	11653	18	0	0
T7	2774	18	0	0
T8	38913	85	0	0
T9	11653	18	0	0
T10	1412	1	0	0
T29	0	85	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	51055	0	0
T1	2182	5	0	0
T2	41652	87	0	0
T3	1661	4	0	0
T4	4554	19	0	0
T5	3798	7	0	0
T6	11653	19	0	0
T7	2774	19	0	0
T8	38913	87	0	0
T9	11653	19	0	0
T10	1412	3	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	35600	0	0
T1	2182	4	0	0
T2	41652	51	0	0
T3	1661	0	0	0
T4	4554	18	0	0
T5	3798	5	0	0
T6	11653	18	0	0
T7	2774	18	0	0
T8	38913	48	0	0
T9	11653	18	0	0
T10	1412	1	0	0
T29	0	51	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	39255	0	0
T1	2182	5	0	0
T2	41652	53	0	0
T3	1661	4	0	0
T4	4554	19	0	0
T5	3798	7	0	0
T6	11653	18	0	0
T7	2774	19	0	0
T8	38913	50	0	0
T9	11653	18	0	0
T10	1412	3	0	0