Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.84	100.00	80.00	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	21961730	50705	0	0
RomAllowCheckGoodState_A	21961730	50755	0	0
RomBlockActiveState_A	21961730	34550	0	0
RomBlockCheckGoodState_A	21961730	421400	0	0
RomIntgChkDisFalse_A	21961730	21458210	0	0
RomIntgChkDisTrue_A	21961730	93400	0	0
RstreqChkEsctimeout_A	21961730	3800	0	0
RstreqChkFsmterm_A	21961730	100	0	0
RstreqChkGlbesc_A	21961730	3800	0	0
RstreqChkMainpd_A	21961730	929350	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	50705	0	0
T1	2182	5	0	0
T2	41652	87	0	0
T3	1661	4	0	0
T4	4554	12	0	0
T5	3798	7	0	0
T6	11653	19	0	0
T7	2774	19	0	0
T8	38913	87	0	0
T9	11653	19	0	0
T10	1412	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	50755	0	0
T1	2182	5	0	0
T2	41652	87	0	0
T3	1661	4	0	0
T4	4554	13	0	0
T5	3798	7	0	0
T6	11653	19	0	0
T7	2774	19	0	0
T8	38913	87	0	0
T9	11653	19	0	0
T10	1412	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	34550	0	0
T5	3798	691	0	0
T6	11653	0	0	0
T7	2774	0	0	0
T8	38913	0	0	0
T9	11653	0	0	0
T10	1412	0	0	0
T13	187951	0	0	0
T29	41652	0	0	0
T34	0	691	0	0
T36	2182	0	0	0
T38	0	691	0	0
T108	4993	0	0	0
T110	0	691	0	0
T111	0	691	0	0
T112	0	691	0	0
T113	0	691	0	0
T114	0	691	0	0
T115	0	691	0	0
T116	0	691	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	421400	0	0
T2	41652	2525	0	0
T3	1661	0	0	0
T4	4554	0	0	0
T5	3798	497	0	0
T6	11653	0	0	0
T7	2774	0	0	0
T8	38913	2520	0	0
T9	11653	0	0	0
T10	1412	0	0	0
T13	0	2131	0	0
T14	0	2131	0	0
T29	41652	2525	0	0
T30	0	2525	0	0
T31	0	343	0	0
T32	0	412	0	0
T117	0	412	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	21458210	0	0
T1	2182	1833	0	0
T2	41652	41529	0	0
T3	1661	1355	0	0
T4	4554	3614	0	0
T5	3798	2399	0	0
T6	11653	11594	0	0
T7	2774	2715	0	0
T8	38913	38135	0	0
T9	11653	11594	0	0
T10	1412	1291	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	93400	0	0
T5	3798	1213	0	0
T6	11653	0	0	0
T7	2774	0	0	0
T8	38913	655	0	0
T9	11653	0	0	0
T10	1412	0	0	0
T13	187951	0	0	0
T19	0	655	0	0
T29	41652	0	0	0
T34	0	1213	0	0
T36	2182	0	0	0
T38	0	1213	0	0
T108	4993	0	0	0
T110	0	1213	0	0
T111	0	1213	0	0
T118	0	655	0	0
T119	0	655	0	0
T120	0	655	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	3800	0	0
T4	4554	7	0	0
T5	3798	2	0	0
T6	11653	0	0	0
T7	2774	0	0	0
T8	38913	0	0	0
T9	11653	0	0	0
T10	1412	1	0	0
T11	0	1	0	0
T13	187951	37	0	0
T14	0	37	0	0
T29	41652	0	0	0
T31	0	16	0	0
T33	0	16	0	0
T34	0	2	0	0
T36	2182	0	0	0
T39	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	100	0	0
T15	13356	20	0	0
T16	13356	20	0	0
T17	13356	20	0	0
T20	0	20	0	0
T21	0	20	0	0
T22	1689	0	0	0
T23	88802	0	0	0
T24	2774	0	0	0
T25	1412	0	0	0
T26	3798	0	0	0
T27	4554	0	0	0
T28	1412	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	3800	0	0
T4	4554	7	0	0
T5	3798	2	0	0
T6	11653	0	0	0
T7	2774	0	0	0
T8	38913	0	0	0
T9	11653	0	0	0
T10	1412	1	0	0
T11	0	1	0	0
T13	187951	37	0	0
T14	0	37	0	0
T29	41652	0	0	0
T31	0	16	0	0
T33	0	16	0	0
T34	0	2	0	0
T36	2182	0	0	0
T39	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21961730	929350	0	0
T2	41652	3512	0	0
T3	1661	11	0	0
T4	4554	120	0	0
T5	3798	48	0	0
T6	11653	0	0	0
T7	2774	0	0	0
T8	38913	3528	0	0
T9	11653	0	0	0
T10	1412	0	0	0
T13	0	7808	0	0
T14	0	7808	0	0
T29	41652	3512	0	0
T30	0	3512	0	0
T31	0	1720	0	0