PWRMGR Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.780s 35.744us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.650s 29.315us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.640s 24.672us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 2.020s 249.510us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 0.810s 44.993us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 0.730s 39.797us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.640s 24.672us 20 20 100.00
pwrmgr_csr_aliasing 0.810s 44.993us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.330s 283.777us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.330s 283.777us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 0.970s 51.976us 50 50 100.00
pwrmgr_lowpower_invalid 0.830s 49.976us 50 50 100.00
V2 reset pwrmgr_reset 1.130s 119.707us 50 50 100.00
pwrmgr_reset_invalid 0.940s 108.189us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.130s 119.707us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.480s 325.438us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.280s 296.241us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.940s 72.404us 50 50 100.00
V2 stress_all pwrmgr_stress_all 5.950s 2.072ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.680s 23.690us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 1.520s 103.761us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 1.520s 103.761us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.650s 29.315us 5 5 100.00
pwrmgr_csr_rw 0.640s 24.672us 20 20 100.00
pwrmgr_csr_aliasing 0.810s 44.993us 5 5 100.00
pwrmgr_same_csr_outstanding 0.730s 41.047us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.650s 29.315us 5 5 100.00
pwrmgr_csr_rw 0.640s 24.672us 20 20 100.00
pwrmgr_csr_aliasing 0.810s 44.993us 5 5 100.00
pwrmgr_same_csr_outstanding 0.730s 41.047us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.140s 131.850us 20 20 100.00
pwrmgr_sec_cm 1.280s 344.080us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 1.280s 344.080us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 1.280s 344.080us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.140s 131.850us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.050s 919.451us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.190s 968.504us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.060s 91.600us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.750s 30.369us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 1.280s 344.080us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 1.280s 344.080us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 1.280s 344.080us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.790s 33.172us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.790s 39.672us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.420s 314.831us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.640s 24.672us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.640s 24.672us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 11.970s 4.441ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1070 1070 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.39 98.22 95.58 99.44 96.00 96.32 99.73 96.40

Past Results