PWRMGR Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	1.100s	31.531us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.830s	76.384us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.920s	54.375us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.700s	72.718us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.300s	89.623us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.360s	106.346us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.920s	54.375us	20	20	100.00
		pwrmgr_csr_aliasing	1.300s	89.623us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	2.170s	277.643us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	2.170s	277.643us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.410s	29.784us	50	50	100.00
		pwrmgr_lowpower_invalid	1.160s	41.871us	49	50	98.00
V2	reset	pwrmgr_reset	44.306s		49	50	98.00
		pwrmgr_reset_invalid	1.660s	113.978us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	44.306s		49	50	98.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	44.206s		48	50	96.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	44.285s		49	50	98.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.390s	55.634us	49	50	98.00
V2	stress_all	pwrmgr_stress_all	7.870s	1.597ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.800s	56.637us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.650s	215.722us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.650s	215.722us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.830s	76.384us	5	5	100.00
		pwrmgr_csr_rw	0.920s	54.375us	20	20	100.00
		pwrmgr_csr_aliasing	1.300s	89.623us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.040s	48.622us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.830s	76.384us	5	5	100.00
		pwrmgr_csr_rw	0.920s	54.375us	20	20	100.00
		pwrmgr_csr_aliasing	1.300s	89.623us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.040s	48.622us	20	20	100.00
V2		TOTAL			534	540	98.89
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.700s	196.176us	20	20	100.00
		pwrmgr_sec_cm	2.130s	389.444us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.130s	389.444us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.130s	389.444us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.700s	196.176us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	5.240s	870.034us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	5.900s	842.059us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.540s	73.791us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	22.561s		49	50	98.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.130s	389.444us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.130s	389.444us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.130s	389.444us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	1.030s	45.775us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	1.110s	53.586us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	22.556s		49	50	98.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.920s	54.375us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.920s	54.375us	20	20	100.00
V2S		TOTAL			373	375	99.47
V3	escalation_timeout	pwrmgr_escalation_timeout	1.540s	107.593us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	25.540s	7.877ms	49	50	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1110	1120	99.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	7	58.33
V2S	9	9	7	77.78
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.96	98.21	96.58	99.62	96.00	96.32	100.00	99.02

Failure Buckets

Job returned non-zero exit code has 5 failures:

Test pwrmgr_esc_clk_rst_malfunc has 1 failures.

25.pwrmgr_esc_clk_rst_malfunc.73015852622995578091027993588538774892354839289145192382552480248995326920301
Log /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_esc_clk_rst_malfunc/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 15 12:54 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test pwrmgr_sec_cm_ctrl_config_regwen has 1 failures.

25.pwrmgr_sec_cm_ctrl_config_regwen.70466954356054467239307494790773511266580005739910127719204482232039341816727
Log /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 15 12:54 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test pwrmgr_reset has 1 failures.

26.pwrmgr_reset.105495555424448579231840705134486083409578564396877944464272107380881206737916
Log /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_reset/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 15 12:54 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test pwrmgr_lowpower_wakeup_race has 1 failures.

26.pwrmgr_lowpower_wakeup_race.42283768193491883153113779415095256553726812554661523711713994674172764543143
Log /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_lowpower_wakeup_race/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 15 12:54 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test pwrmgr_wakeup_reset has 1 failures.

26.pwrmgr_wakeup_reset.78781957880933363608844643507164164782735780282605095791149742690224721118275
Log /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_wakeup_reset/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 15 12:54 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 1 failures:
- Test pwrmgr_lowpower_invalid has 1 failures.
  - 6.pwrmgr_lowpower_invalid.7013548097329164828702396761564680304452792615793209188612869846693327539361
    Line 64, in log /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_lowpower_invalid/latest/run.log
```
  UVM_FATAL @  37338550 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
  UVM_INFO @  37338550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwrmgr_wakeup_reset has 1 failures.
  - 10.pwrmgr_wakeup_reset.98797854118691190326735565216481212009819009020452753112714337984346518476068
    Line 193, in log /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_wakeup_reset/latest/run.log
```
  UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pwrmgr_scoreboard.sv:254) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 1 failures:
- Test pwrmgr_disable_rom_integrity_check has 1 failures.
  - 12.pwrmgr_disable_rom_integrity_check.15921480643141938786139240273158272344952672019440197925006167142187442518249
    Line 81, in log /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_disable_rom_integrity_check/latest/run.log
```
  UVM_ERROR @  34124624 ps: (pwrmgr_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @  34124624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:
- Test pwrmgr_escalation_timeout has 1 failures.
  - 36.pwrmgr_escalation_timeout.96576566558991542396765966453177679499166862004078885496023126128412961191471
    Line 64, in log /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_escalation_timeout/latest/run.log
```
      Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
  UVM_ERROR @ 100643164 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
  UVM_INFO @ 100643164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:101) [pwrmgr_common_vseq] wait timeout occurred! has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 39.pwrmgr_stress_all_with_rand_reset.69374370248413063538858948046115082775080460331457082255669248787540728205606
    Line 2802, in log /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11831667248 ps: (cip_base_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
  UVM_INFO @ 11831667248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```