PWRMGR Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	1.030s	40.820us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	1.000s	27.660us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	1.040s	22.737us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.260s	268.243us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.590s	464.179us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	2.030s	131.649us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	1.040s	22.737us	20	20	100.00
		pwrmgr_csr_aliasing	1.590s	464.179us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.740s	298.615us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.740s	298.615us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.540s	34.787us	50	50	100.00
		pwrmgr_lowpower_invalid	1.160s	44.061us	50	50	100.00
V2	reset	pwrmgr_reset	1.570s	84.895us	50	50	100.00
		pwrmgr_reset_invalid	1.730s	101.029us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.570s	84.895us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.940s	247.105us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	2.110s	264.638us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.340s	52.606us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.190s	1.847ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.960s	22.590us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	3.950s	139.743us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	3.950s	139.743us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	1.000s	27.660us	5	5	100.00
		pwrmgr_csr_rw	1.040s	22.737us	20	20	100.00
		pwrmgr_csr_aliasing	1.590s	464.179us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.470s	49.409us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	1.000s	27.660us	5	5	100.00
		pwrmgr_csr_rw	1.040s	22.737us	20	20	100.00
		pwrmgr_csr_aliasing	1.590s	464.179us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.470s	49.409us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	2.710s	195.774us	20	20	100.00
		pwrmgr_sec_cm	1.830s	1.615ms	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.830s	1.615ms	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.830s	1.615ms	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	2.710s	195.774us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	5.500s	930.023us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	5.240s	946.126us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.390s	94.343us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.990s	29.293us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.830s	1.615ms	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.830s	1.615ms	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.830s	1.615ms	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	1.020s	33.914us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	1.040s	39.982us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	2.100s	261.078us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	1.040s	22.737us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	1.040s	22.737us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.860s	158.912us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	40.350s	10.974ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1119	1120	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:755) [pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 1.pwrmgr_stress_all_with_rand_reset.14855928201853011233413943604913520602937003353052187854188883705826189322613
      Line 803, in log /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1248836072 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1248836072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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