Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	634167	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

299384

1

T1

166

T2

61

T3

713

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	579232	1			T1	289		T2	155		T3	1475
values[0x0]	177359	1			T1	51		T2	18		T3	221
values[0x1]	176960	1			T1	57		T2	28		T3	231

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	502345	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

431206

1

T1

208

T2

92

T3

980

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2911	1			T1	2		T8	5		T9	1
valid_sources[0x01]	2744	1			T8	1		T15	32		T36	6
valid_sources[0x02]	7214	1			T1	11		T2	201		T9	1
valid_sources[0x03]	2697	1			T8	6		T9	1		T50	2
valid_sources[0x04]	2776	1			T6	6		T8	1		T15	54
valid_sources[0x05]	2644	1			T1	1		T6	2		T8	11
valid_sources[0x06]	2932	1			T8	2		T15	46		T35	2
valid_sources[0x07]	2799	1			T8	7		T9	2		T50	2
valid_sources[0x08]	2803	1			T1	8		T8	2		T9	4
valid_sources[0x09]	2968	1			T9	1		T10	2		T50	3
valid_sources[0x0a]	2785	1			T6	6		T8	2		T10	6
valid_sources[0x0b]	2731	1			T6	14		T9	1		T10	4
valid_sources[0x0c]	2833	1			T1	2		T8	3		T9	1
valid_sources[0x0d]	3783	1			T1	2		T8	1		T9	1
valid_sources[0x0e]	2912	1			T8	3		T9	1		T15	44
valid_sources[0x0f]	2954	1			T6	29		T8	4		T15	48
valid_sources[0x10]	2864	1			T6	2		T9	3		T15	41
valid_sources[0x11]	3769	1			T8	1		T10	49		T13	1
valid_sources[0x12]	4169	1			T1	1		T8	2		T10	3
valid_sources[0x13]	3459	1			T1	3		T8	6		T50	1
valid_sources[0x14]	3124	1			T6	1		T8	4		T15	51
valid_sources[0x15]	2854	1			T1	10		T6	1		T8	3
valid_sources[0x16]	3233	1			T8	4		T9	1		T10	16
valid_sources[0x17]	4184	1			T6	3		T8	3		T9	2
valid_sources[0x18]	2972	1			T6	16		T8	4		T9	2
valid_sources[0x19]	2924	1			T8	11		T9	2		T13	1
valid_sources[0x1a]	2712	1			T8	1		T9	2		T10	13
valid_sources[0x1b]	2875	1			T8	2		T9	1		T13	1
valid_sources[0x1c]	2949	1			T8	3		T10	5		T15	37
valid_sources[0x1d]	3022	1			T1	2		T8	2		T9	2
valid_sources[0x1e]	2731	1			T8	1		T9	2		T50	3
valid_sources[0x1f]	3159	1			T1	1		T8	2		T9	1
valid_sources[0x20]	2724	1			T8	3		T9	1		T10	15
valid_sources[0x21]	2792	1			T8	6		T15	39		T35	1
valid_sources[0x22]	3510	1			T6	39		T8	4		T9	1
valid_sources[0x23]	3103	1			T1	1		T8	6		T15	38
valid_sources[0x24]	3086	1			T8	6		T10	1		T15	49
valid_sources[0x25]	2915	1			T8	1		T10	20		T50	2
valid_sources[0x26]	2942	1			T1	5		T5	1		T6	3
valid_sources[0x27]	3118	1			T6	1		T8	1		T9	1
valid_sources[0x28]	2838	1			T8	3		T50	2		T15	42
valid_sources[0x29]	3020	1			T8	3		T9	2		T10	21
valid_sources[0x2a]	2753	1			T8	4		T9	1		T13	1
valid_sources[0x2b]	5299	1			T8	4		T50	3		T15	41
valid_sources[0x2c]	5920	1			T4	1		T6	5		T8	9
valid_sources[0x2d]	3105	1			T6	2		T8	6		T50	6
valid_sources[0x2e]	3099	1			T8	3		T9	1		T10	44
valid_sources[0x2f]	2944	1			T8	1		T9	1		T13	1
valid_sources[0x30]	4185	1			T8	4		T9	3		T13	1
valid_sources[0x31]	2988	1			T8	4		T9	2		T13	1
valid_sources[0x32]	3067	1			T6	2		T8	13		T15	43
valid_sources[0x33]	3574	1			T8	3		T15	39		T35	3
valid_sources[0x34]	4628	1			T4	11		T8	8		T10	25
valid_sources[0x35]	2895	1			T8	4		T9	2		T10	4
valid_sources[0x36]	5595	1			T6	17		T8	4		T9	1
valid_sources[0x37]	2831	1			T8	6		T50	1		T15	39
valid_sources[0x38]	5450	1			T1	4		T3	1927		T8	5
valid_sources[0x39]	2803	1			T8	8		T15	39		T36	6
valid_sources[0x3a]	2765	1			T8	1		T9	1		T10	4
valid_sources[0x3b]	3076	1			T8	6		T50	2		T15	35
valid_sources[0x3c]	3047	1			T8	1		T9	1		T13	3
valid_sources[0x3d]	2714	1			T6	18		T8	8		T9	1
valid_sources[0x3e]	2862	1			T1	1		T8	6		T9	2
valid_sources[0x3f]	14129	1			T6	1		T8	3		T15	48
valid_sources[0x40]	2594	1			T8	2		T9	1		T13	4
valid_sources[0x41]	2891	1			T1	1		T8	1		T15	37
valid_sources[0x42]	2788	1			T9	2		T50	3		T15	61
valid_sources[0x43]	2857	1			T1	3		T6	10		T8	5
valid_sources[0x44]	2800	1			T8	3		T10	10		T14	1
valid_sources[0x45]	3110	1			T1	7		T6	3		T8	8
valid_sources[0x46]	3063	1			T8	2		T9	1		T10	44
valid_sources[0x47]	5598	1			T6	1		T8	4		T9	2
valid_sources[0x48]	2995	1			T8	6		T13	1		T15	43
valid_sources[0x49]	3963	1			T1	2		T6	18		T8	1
valid_sources[0x4a]	2724	1			T8	4		T13	1		T15	57
valid_sources[0x4b]	2774	1			T8	1		T13	1		T50	1
valid_sources[0x4c]	2738	1			T8	2		T15	48		T35	1
valid_sources[0x4d]	2934	1			T4	7		T8	7		T15	47
valid_sources[0x4e]	8347	1			T8	9		T50	3		T15	48
valid_sources[0x4f]	3343	1			T8	3		T9	2		T50	1
valid_sources[0x50]	3101	1			T9	2		T10	28		T50	13
valid_sources[0x51]	2524	1			T8	5		T9	1		T10	17
valid_sources[0x52]	5439	1			T8	3		T10	145		T50	3
valid_sources[0x53]	2963	1			T6	14		T8	1		T10	2
valid_sources[0x54]	3971	1			T6	6		T9	1		T10	20
valid_sources[0x55]	3314	1			T1	5		T8	3		T13	1
valid_sources[0x56]	2767	1			T6	3		T8	5		T10	56
valid_sources[0x57]	3067	1			T1	11		T6	14		T8	2
valid_sources[0x58]	2836	1			T8	2		T15	43		T35	1
valid_sources[0x59]	2963	1			T50	10		T15	57		T35	1
valid_sources[0x5a]	3444	1			T8	3		T9	1		T15	48
valid_sources[0x5b]	2849	1			T1	4		T8	8		T9	1
valid_sources[0x5c]	2720	1			T8	6		T9	1		T15	50
valid_sources[0x5d]	3738	1			T6	3		T8	1		T9	1
valid_sources[0x5e]	3608	1			T8	3		T15	37		T36	4
valid_sources[0x5f]	4429	1			T1	1		T6	4		T8	4
valid_sources[0x60]	2803	1			T8	5		T9	2		T10	34
valid_sources[0x61]	2566	1			T6	49		T8	2		T50	2
valid_sources[0x62]	3329	1			T6	13		T8	4		T15	42
valid_sources[0x63]	10942	1			T8	5		T9	1		T10	29
valid_sources[0x64]	3149	1			T8	12		T9	1		T50	3
valid_sources[0x65]	3704	1			T1	2		T8	1		T13	1
valid_sources[0x66]	4311	1			T8	6		T9	2		T50	3
valid_sources[0x67]	3617	1			T8	5		T9	1		T10	1
valid_sources[0x68]	3044	1			T6	14		T8	1		T9	2
valid_sources[0x69]	3107	1			T1	1		T8	3		T9	1
valid_sources[0x6a]	2981	1			T8	7		T9	2		T10	26
valid_sources[0x6b]	2616	1			T8	8		T9	1		T50	5
valid_sources[0x6c]	2779	1			T8	5		T9	1		T10	12
valid_sources[0x6d]	2914	1			T1	10		T8	4		T9	1
valid_sources[0x6e]	2764	1			T1	10		T13	1		T15	36
valid_sources[0x6f]	2889	1			T8	3		T10	11		T15	43
valid_sources[0x70]	3348	1			T10	65		T50	1		T15	42
valid_sources[0x71]	5335	1			T8	5		T9	1		T13	2
valid_sources[0x72]	2872	1			T8	7		T15	50		T36	16
valid_sources[0x73]	2647	1			T1	10		T8	3		T9	3
valid_sources[0x74]	2667	1			T8	5		T15	48		T35	1
valid_sources[0x75]	7957	1			T1	13		T8	4		T10	27
valid_sources[0x76]	3479	1			T8	2		T50	4		T15	46
valid_sources[0x77]	8540	1			T1	3		T8	10		T9	1
valid_sources[0x78]	3953	1			T6	4		T8	1		T50	3
valid_sources[0x79]	2932	1			T1	1		T8	3		T9	3
valid_sources[0x7a]	3081	1			T8	4		T10	36		T50	9
valid_sources[0x7b]	3061	1			T1	5		T6	35		T8	9
valid_sources[0x7c]	15679	1			T8	3		T9	2		T13	1
valid_sources[0x7d]	3230	1			T8	1		T50	6		T15	44
valid_sources[0x7e]	2946	1			T8	2		T50	2		T15	45
valid_sources[0x7f]	3453	1			T6	5		T8	1		T9	1
valid_sources[0x80]	2868	1			T1	1		T8	5		T10	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

197678

1

T1

134

T2

54

T3

593

values[0x0]

all_enables

biggest_size

66224

1

T1

19

T2

6

T3

88

values[0x1]

all_enables

biggest_size

35482

1

T1

13

T2

1

T3

32