SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35166 | 1 | T3 | 298 | T6 | 399 | T8 | 286 | ||||
others[1] | 34783 | 1 | T3 | 298 | T6 | 376 | T8 | 299 | ||||
others[2] | 34798 | 1 | T3 | 292 | T6 | 369 | T8 | 288 | ||||
others[3] | 58645 | 1 | T3 | 494 | T6 | 707 | T8 | 523 | ||||
false | 20263 | 1 | T3 | 50 | T6 | 50 | T8 | 50 | ||||
true | 30619 | 1 | T1 | 1 | T2 | 1 | T3 | 52 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34998 | 1 | T3 | 318 | T6 | 399 | T8 | 317 | ||||
others[1] | 34836 | 1 | T3 | 306 | T6 | 367 | T8 | 308 | ||||
others[2] | 35218 | 1 | T3 | 304 | T6 | 437 | T8 | 294 | ||||
others[3] | 58455 | 1 | T3 | 478 | T6 | 662 | T8 | 481 | ||||
false | 12730 | 1 | T3 | 50 | T6 | 50 | T8 | 50 | ||||
true | 23157 | 1 | T1 | 1 | T2 | 1 | T3 | 52 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 694 | 1 | T15 | 5 | T37 | 2 | T39 | 2 | ||||
others[1] | 703 | 1 | T15 | 6 | T37 | 1 | T39 | 1 | ||||
others[2] | 737 | 1 | T13 | 1 | T15 | 10 | T41 | 1 | ||||
others[3] | 1162 | 1 | T2 | 1 | T15 | 9 | T35 | 1 | ||||
false | 14396 | 1 | T1 | 1 | T2 | 6 | T3 | 2 | ||||
true | 4358 | 1 | T2 | 4 | T13 | 3 | T15 | 52 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |