Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T38

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	24136295	6554	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	24136295	258604	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	24136295	10150672	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	24136295	258592	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	24136295	6554	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	24136295	258604	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	24136295	10150672	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	24136295	258592	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	6554	0	0
T3	49045	22	0	0
T4	1668	0	0	0
T5	2392	0	0	0
T6	39491	19	0	0
T7	1335	0	0	0
T8	22249	24	0	0
T9	5357	0	0	0
T10	52819	18	0	0
T13	3170	0	0	0
T14	1453	0	0	0
T15	0	53	0	0
T16	0	17	0	0
T36	0	24	0	0
T38	0	6	0	0
T46	0	22	0	0
T67	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	258604	0	0
T3	49045	1414	0	0
T4	1668	0	0	0
T5	2392	0	0	0
T6	39491	555	0	0
T7	1335	0	0	0
T8	22249	582	0	0
T9	5357	0	0	0
T10	52819	1223	0	0
T13	3170	0	0	0
T14	1453	0	0	0
T15	0	1608	0	0
T16	0	461	0	0
T36	0	1293	0	0
T38	0	627	0	0
T46	0	526	0	0
T67	0	12	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	10150672	0	0
T1	7352	5254	0	0
T2	4664	0	0	0
T3	49045	25200	0	0
T4	1668	301	0	0
T5	2392	0	0	0
T6	39491	18047	0	0
T7	1335	0	0	0
T8	22249	11218	0	0
T9	5357	2211	0	0
T10	52819	20951	0	0
T15	0	129792	0	0
T50	0	4468	0	0
T54	0	606	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	258592	0	0
T3	49045	1414	0	0
T4	1668	0	0	0
T5	2392	0	0	0
T6	39491	555	0	0
T7	1335	0	0	0
T8	22249	582	0	0
T9	5357	0	0	0
T10	52819	1223	0	0
T13	3170	0	0	0
T14	1453	0	0	0
T15	0	1608	0	0
T16	0	461	0	0
T36	0	1293	0	0
T38	0	627	0	0
T46	0	526	0	0
T67	0	12	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	6554	0	0
T3	49045	22	0	0
T4	1668	0	0	0
T5	2392	0	0	0
T6	39491	19	0	0
T7	1335	0	0	0
T8	22249	24	0	0
T9	5357	0	0	0
T10	52819	18	0	0
T13	3170	0	0	0
T14	1453	0	0	0
T15	0	53	0	0
T16	0	17	0	0
T36	0	24	0	0
T38	0	6	0	0
T46	0	22	0	0
T67	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	258604	0	0
T3	49045	1414	0	0
T4	1668	0	0	0
T5	2392	0	0	0
T6	39491	555	0	0
T7	1335	0	0	0
T8	22249	582	0	0
T9	5357	0	0	0
T10	52819	1223	0	0
T13	3170	0	0	0
T14	1453	0	0	0
T15	0	1608	0	0
T16	0	461	0	0
T36	0	1293	0	0
T38	0	627	0	0
T46	0	526	0	0
T67	0	12	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	10150672	0	0
T1	7352	5254	0	0
T2	4664	0	0	0
T3	49045	25200	0	0
T4	1668	301	0	0
T5	2392	0	0	0
T6	39491	18047	0	0
T7	1335	0	0	0
T8	22249	11218	0	0
T9	5357	2211	0	0
T10	52819	20951	0	0
T15	0	129792	0	0
T50	0	4468	0	0
T54	0	606	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	258592	0	0
T3	49045	1414	0	0
T4	1668	0	0	0
T5	2392	0	0	0
T6	39491	555	0	0
T7	1335	0	0	0
T8	22249	582	0	0
T9	5357	0	0	0
T10	52819	1223	0	0
T13	3170	0	0	0
T14	1453	0	0	0
T15	0	1608	0	0
T16	0	461	0	0
T36	0	1293	0	0
T38	0	627	0	0
T46	0	526	0	0
T67	0	12	0	0