Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24718539	16009	0	0
intr_enable_rd_A	24718539	53323	0	0
reset_en_rd_A	24718539	1113	0	0
reset_en_regwen_rd_A	24718539	895	0	0
wake_info_capture_dis_rd_A	24718539	1027	0	0
wakeup_en_rd_A	24718539	1820	0	0
wakeup_en_regwen_rd_A	24718539	1002	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24718539	16009	0	0
T15	307596	8	0	0
T22	249550	107	0	0
T23	0	8	0	0
T35	3379	0	0	0
T45	3290	0	0	0
T47	0	48	0	0
T48	0	11	0	0
T49	0	949	0	0
T52	0	1092	0	0
T53	0	796	0	0
T54	2860	0	0	0
T67	1697	0	0	0
T74	0	35	0	0
T79	0	3	0	0
T101	3109	0	0	0
T102	2099	0	0	0
T103	2033	0	0	0
T104	14877	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24718539	53323	0	0
T6	39491	174	0	0
T7	1335	0	0	0
T8	22249	0	0	0
T9	5357	0	0	0
T10	52819	0	0	0
T11	2417	0	0	0
T13	3170	13	0	0
T14	1453	0	0	0
T15	307596	1623	0	0
T29	0	55	0	0
T33	0	40	0	0
T50	7740	0	0	0
T55	0	24	0	0
T102	0	10	0	0
T105	0	151	0	0
T106	0	135	0	0
T107	0	51	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24718539	1113	0	0
T15	307596	1	0	0
T35	3379	0	0	0
T51	0	127	0	0
T52	14769	11	0	0
T53	13990	33	0	0
T54	2860	0	0	0
T56	4436	40	0	0
T67	1697	0	0	0
T78	0	15	0	0
T81	4321	85	0	0
T83	0	8	0	0
T101	3109	0	0	0
T102	2099	0	0	0
T108	0	53	0	0
T109	0	18	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24718539	895	0	0
T15	307596	10	0	0
T35	3379	0	0	0
T51	0	83	0	0
T52	14769	13	0	0
T53	13990	17	0	0
T54	2860	0	0	0
T56	4436	42	0	0
T67	1697	0	0	0
T78	0	12	0	0
T81	4321	90	0	0
T83	0	8	0	0
T101	3109	0	0	0
T102	2099	0	0	0
T108	0	42	0	0
T109	0	10	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24718539	1027	0	0
T15	307596	5	0	0
T35	3379	0	0	0
T51	0	72	0	0
T52	14769	8	0	0
T53	13990	38	0	0
T54	2860	0	0	0
T56	4436	8	0	0
T67	1697	0	0	0
T78	0	6	0	0
T81	4321	112	0	0
T83	0	8	0	0
T101	3109	0	0	0
T102	2099	0	0	0
T108	0	55	0	0
T109	0	22	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24718539	1820	0	0
T15	307596	11	0	0
T35	3379	0	0	0
T51	0	243	0	0
T52	14769	33	0	0
T53	13990	37	0	0
T54	2860	0	0	0
T56	4436	49	0	0
T67	1697	0	0	0
T73	0	2	0	0
T78	0	70	0	0
T81	4321	98	0	0
T83	0	5	0	0
T101	3109	0	0	0
T102	2099	0	0	0
T108	0	63	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24718539	1002	0	0
T15	307596	2	0	0
T35	3379	0	0	0
T51	0	79	0	0
T52	14769	35	0	0
T53	13990	34	0	0
T54	2860	0	0	0
T56	4436	50	0	0
T67	1697	0	0	0
T73	0	3	0	0
T78	0	2	0	0
T81	4321	121	0	0
T101	3109	0	0	0
T102	2099	0	0	0
T108	0	23	0	0
T109	0	24	0	0