Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	24136295	57114	0	0
IoStatusRise_A	24136295	63570	0	0
MainStatusFall_A	24136295	57115	0	0
MainStatusRise_A	24136295	63571	0	0
UsbStatusFall_A	24136295	44476	0	0
UsbStatusRise_A	24136295	49734	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	57114	0	0
T1	7352	15	0	0
T2	4664	13	0	0
T3	49045	81	0	0
T4	1668	15	0	0
T5	2392	1	0	0
T6	39491	82	0	0
T7	1335	0	0	0
T8	22249	87	0	0
T9	5357	13	0	0
T10	52819	84	0	0
T13	0	5	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	63570	0	0
T1	7352	16	0	0
T2	4664	14	0	0
T3	49045	83	0	0
T4	1668	16	0	0
T5	2392	3	0	0
T6	39491	83	0	0
T7	1335	3	0	0
T8	22249	88	0	0
T9	5357	14	0	0
T10	52819	86	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	57115	0	0
T1	7352	15	0	0
T2	4664	13	0	0
T3	49045	81	0	0
T4	1668	15	0	0
T5	2392	1	0	0
T6	39491	82	0	0
T7	1335	0	0	0
T8	22249	87	0	0
T9	5357	13	0	0
T10	52819	84	0	0
T13	0	5	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	63571	0	0
T1	7352	16	0	0
T2	4664	14	0	0
T3	49045	83	0	0
T4	1668	16	0	0
T5	2392	3	0	0
T6	39491	83	0	0
T7	1335	3	0	0
T8	22249	88	0	0
T9	5357	14	0	0
T10	52819	86	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	44476	0	0
T1	7352	6	0	0
T2	4664	13	0	0
T3	49045	38	0	0
T4	1668	15	0	0
T5	2392	1	0	0
T6	39491	59	0	0
T7	1335	0	0	0
T8	22249	62	0	0
T9	5357	11	0	0
T10	52819	41	0	0
T13	0	5	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	49734	0	0
T1	7352	7	0	0
T2	4664	14	0	0
T3	49045	39	0	0
T4	1668	16	0	0
T5	2392	3	0	0
T6	39491	60	0	0
T7	1335	3	0	0
T8	22249	63	0	0
T9	5357	12	0	0
T10	52819	43	0	0