Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	24136295	63168	0	0
RomAllowCheckGoodState_A	24136295	63222	0	0
RomBlockActiveState_A	24136295	20835	0	0
RomBlockCheckGoodState_A	24136295	440650	0	0
RomIntgChkDisFalse_A	24136295	23488458	0	0
RomIntgChkDisTrue_A	24136295	95955	0	0
RstreqChkEsctimeout_A	24136295	4577	0	0
RstreqChkFsmterm_A	24136295	160	0	0
RstreqChkGlbesc_A	24136295	4578	0	0
RstreqChkMainpd_A	24136295	961130	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	63168	0	0
T1	7352	16	0	0
T2	4664	14	0	0
T3	49045	83	0	0
T4	1668	16	0	0
T5	2392	3	0	0
T6	39491	83	0	0
T7	1335	3	0	0
T8	22249	88	0	0
T9	5357	14	0	0
T10	52819	86	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	63222	0	0
T1	7352	16	0	0
T2	4664	14	0	0
T3	49045	83	0	0
T4	1668	16	0	0
T5	2392	3	0	0
T6	39491	83	0	0
T7	1335	3	0	0
T8	22249	88	0	0
T9	5357	14	0	0
T10	52819	86	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	20835	0	0
T11	2417	0	0	0
T13	3170	611	0	0
T14	1453	0	0	0
T15	307596	0	0	0
T35	3379	0	0	0
T40	0	177	0	0
T46	0	11	0	0
T50	7740	0	0	0
T54	2860	0	0	0
T67	1697	0	0	0
T101	3109	0	0	0
T102	2099	0	0	0
T110	0	42	0	0
T111	0	13	0	0
T112	0	305	0	0
T113	0	9	0	0
T114	0	1002	0	0
T115	0	114	0	0
T116	0	7	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	440650	0	0
T3	49045	3829	0	0
T4	1668	0	0	0
T5	2392	0	0	0
T6	39491	2266	0	0
T7	1335	0	0	0
T8	22249	1314	0	0
T9	5357	0	0	0
T10	52819	3978	0	0
T13	3170	234	0	0
T14	1453	0	0	0
T15	0	1949	0	0
T16	0	712	0	0
T36	0	3417	0	0
T38	0	414	0	0
T46	0	1283	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	23488458	0	0
T1	7352	7293	0	0
T2	4664	4598	0	0
T3	49045	47886	0	0
T4	1668	1591	0	0
T5	2392	2224	0	0
T6	39491	39425	0	0
T7	1335	1124	0	0
T8	22249	21963	0	0
T9	5357	5296	0	0
T10	52819	52656	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	95955	0	0
T3	49045	1037	0	0
T4	1668	0	0	0
T5	2392	0	0	0
T6	39491	0	0	0
T7	1335	0	0	0
T8	22249	218	0	0
T9	5357	0	0	0
T10	52819	0	0	0
T13	3170	1179	0	0
T14	1453	0	0	0
T36	0	1335	0	0
T40	0	253	0	0
T105	0	2236	0	0
T110	0	27	0	0
T112	0	719	0	0
T114	0	133	0	0
T117	0	469	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	4577	0	0
T2	4664	5	0	0
T3	49045	0	0	0
T4	1668	0	0	0
T5	2392	1	0	0
T6	39491	0	0	0
T7	1335	0	0	0
T8	22249	0	0	0
T9	5357	0	0	0
T10	52819	0	0	0
T11	0	1	0	0
T13	3170	2	0	0
T14	0	3	0	0
T15	0	51	0	0
T35	0	5	0	0
T37	0	9	0	0
T39	0	6	0	0
T42	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	160	0	0
T19	16231	40	0	0
T20	0	20	0	0
T21	0	40	0	0
T24	0	20	0	0
T25	0	40	0	0
T26	2427	0	0	0
T27	54578	0	0	0
T28	3776	0	0	0
T29	5990	0	0	0
T30	2856	0	0	0
T31	782	0	0	0
T32	7487	0	0	0
T33	15778	0	0	0
T34	4185	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	4578	0	0
T2	4664	5	0	0
T3	49045	0	0	0
T4	1668	0	0	0
T5	2392	1	0	0
T6	39491	0	0	0
T7	1335	0	0	0
T8	22249	0	0	0
T9	5357	0	0	0
T10	52819	0	0	0
T11	0	1	0	0
T13	3170	2	0	0
T14	0	3	0	0
T15	0	51	0	0
T35	0	5	0	0
T37	0	9	0	0
T39	0	6	0	0
T42	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24136295	961130	0	0
T2	4664	243	0	0
T3	49045	5420	0	0
T4	1668	0	0	0
T5	2392	0	0	0
T6	39491	1871	0	0
T7	1335	11	0	0
T8	22249	2120	0	0
T9	5357	0	0	0
T10	52819	4702	0	0
T13	3170	42	0	0
T15	0	4339	0	0
T35	0	168	0	0
T101	0	17	0	0