Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	619617	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

304200

1

T1

18

T2

23

T3

492

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	588354	1			T1	26		T2	73		T3	1040
values[0x0]	167590	1			T1	50		T2	12		T3	220
values[0x1]	167873	1			T1	34		T2	10		T3	232

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	490452	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

433365

1

T1

33

T2

42

T3

692

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2841	1			T1	1		T3	1		T7	2
valid_sources[0x01]	2686	1			T1	1		T3	4		T33	9
valid_sources[0x02]	4223	1			T1	1		T3	4		T4	1
valid_sources[0x03]	2535	1			T3	7		T33	2		T72	1
valid_sources[0x04]	2568	1			T3	5		T4	1		T33	5
valid_sources[0x05]	2747	1			T3	7		T33	6		T73	2
valid_sources[0x06]	2828	1			T3	4		T4	3		T7	1
valid_sources[0x07]	4925	1			T3	3		T4	2		T33	3
valid_sources[0x08]	2650	1			T1	2		T3	9		T4	1
valid_sources[0x09]	2512	1			T3	4		T33	8		T73	2
valid_sources[0x0a]	2730	1			T3	7		T4	1		T7	1
valid_sources[0x0b]	2399	1			T3	10		T33	4		T73	1
valid_sources[0x0c]	2493	1			T1	1		T3	4		T4	1
valid_sources[0x0d]	3030	1			T2	1		T3	9		T4	1
valid_sources[0x0e]	3250	1			T3	2		T4	1		T7	1
valid_sources[0x0f]	2498	1			T1	1		T3	7		T4	2
valid_sources[0x10]	2623	1			T3	5		T4	3		T7	3
valid_sources[0x11]	2958	1			T3	10		T33	8		T73	2
valid_sources[0x12]	2553	1			T3	5		T4	1		T7	2
valid_sources[0x13]	2674	1			T1	1		T3	17		T7	4
valid_sources[0x14]	2717	1			T2	2		T3	2		T4	1
valid_sources[0x15]	3457	1			T1	1		T3	5		T7	1
valid_sources[0x16]	3193	1			T3	8		T4	1		T33	5
valid_sources[0x17]	2591	1			T2	3		T3	3		T4	1
valid_sources[0x18]	2720	1			T3	10		T4	1		T33	3
valid_sources[0x19]	3400	1			T3	5		T33	4		T74	2
valid_sources[0x1a]	2658	1			T2	1		T3	10		T4	3
valid_sources[0x1b]	5528	1			T3	4		T4	4		T33	4
valid_sources[0x1c]	2719	1			T3	8		T4	2		T6	1
valid_sources[0x1d]	2598	1			T3	5		T33	3		T73	2
valid_sources[0x1e]	2685	1			T1	1		T3	7		T7	1
valid_sources[0x1f]	3934	1			T3	4		T4	1		T33	1
valid_sources[0x20]	3693	1			T3	7		T4	1		T7	1
valid_sources[0x21]	2646	1			T3	2		T4	1		T7	2
valid_sources[0x22]	4584	1			T1	1		T2	1		T3	2
valid_sources[0x23]	2935	1			T2	1		T3	5		T4	1
valid_sources[0x24]	3907	1			T2	2		T3	7		T7	3
valid_sources[0x25]	3681	1			T3	8		T4	1		T6	2
valid_sources[0x26]	3027	1			T2	1		T3	13		T7	2
valid_sources[0x27]	4987	1			T1	2		T3	7		T33	5
valid_sources[0x28]	2617	1			T3	6		T6	1		T33	3
valid_sources[0x29]	2596	1			T1	1		T3	6		T4	1
valid_sources[0x2a]	2577	1			T1	2		T3	14		T33	2
valid_sources[0x2b]	12654	1			T1	1		T3	13		T4	1
valid_sources[0x2c]	2476	1			T1	1		T2	1		T3	6
valid_sources[0x2d]	2798	1			T4	3		T33	2		T73	1
valid_sources[0x2e]	3651	1			T1	1		T4	1		T33	5
valid_sources[0x2f]	4827	1			T2	2		T3	2		T4	1
valid_sources[0x30]	3092	1			T3	11		T33	1		T73	2
valid_sources[0x31]	3799	1			T1	1		T3	1		T72	2
valid_sources[0x32]	3099	1			T2	1		T3	3		T4	1
valid_sources[0x33]	3028	1			T2	3		T3	5		T7	1
valid_sources[0x34]	3201	1			T3	6		T7	2		T33	3
valid_sources[0x35]	6974	1			T3	4		T4	3		T7	2
valid_sources[0x36]	2820	1			T3	9		T4	2		T33	3
valid_sources[0x37]	3775	1			T2	1		T3	8		T4	1
valid_sources[0x38]	9595	1			T3	3		T33	6		T73	2
valid_sources[0x39]	2532	1			T3	5		T4	1		T33	2
valid_sources[0x3a]	2920	1			T3	7		T4	1		T73	1
valid_sources[0x3b]	2953	1			T1	1		T2	1		T3	7
valid_sources[0x3c]	3135	1			T1	1		T3	4		T4	1
valid_sources[0x3d]	2930	1			T3	5		T7	2		T33	3
valid_sources[0x3e]	3269	1			T3	3		T4	2		T7	8
valid_sources[0x3f]	2711	1			T3	6		T21	53		T23	9
valid_sources[0x40]	2653	1			T3	7		T4	3		T33	4
valid_sources[0x41]	3590	1			T1	1		T2	1		T3	2
valid_sources[0x42]	20603	1			T1	1		T3	6		T7	1
valid_sources[0x43]	5335	1			T1	1		T3	11		T5	1611
valid_sources[0x44]	2710	1			T3	5		T7	4		T33	9
valid_sources[0x45]	2539	1			T2	2		T3	9		T4	1
valid_sources[0x46]	2793	1			T2	3		T3	2		T4	1
valid_sources[0x47]	6463	1			T1	1		T2	1		T3	1
valid_sources[0x48]	8438	1			T2	4		T3	5		T7	1
valid_sources[0x49]	3206	1			T3	12		T7	1		T14	99
valid_sources[0x4a]	2566	1			T3	5		T4	1		T33	2
valid_sources[0x4b]	3066	1			T1	2		T3	1		T4	1
valid_sources[0x4c]	2903	1			T3	3		T4	1		T7	1
valid_sources[0x4d]	2707	1			T1	2		T3	2		T4	2
valid_sources[0x4e]	2489	1			T3	10		T7	6		T33	3
valid_sources[0x4f]	2776	1			T1	2		T2	3		T3	3
valid_sources[0x50]	2993	1			T1	1		T3	6		T4	2
valid_sources[0x51]	2792	1			T1	2		T3	4		T33	4
valid_sources[0x52]	2830	1			T2	1		T3	8		T7	2
valid_sources[0x53]	2582	1			T3	2		T4	2		T7	4
valid_sources[0x54]	3694	1			T1	1		T3	10		T4	1
valid_sources[0x55]	2738	1			T2	1		T3	2		T7	1
valid_sources[0x56]	2810	1			T2	1		T3	4		T4	1
valid_sources[0x57]	6941	1			T1	1		T3	4		T4	1
valid_sources[0x58]	5346	1			T1	1		T3	5		T7	6
valid_sources[0x59]	2537	1			T2	2		T3	4		T21	46
valid_sources[0x5a]	2549	1			T1	1		T7	2		T33	5
valid_sources[0x5b]	2829	1			T3	3		T4	2		T6	2
valid_sources[0x5c]	2924	1			T3	8		T4	2		T7	5
valid_sources[0x5d]	4020	1			T3	4		T4	1		T33	1
valid_sources[0x5e]	2822	1			T3	6		T7	1		T33	6
valid_sources[0x5f]	4226	1			T1	1		T3	9		T33	6
valid_sources[0x60]	2431	1			T3	5		T4	2		T33	4
valid_sources[0x61]	3716	1			T3	3		T4	2		T7	2
valid_sources[0x62]	4604	1			T3	6		T4	2		T10	1
valid_sources[0x63]	2532	1			T3	8		T4	2		T33	2
valid_sources[0x64]	2848	1			T3	4		T33	1		T74	1
valid_sources[0x65]	5887	1			T3	3		T4	1		T10	4
valid_sources[0x66]	4007	1			T3	6		T7	1		T33	7
valid_sources[0x67]	4075	1			T3	4		T4	1		T7	5
valid_sources[0x68]	2508	1			T3	14		T4	1		T10	2
valid_sources[0x69]	2789	1			T3	4		T4	1		T33	2
valid_sources[0x6a]	3358	1			T2	1		T3	4		T4	1
valid_sources[0x6b]	3476	1			T1	1		T3	11		T4	1
valid_sources[0x6c]	3629	1			T2	1		T3	5		T4	1
valid_sources[0x6d]	2724	1			T1	1		T3	3		T4	1
valid_sources[0x6e]	2859	1			T1	1		T3	10		T33	3
valid_sources[0x6f]	2506	1			T3	11		T4	1		T33	6
valid_sources[0x70]	2701	1			T3	9		T4	2		T33	4
valid_sources[0x71]	2607	1			T1	2		T3	5		T4	5
valid_sources[0x72]	6358	1			T1	2		T3	13		T4	1
valid_sources[0x73]	2867	1			T3	4		T4	2		T33	7
valid_sources[0x74]	2776	1			T3	15		T4	5		T6	3
valid_sources[0x75]	10261	1			T3	7		T33	3		T73	1
valid_sources[0x76]	14890	1			T3	1		T4	1		T33	4
valid_sources[0x77]	2548	1			T3	6		T33	7		T21	38
valid_sources[0x78]	2857	1			T3	9		T4	1		T33	3
valid_sources[0x79]	5478	1			T2	3		T3	2		T33	1
valid_sources[0x7a]	2757	1			T1	1		T2	1		T3	7
valid_sources[0x7b]	3068	1			T3	2		T7	3		T33	1
valid_sources[0x7c]	2807	1			T3	5		T7	5		T33	8
valid_sources[0x7d]	3306	1			T3	3		T33	6		T74	1
valid_sources[0x7e]	2788	1			T3	11		T4	1		T33	3
valid_sources[0x7f]	2632	1			T3	6		T4	2		T7	1
valid_sources[0x80]	4216	1			T3	6		T4	1		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

207412

1

T2

20

T3

388

T4

60

values[0x0]

all_enables

biggest_size

62735

1

T1

13

T2

2

T3

65

values[0x1]

all_enables

biggest_size

34053

1

T1

5

T2

1

T3

39