SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34999 | 1 | T3 | 292 | T33 | 401 | T23 | 290 | ||||
others[1] | 34950 | 1 | T3 | 294 | T33 | 405 | T23 | 321 | ||||
others[2] | 35152 | 1 | T2 | 1 | T3 | 298 | T33 | 406 | ||||
others[3] | 58464 | 1 | T3 | 520 | T33 | 644 | T23 | 498 | ||||
false | 19477 | 1 | T2 | 1 | T3 | 50 | T5 | 452 | ||||
true | 29463 | 1 | T1 | 1 | T2 | 3 | T3 | 51 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34809 | 1 | T3 | 299 | T33 | 397 | T23 | 299 | ||||
others[1] | 35164 | 1 | T3 | 306 | T33 | 416 | T23 | 282 | ||||
others[2] | 35070 | 1 | T3 | 314 | T33 | 408 | T23 | 302 | ||||
others[3] | 58375 | 1 | T3 | 488 | T33 | 633 | T23 | 516 | ||||
false | 12340 | 1 | T2 | 2 | T3 | 50 | T5 | 226 | ||||
true | 22388 | 1 | T1 | 1 | T2 | 3 | T3 | 51 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 711 | 1 | T5 | 15 | T21 | 9 | T35 | 1 | ||||
others[1] | 718 | 1 | T2 | 1 | T5 | 20 | T21 | 8 | ||||
others[2] | 704 | 1 | T2 | 1 | T5 | 11 | T14 | 1 | ||||
others[3] | 1215 | 1 | T2 | 1 | T5 | 27 | T21 | 14 | ||||
false | 13925 | 1 | T1 | 1 | T2 | 6 | T3 | 1 | ||||
true | 4246 | 1 | T2 | 2 | T5 | 131 | T14 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |