Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	648505	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

319862

1

T1

110

T2

32

T3

31

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	623084	1			T1	241		T2	38		T3	51
values[0x0]	172234	1			T1	58		T2	59		T3	8
values[0x1]	173049	1			T1	79		T2	67		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	513492	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

454875

1

T1

170

T2

53

T3

42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3192	1			T14	88		T21	4		T20	34
valid_sources[0x01]	2803	1			T1	1		T7	20		T25	4
valid_sources[0x02]	3091	1			T7	16		T19	2		T14	66
valid_sources[0x03]	5374	1			T2	6		T7	46		T37	1
valid_sources[0x04]	3110	1			T25	1		T19	2		T14	78
valid_sources[0x05]	3876	1			T7	102		T9	23		T25	6
valid_sources[0x06]	3402	1			T6	8		T14	88		T21	13
valid_sources[0x07]	3226	1			T2	2		T37	1		T19	2
valid_sources[0x08]	3031	1			T7	4		T25	7		T19	2
valid_sources[0x09]	2943	1			T1	2		T19	3		T14	61
valid_sources[0x0a]	6859	1			T7	1		T37	1		T14	62
valid_sources[0x0b]	3730	1			T1	3		T7	36		T25	15
valid_sources[0x0c]	2981	1			T19	1		T14	72		T21	12
valid_sources[0x0d]	3060	1			T25	3		T37	2		T19	1
valid_sources[0x0e]	3254	1			T1	1		T2	3		T25	2
valid_sources[0x0f]	3243	1			T1	1		T2	2		T25	4
valid_sources[0x10]	3414	1			T7	20		T19	3		T14	72
valid_sources[0x11]	9768	1			T2	1		T19	2		T14	59
valid_sources[0x12]	3171	1			T7	78		T25	2		T37	1
valid_sources[0x13]	2984	1			T1	3		T2	2		T7	142
valid_sources[0x14]	3029	1			T2	1		T25	2		T19	4
valid_sources[0x15]	2729	1			T2	4		T14	40		T21	2
valid_sources[0x16]	2827	1			T25	4		T14	63		T21	4
valid_sources[0x17]	3133	1			T7	31		T19	2		T14	65
valid_sources[0x18]	5901	1			T2	4		T7	58		T37	1
valid_sources[0x19]	2922	1			T2	2		T25	1		T37	1
valid_sources[0x1a]	3180	1			T7	37		T37	3		T19	3
valid_sources[0x1b]	2896	1			T7	67		T25	7		T39	1
valid_sources[0x1c]	3009	1			T7	19		T25	5		T37	1
valid_sources[0x1d]	3150	1			T1	10		T7	155		T14	70
valid_sources[0x1e]	2955	1			T37	2		T19	1		T14	63
valid_sources[0x1f]	3041	1			T7	33		T14	71		T21	2
valid_sources[0x20]	3536	1			T25	2		T39	1		T14	81
valid_sources[0x21]	2930	1			T6	1		T37	2		T19	1
valid_sources[0x22]	3038	1			T2	7		T37	1		T19	7
valid_sources[0x23]	2887	1			T1	4		T25	7		T19	2
valid_sources[0x24]	3100	1			T6	17		T19	1		T14	76
valid_sources[0x25]	3064	1			T7	284		T25	2		T14	73
valid_sources[0x26]	3211	1			T7	56		T37	4		T19	1
valid_sources[0x27]	3305	1			T1	9		T7	39		T19	2
valid_sources[0x28]	3075	1			T25	5		T37	2		T19	3
valid_sources[0x29]	3058	1			T25	3		T14	67		T21	4
valid_sources[0x2a]	3380	1			T7	14		T19	4		T14	59
valid_sources[0x2b]	3323	1			T1	2		T2	1		T7	116
valid_sources[0x2c]	3081	1			T19	1		T14	58		T21	1
valid_sources[0x2d]	3179	1			T1	10		T25	3		T37	3
valid_sources[0x2e]	3524	1			T7	50		T25	2		T14	64
valid_sources[0x2f]	3036	1			T1	10		T25	3		T19	1
valid_sources[0x30]	2990	1			T7	56		T9	8		T19	2
valid_sources[0x31]	2959	1			T1	4		T7	9		T14	78
valid_sources[0x32]	3078	1			T7	27		T25	7		T37	7
valid_sources[0x33]	3383	1			T7	167		T37	2		T14	94
valid_sources[0x34]	3193	1			T2	2		T39	3		T19	4
valid_sources[0x35]	2854	1			T7	43		T9	15		T19	2
valid_sources[0x36]	5975	1			T7	14		T25	2		T37	1
valid_sources[0x37]	3387	1			T1	1		T2	1		T7	44
valid_sources[0x38]	2921	1			T1	1		T19	1		T14	85
valid_sources[0x39]	3099	1			T2	3		T25	6		T37	2
valid_sources[0x3a]	3290	1			T7	57		T14	80		T21	2
valid_sources[0x3b]	3073	1			T7	152		T39	3		T14	88
valid_sources[0x3c]	3009	1			T7	80		T25	8		T39	4
valid_sources[0x3d]	4298	1			T9	10		T39	1		T19	1
valid_sources[0x3e]	2926	1			T2	4		T7	13		T9	6
valid_sources[0x3f]	2890	1			T1	15		T25	5		T19	4
valid_sources[0x40]	2874	1			T6	1		T7	50		T37	3
valid_sources[0x41]	2837	1			T25	1		T19	2		T14	87
valid_sources[0x42]	3328	1			T1	10		T2	4		T25	1
valid_sources[0x43]	3097	1			T19	1		T14	63		T21	4
valid_sources[0x44]	2980	1			T2	2		T25	6		T37	1
valid_sources[0x45]	3880	1			T1	13		T25	1		T14	64
valid_sources[0x46]	3059	1			T1	2		T25	11		T39	1
valid_sources[0x47]	3254	1			T6	8		T7	129		T19	3
valid_sources[0x48]	3013	1			T39	3		T37	1		T19	3
valid_sources[0x49]	3154	1			T7	118		T25	8		T19	1
valid_sources[0x4a]	3374	1			T7	129		T39	1		T19	1
valid_sources[0x4b]	3682	1			T1	2		T7	61		T25	17
valid_sources[0x4c]	3019	1			T25	2		T39	2		T14	72
valid_sources[0x4d]	2960	1			T1	4		T9	14		T25	8
valid_sources[0x4e]	3026	1			T2	2		T7	106		T9	2
valid_sources[0x4f]	2822	1			T37	2		T19	2		T14	64
valid_sources[0x50]	3215	1			T37	1		T19	2		T14	57
valid_sources[0x51]	3865	1			T14	80		T21	7		T70	2
valid_sources[0x52]	3372	1			T6	1		T14	52		T21	1
valid_sources[0x53]	2867	1			T25	9		T19	6		T14	76
valid_sources[0x54]	3133	1			T6	1		T7	59		T14	59
valid_sources[0x55]	3129	1			T19	1		T14	68		T21	8
valid_sources[0x56]	3902	1			T1	6		T2	4		T9	10
valid_sources[0x57]	2981	1			T1	4		T7	28		T25	5
valid_sources[0x58]	4037	1			T14	50		T21	4		T20	30
valid_sources[0x59]	3019	1			T1	13		T2	6		T10	1
valid_sources[0x5a]	3118	1			T7	107		T37	1		T14	64
valid_sources[0x5b]	3393	1			T37	1		T19	3		T14	76
valid_sources[0x5c]	3193	1			T1	5		T7	114		T25	3
valid_sources[0x5d]	5228	1			T14	66		T21	3		T70	5
valid_sources[0x5e]	2901	1			T1	1		T19	2		T14	58
valid_sources[0x5f]	3194	1			T1	1		T2	1		T7	45
valid_sources[0x60]	3130	1			T1	4		T2	5		T7	5
valid_sources[0x61]	2798	1			T9	23		T37	1		T14	69
valid_sources[0x62]	3001	1			T7	65		T25	3		T37	1
valid_sources[0x63]	3094	1			T2	1		T6	11		T7	35
valid_sources[0x64]	3582	1			T7	88		T39	3		T14	67
valid_sources[0x65]	3150	1			T1	4		T25	7		T19	4
valid_sources[0x66]	3048	1			T25	1		T14	55		T21	8
valid_sources[0x67]	2760	1			T2	1		T7	67		T9	11
valid_sources[0x68]	3161	1			T2	1		T7	24		T25	7
valid_sources[0x69]	2816	1			T1	6		T37	1		T14	69
valid_sources[0x6a]	2907	1			T1	7		T6	1		T7	125
valid_sources[0x6b]	3304	1			T2	3		T19	2		T14	51
valid_sources[0x6c]	2943	1			T1	4		T6	3		T7	13
valid_sources[0x6d]	2957	1			T19	1		T14	87		T21	1
valid_sources[0x6e]	3214	1			T1	1		T37	1		T14	76
valid_sources[0x6f]	2498	1			T7	9		T25	3		T14	84
valid_sources[0x70]	3152	1			T25	7		T19	2		T14	69
valid_sources[0x71]	11608	1			T7	95		T9	6		T19	4
valid_sources[0x72]	10594	1			T7	34		T25	1		T39	3
valid_sources[0x73]	3489	1			T14	60		T21	5		T41	3
valid_sources[0x74]	2922	1			T14	66		T21	6		T20	29
valid_sources[0x75]	3086	1			T2	1		T7	62		T25	10
valid_sources[0x76]	5320	1			T1	3		T2	3		T7	117
valid_sources[0x77]	3170	1			T1	1		T2	5		T7	54
valid_sources[0x78]	4585	1			T14	59		T21	3		T41	1
valid_sources[0x79]	11746	1			T1	2		T7	6		T9	1
valid_sources[0x7a]	2897	1			T2	7		T37	1		T19	4
valid_sources[0x7b]	6089	1			T7	13		T9	14		T25	1
valid_sources[0x7c]	3418	1			T7	16		T37	2		T19	3
valid_sources[0x7d]	3287	1			T7	14		T37	1		T19	6
valid_sources[0x7e]	3319	1			T19	3		T14	75		T21	3
valid_sources[0x7f]	4088	1			T1	1		T7	1		T25	3
valid_sources[0x80]	3089	1			T1	2		T7	109		T25	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

220807

1

T1

80

T2

1

T3

26

values[0x0]

all_enables

biggest_size

64204

1

T1

17

T2

19

T3

3

values[0x1]

all_enables

biggest_size

34851

1

T1

13

T2

12

T3

2