SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35039 | 1 | T21 | 284 | T38 | 1 | T42 | 364 | ||||
others[1] | 35019 | 1 | T21 | 298 | T42 | 394 | T28 | 425 | ||||
others[2] | 35016 | 1 | T21 | 315 | T42 | 403 | T28 | 376 | ||||
others[3] | 58346 | 1 | T21 | 505 | T38 | 2 | T42 | 694 | ||||
false | 20041 | 1 | T1 | 30 | T7 | 50 | T25 | 8 | ||||
true | 30405 | 1 | T1 | 32 | T2 | 1 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35184 | 1 | T21 | 278 | T22 | 1 | T38 | 1 | ||||
others[1] | 35050 | 1 | T21 | 297 | T42 | 412 | T28 | 374 | ||||
others[2] | 35063 | 1 | T21 | 300 | T42 | 390 | T28 | 414 | ||||
others[3] | 58334 | 1 | T21 | 523 | T38 | 1 | T42 | 661 | ||||
false | 12623 | 1 | T1 | 15 | T7 | 25 | T25 | 4 | ||||
true | 23047 | 1 | T1 | 17 | T2 | 1 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 709 | 1 | T7 | 4 | T14 | 1 | T70 | 5 | ||||
others[1] | 746 | 1 | T7 | 10 | T9 | 1 | T14 | 3 | ||||
others[2] | 738 | 1 | T7 | 7 | T37 | 1 | T14 | 4 | ||||
others[3] | 1205 | 1 | T6 | 2 | T7 | 7 | T9 | 1 | ||||
false | 14465 | 1 | T1 | 2 | T2 | 1 | T3 | 5 | ||||
true | 4353 | 1 | T6 | 6 | T7 | 45 | T9 | 9 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |