Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26197352	14663	0	0
intr_enable_rd_A	26197352	41214	0	0
reset_en_rd_A	26197352	1690	0	0
reset_en_regwen_rd_A	26197352	1730	0	0
wake_info_capture_dis_rd_A	26197352	1560	0	0
wakeup_en_rd_A	26197352	2311	0	0
wakeup_en_regwen_rd_A	26197352	1599	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26197352	14663	0	0
T7	143845	11	0	0
T8	4131	0	0	0
T9	7541	0	0	0
T10	2169	0	0	0
T11	1428	0	0	0
T14	388827	102	0	0
T19	5792	0	0	0
T20	0	6	0	0
T25	19272	0	0	0
T37	3502	0	0	0
T38	0	79	0	0
T39	4424	0	0	0
T43	0	596	0	0
T44	0	405	0	0
T45	0	4	0	0
T49	0	258	0	0
T52	0	43	0	0
T71	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26197352	41214	0	0
T14	388827	0	0	0
T16	38764	0	0	0
T19	5792	0	0	0
T21	57107	112	0	0
T23	0	163	0	0
T28	58456	0	0	0
T32	0	41	0	0
T33	0	59	0	0
T35	0	49	0	0
T37	3502	56	0	0
T40	1900	0	0	0
T41	1883	0	0	0
T42	25721	118	0	0
T70	6461	62	0	0
T101	0	62	0	0
T102	0	59	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26197352	1690	0	0
T43	7836	4	0	0
T44	6821	25	0	0
T47	16535	111	0	0
T48	9065	0	0	0
T49	4685	8	0	0
T52	3984	16	0	0
T54	3027	34	0	0
T60	1385	0	0	0
T77	0	10	0	0
T78	0	6	0	0
T79	0	20	0	0
T103	15897	191	0	0
T104	1699	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26197352	1730	0	0
T43	7836	8	0	0
T44	6821	9	0	0
T47	16535	83	0	0
T48	9065	0	0	0
T49	4685	40	0	0
T52	3984	12	0	0
T54	3027	65	0	0
T60	1385	0	0	0
T77	0	3	0	0
T78	0	6	0	0
T79	0	32	0	0
T103	15897	211	0	0
T104	1699	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26197352	1560	0	0
T44	6821	25	0	0
T47	16535	57	0	0
T48	9065	0	0	0
T49	4685	13	0	0
T52	3984	4	0	0
T54	3027	12	0	0
T60	1385	0	0	0
T72	2401	0	0	0
T77	0	1	0	0
T78	0	7	0	0
T79	0	10	0	0
T100	0	26	0	0
T103	15897	234	0	0
T104	1699	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26197352	2311	0	0
T43	7836	15	0	0
T44	6821	8	0	0
T47	16535	228	0	0
T48	9065	0	0	0
T49	4685	11	0	0
T52	3984	6	0	0
T54	3027	36	0	0
T60	1385	0	0	0
T77	0	7	0	0
T78	0	25	0	0
T79	0	46	0	0
T103	15897	210	0	0
T104	1699	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26197352	1599	0	0
T43	7836	10	0	0
T44	6821	16	0	0
T47	16535	89	0	0
T48	9065	0	0	0
T49	4685	16	0	0
T52	3984	4	0	0
T54	3027	39	0	0
T60	1385	0	0	0
T77	0	5	0	0
T78	0	13	0	0
T79	0	2	0	0
T103	15897	205	0	0
T104	1699	0	0	0