Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	25590040	56699	0	0
IoStatusRise_A	25590040	63097	0	0
MainStatusFall_A	25590040	56699	0	0
MainStatusRise_A	25590040	63098	0	0
UsbStatusFall_A	25590040	43942	0	0
UsbStatusRise_A	25590040	49208	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	56699	0	0
T1	6102	26	0	0
T2	1222	18	0	0
T3	3253	4	0	0
T4	11729	12	0	0
T5	2583	0	0	0
T6	5447	18	0	0
T7	143845	475	0	0
T8	4131	0	0	0
T9	7541	22	0	0
T10	2169	0	0	0
T11	0	1	0	0
T25	0	44	0	0
T39	0	3	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	63097	0	0
T1	6102	28	0	0
T2	1222	19	0	0
T3	3253	5	0	0
T4	11729	13	0	0
T5	2583	3	0	0
T6	5447	19	0	0
T7	143845	540	0	0
T8	4131	6	0	0
T9	7541	24	0	0
T10	2169	3	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	56699	0	0
T1	6102	26	0	0
T2	1222	18	0	0
T3	3253	4	0	0
T4	11729	12	0	0
T5	2583	0	0	0
T6	5447	18	0	0
T7	143845	475	0	0
T8	4131	0	0	0
T9	7541	22	0	0
T10	2169	0	0	0
T11	0	1	0	0
T25	0	44	0	0
T39	0	3	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	63098	0	0
T1	6102	28	0	0
T2	1222	19	0	0
T3	3253	5	0	0
T4	11729	13	0	0
T5	2583	3	0	0
T6	5447	19	0	0
T7	143845	540	0	0
T8	4131	6	0	0
T9	7541	24	0	0
T10	2169	3	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	43942	0	0
T1	6102	18	0	0
T2	1222	18	0	0
T3	3253	4	0	0
T4	11729	6	0	0
T5	2583	0	0	0
T6	5447	18	0	0
T7	143845	406	0	0
T8	4131	0	0	0
T9	7541	22	0	0
T10	2169	0	0	0
T11	0	1	0	0
T25	0	37	0	0
T39	0	2	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	49208	0	0
T1	6102	19	0	0
T2	1222	19	0	0
T3	3253	5	0	0
T4	11729	7	0	0
T5	2583	3	0	0
T6	5447	19	0	0
T7	143845	458	0	0
T8	4131	6	0	0
T9	7541	24	0	0
T10	2169	3	0	0