Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	25590040	62721	0	0
RomAllowCheckGoodState_A	25590040	62776	0	0
RomBlockActiveState_A	25590040	29914	0	0
RomBlockCheckGoodState_A	25590040	434768	0	0
RomIntgChkDisFalse_A	25590040	24919760	0	0
RomIntgChkDisTrue_A	25590040	122008	0	0
RstreqChkEsctimeout_A	25590040	4573	0	0
RstreqChkFsmterm_A	25590040	180	0	0
RstreqChkGlbesc_A	25590040	4576	0	0
RstreqChkMainpd_A	25590040	1051072	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	62721	0	0
T1	6102	28	0	0
T2	1222	19	0	0
T3	3253	5	0	0
T4	11729	13	0	0
T5	2583	3	0	0
T6	5447	12	0	0
T7	143845	540	0	0
T8	4131	6	0	0
T9	7541	24	0	0
T10	2169	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	62776	0	0
T1	6102	28	0	0
T2	1222	19	0	0
T3	3253	5	0	0
T4	11729	13	0	0
T5	2583	3	0	0
T6	5447	13	0	0
T7	143845	540	0	0
T8	4131	6	0	0
T9	7541	24	0	0
T10	2169	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	29914	0	0
T15	1562	0	0	0
T16	38764	0	0	0
T20	184666	0	0	0
T22	4586	619	0	0
T24	0	1189	0	0
T38	456618	0	0	0
T42	25721	8	0	0
T50	1464	0	0	0
T69	5031	0	0	0
T105	0	578	0	0
T106	0	266	0	0
T107	0	228	0	0
T108	0	2	0	0
T109	0	1023	0	0
T110	0	931	0	0
T111	0	1070	0	0
T112	2858	0	0	0
T113	1601	0	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	434768	0	0
T1	6102	344	0	0
T2	1222	0	0	0
T3	3253	0	0	0
T4	11729	0	0	0
T5	2583	0	0	0
T6	5447	0	0	0
T7	143845	574	0	0
T8	4131	0	0	0
T9	7541	0	0	0
T10	2169	0	0	0
T14	0	3419	0	0
T19	0	344	0	0
T20	0	2134	0	0
T21	0	4008	0	0
T22	0	1006	0	0
T25	0	92	0	0
T38	0	2440	0	0
T42	0	1308	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	24919760	0	0
T1	6102	5956	0	0
T2	1222	1142	0	0
T3	3253	2905	0	0
T4	11729	11635	0	0
T5	2583	2392	0	0
T6	5447	4666	0	0
T7	143845	139089	0	0
T8	4131	3739	0	0
T9	7541	7395	0	0
T10	2169	1899	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	122008	0	0
T13	1551	0	0	0
T21	57107	3068	0	0
T23	38974	927	0	0
T24	0	795	0	0
T40	1900	0	0	0
T41	1883	0	0	0
T70	6461	0	0	0
T105	0	318	0	0
T106	0	86	0	0
T107	0	920	0	0
T108	0	66	0	0
T109	0	187	0	0
T110	0	118	0	0
T114	0	2630	0	0
T115	1560	0	0	0
T116	2150	0	0	0
T117	2523	0	0	0
T118	6960	0	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	4573	0	0
T6	5447	3	0	0
T7	143845	52	0	0
T8	4131	0	0	0
T9	7541	6	0	0
T10	2169	2	0	0
T11	1428	1	0	0
T14	0	48	0	0
T19	5792	0	0	0
T20	0	34	0	0
T22	0	3	0	0
T25	19272	0	0	0
T37	3502	6	0	0
T38	0	94	0	0
T39	4424	0	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	180	0	0
T16	38764	40	0	0
T17	0	40	0	0
T18	0	40	0	0
T26	0	20	0	0
T27	0	40	0	0
T28	58456	0	0	0
T29	6515	0	0	0
T30	3465	0	0	0
T31	5494	0	0	0
T32	13912	0	0	0
T33	2725	0	0	0
T34	3380	0	0	0
T35	4899	0	0	0
T36	1362	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	4576	0	0
T6	5447	3	0	0
T7	143845	52	0	0
T8	4131	0	0	0
T9	7541	6	0	0
T10	2169	2	0	0
T11	1428	1	0	0
T14	0	48	0	0
T19	5792	0	0	0
T20	0	34	0	0
T22	0	3	0	0
T25	19272	0	0	0
T37	3502	6	0	0
T38	0	94	0	0
T39	4424	0	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25590040	1051072	0	0
T1	6102	928	0	0
T2	1222	0	0	0
T3	3253	0	0	0
T4	11729	0	0	0
T5	2583	6	0	0
T6	5447	65	0	0
T7	143845	1643	0	0
T8	4131	22	0	0
T9	7541	800	0	0
T10	2169	0	0	0
T14	0	18255	0	0
T19	0	364	0	0
T25	0	103	0	0
T37	0	85	0	0