Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	591120	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

288280

1

T1

20

T2

120

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	559099	1			T1	31		T2	205		T3	22
values[0x0]	159689	1			T1	17		T2	80		T3	8
values[0x1]	160612	1			T1	16		T2	66		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	468802	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

410598

1

T1

29

T2

161

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3596	1			T1	1		T6	7		T10	4
valid_sources[0x01]	3019	1			T5	6		T6	7		T10	1
valid_sources[0x02]	2694	1			T5	1		T10	4		T40	3
valid_sources[0x03]	3491	1			T6	17		T10	1		T75	1
valid_sources[0x04]	4073	1			T1	1		T6	16		T10	4
valid_sources[0x05]	3048	1			T5	2		T6	6		T10	2
valid_sources[0x06]	2732	1			T5	1		T6	12		T10	1
valid_sources[0x07]	3026	1			T5	3		T6	3		T40	3
valid_sources[0x08]	2640	1			T5	2		T10	2		T42	2
valid_sources[0x09]	2848	1			T6	15		T10	2		T40	2
valid_sources[0x0a]	2986	1			T6	17		T10	5		T40	2
valid_sources[0x0b]	2791	1			T6	4		T10	2		T40	3
valid_sources[0x0c]	2722	1			T10	5		T40	1		T42	1
valid_sources[0x0d]	2904	1			T1	1		T10	6		T40	2
valid_sources[0x0e]	17271	1			T3	1		T6	5		T10	2
valid_sources[0x0f]	2593	1			T6	1		T10	1		T40	1
valid_sources[0x10]	2817	1			T3	1		T6	2		T10	3
valid_sources[0x11]	2525	1			T6	8		T10	2		T62	1
valid_sources[0x12]	2894	1			T5	1		T6	4		T10	4
valid_sources[0x13]	2877	1			T5	1		T6	1		T10	3
valid_sources[0x14]	3727	1			T10	4		T23	1		T40	1
valid_sources[0x15]	2502	1			T6	5		T10	3		T23	1
valid_sources[0x16]	2776	1			T6	1		T10	3		T40	1
valid_sources[0x17]	2869	1			T6	2		T10	2		T23	1
valid_sources[0x18]	3954	1			T6	7		T10	3		T23	2
valid_sources[0x19]	2593	1			T10	6		T23	2		T40	3
valid_sources[0x1a]	4925	1			T3	1		T5	3		T6	2
valid_sources[0x1b]	2842	1			T3	1		T10	3		T23	3
valid_sources[0x1c]	2901	1			T5	1		T6	5		T40	2
valid_sources[0x1d]	2795	1			T6	4		T10	2		T40	1
valid_sources[0x1e]	8260	1			T6	17		T10	4		T42	1
valid_sources[0x1f]	2939	1			T6	3		T10	2		T62	4
valid_sources[0x20]	2851	1			T10	1		T40	2		T62	4
valid_sources[0x21]	6279	1			T5	2		T6	3		T10	4
valid_sources[0x22]	2882	1			T5	1		T6	4		T22	26
valid_sources[0x23]	4745	1			T6	4		T10	4		T23	2
valid_sources[0x24]	2828	1			T6	6		T10	4		T42	4
valid_sources[0x25]	3049	1			T6	12		T10	2		T40	7
valid_sources[0x26]	2925	1			T6	5		T10	7		T23	1
valid_sources[0x27]	2613	1			T6	11		T10	4		T23	3
valid_sources[0x28]	2763	1			T6	11		T10	5		T40	1
valid_sources[0x29]	2541	1			T1	3		T3	1		T10	3
valid_sources[0x2a]	2850	1			T6	7		T10	3		T40	2
valid_sources[0x2b]	2646	1			T5	1		T10	5		T40	1
valid_sources[0x2c]	3584	1			T6	3		T10	1		T42	1
valid_sources[0x2d]	2900	1			T5	5		T6	1		T10	1
valid_sources[0x2e]	7369	1			T5	11		T6	4		T10	3
valid_sources[0x2f]	2948	1			T3	1		T6	9		T10	4
valid_sources[0x30]	2710	1			T5	2		T6	2		T10	2
valid_sources[0x31]	24213	1			T5	3		T6	8		T10	5
valid_sources[0x32]	2831	1			T3	2		T6	3		T10	1
valid_sources[0x33]	5438	1			T2	351		T5	4		T6	3
valid_sources[0x34]	3219	1			T5	3		T6	3		T10	1
valid_sources[0x35]	2706	1			T6	8		T10	3		T23	1
valid_sources[0x36]	2960	1			T5	2		T6	2		T10	2
valid_sources[0x37]	18105	1			T1	4		T5	2		T6	6
valid_sources[0x38]	2829	1			T3	2		T6	5		T10	3
valid_sources[0x39]	3876	1			T5	1		T6	4		T10	1
valid_sources[0x3a]	3970	1			T5	10		T6	4		T10	2
valid_sources[0x3b]	2681	1			T5	1		T6	10		T10	6
valid_sources[0x3c]	2795	1			T3	1		T6	5		T10	1
valid_sources[0x3d]	2817	1			T1	4		T6	6		T10	2
valid_sources[0x3e]	3633	1			T5	1		T6	4		T10	2
valid_sources[0x3f]	2837	1			T6	1		T10	4		T40	2
valid_sources[0x40]	2784	1			T6	3		T10	2		T23	1
valid_sources[0x41]	2699	1			T10	2		T42	1		T62	3
valid_sources[0x42]	2879	1			T3	1		T5	4		T6	3
valid_sources[0x43]	3155	1			T5	6		T6	12		T10	4
valid_sources[0x44]	2769	1			T10	2		T40	7		T42	2
valid_sources[0x45]	3028	1			T6	4		T10	2		T23	2
valid_sources[0x46]	2651	1			T6	4		T10	1		T40	1
valid_sources[0x47]	3065	1			T5	1		T6	7		T10	1
valid_sources[0x48]	2657	1			T5	1		T6	4		T23	3
valid_sources[0x49]	2835	1			T6	3		T10	1		T40	2
valid_sources[0x4a]	2742	1			T6	5		T10	2		T40	1
valid_sources[0x4b]	2750	1			T3	2		T5	4		T10	3
valid_sources[0x4c]	2932	1			T6	3		T10	1		T40	2
valid_sources[0x4d]	4469	1			T5	14		T6	13		T10	3
valid_sources[0x4e]	2907	1			T3	1		T6	2		T10	3
valid_sources[0x4f]	2995	1			T6	8		T40	1		T42	1
valid_sources[0x50]	2590	1			T5	1		T6	9		T10	4
valid_sources[0x51]	3118	1			T5	4		T6	14		T10	1
valid_sources[0x52]	3128	1			T3	1		T6	16		T10	2
valid_sources[0x53]	2755	1			T6	6		T23	2		T75	5
valid_sources[0x54]	2639	1			T6	2		T10	1		T23	1
valid_sources[0x55]	2852	1			T6	8		T10	3		T23	1
valid_sources[0x56]	2854	1			T5	4		T6	1		T10	3
valid_sources[0x57]	2890	1			T3	1		T6	11		T10	3
valid_sources[0x58]	2817	1			T6	4		T10	3		T23	1
valid_sources[0x59]	3113	1			T5	1		T6	7		T10	2
valid_sources[0x5a]	2832	1			T5	9		T6	8		T10	2
valid_sources[0x5b]	2914	1			T6	1		T10	2		T40	1
valid_sources[0x5c]	2818	1			T5	3		T6	1		T10	1
valid_sources[0x5d]	3062	1			T6	3		T10	2		T40	3
valid_sources[0x5e]	2884	1			T6	3		T10	5		T40	2
valid_sources[0x5f]	2688	1			T5	2		T40	2		T42	1
valid_sources[0x60]	2702	1			T6	2		T10	2		T40	1
valid_sources[0x61]	2825	1			T6	2		T10	2		T40	1
valid_sources[0x62]	2933	1			T5	2		T6	17		T10	1
valid_sources[0x63]	4826	1			T6	2		T10	4		T23	1
valid_sources[0x64]	3155	1			T6	7		T10	2		T45	1
valid_sources[0x65]	2783	1			T10	2		T23	1		T42	2
valid_sources[0x66]	2640	1			T5	7		T6	16		T10	1
valid_sources[0x67]	3158	1			T6	1		T10	1		T60	285
valid_sources[0x68]	2583	1			T5	4		T6	1		T10	2
valid_sources[0x69]	2966	1			T3	1		T5	10		T6	4
valid_sources[0x6a]	2717	1			T3	1		T5	2		T6	5
valid_sources[0x6b]	2715	1			T23	1		T42	2		T26	8
valid_sources[0x6c]	2897	1			T6	11		T10	5		T23	3
valid_sources[0x6d]	3283	1			T5	8		T6	5		T10	3
valid_sources[0x6e]	4299	1			T5	1		T6	5		T10	3
valid_sources[0x6f]	2633	1			T5	3		T6	8		T23	2
valid_sources[0x70]	2952	1			T5	4		T6	15		T10	1
valid_sources[0x71]	2920	1			T1	4		T3	1		T5	1
valid_sources[0x72]	2596	1			T3	1		T6	2		T10	1
valid_sources[0x73]	2633	1			T5	1		T6	11		T23	1
valid_sources[0x74]	3105	1			T6	12		T10	1		T23	2
valid_sources[0x75]	2709	1			T6	8		T40	5		T42	2
valid_sources[0x76]	2966	1			T6	3		T10	1		T40	1
valid_sources[0x77]	3824	1			T6	2		T10	4		T23	1
valid_sources[0x78]	2599	1			T6	5		T10	2		T40	1
valid_sources[0x79]	5177	1			T6	1		T10	2		T40	2
valid_sources[0x7a]	2806	1			T3	1		T6	10		T10	4
valid_sources[0x7b]	2819	1			T5	2		T6	19		T10	1
valid_sources[0x7c]	3295	1			T6	8		T10	3		T40	2
valid_sources[0x7d]	2575	1			T3	1		T5	4		T6	7
valid_sources[0x7e]	2758	1			T1	1		T6	3		T10	1
valid_sources[0x7f]	12055	1			T5	2		T6	1		T10	2
valid_sources[0x80]	2693	1			T5	1		T6	5		T10	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

196623

1

T1

12

T2

81

T3

11

values[0x0]

all_enables

biggest_size

59500

1

T1

4

T2

24

T3

4

values[0x1]

all_enables

biggest_size

32157

1

T1

4

T2

15

T3

2