SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35017 | 1 | T6 | 408 | T7 | 405 | T41 | 402 | ||||
others[1] | 35112 | 1 | T6 | 406 | T7 | 407 | T41 | 388 | ||||
others[2] | 35116 | 1 | T6 | 403 | T7 | 408 | T23 | 1 | ||||
others[3] | 58098 | 1 | T6 | 646 | T7 | 662 | T41 | 643 | ||||
false | 18725 | 1 | T5 | 30 | T6 | 50 | T7 | 50 | ||||
true | 28445 | 1 | T1 | 12 | T2 | 1 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35301 | 1 | T6 | 376 | T7 | 410 | T23 | 1 | ||||
others[1] | 34828 | 1 | T6 | 421 | T7 | 384 | T41 | 397 | ||||
others[2] | 34887 | 1 | T6 | 397 | T7 | 386 | T23 | 1 | ||||
others[3] | 58544 | 1 | T6 | 679 | T7 | 696 | T41 | 683 | ||||
false | 11954 | 1 | T5 | 15 | T6 | 50 | T7 | 50 | ||||
true | 21739 | 1 | T1 | 12 | T2 | 1 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 631 | 1 | T4 | 1 | T40 | 1 | T122 | 5 | ||||
others[1] | 729 | 1 | T4 | 2 | T40 | 1 | T122 | 6 | ||||
others[2] | 610 | 1 | T1 | 1 | T122 | 6 | T14 | 9 | ||||
others[3] | 1103 | 1 | T10 | 1 | T23 | 1 | T40 | 2 | ||||
false | 13004 | 1 | T1 | 19 | T2 | 1 | T3 | 5 | ||||
true | 3832 | 1 | T1 | 6 | T4 | 4 | T10 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |