Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T22

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	22716859	6130	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	22716859	251975	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	22716859	9681939	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	22716859	251946	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	22716859	6130	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	22716859	251975	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	22716859	9681939	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	22716859	251946	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	6130	0	0
T3	1532	1	0	0
T4	3205	0	0	0
T5	6180	4	0	0
T6	25760	21	0	0
T7	60274	26	0	0
T8	13521	0	0	0
T9	4889	0	0	0
T10	27270	1	0	0
T22	1809	2	0	0
T23	2851	0	0	0
T26	0	20	0	0
T41	0	15	0	0
T42	0	6	0	0
T74	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	251975	0	0
T3	1532	83	0	0
T4	3205	0	0	0
T5	6180	86	0	0
T6	25760	605	0	0
T7	60274	1857	0	0
T8	13521	0	0	0
T9	4889	0	0	0
T10	27270	10	0	0
T22	1809	166	0	0
T23	2851	0	0	0
T26	0	500	0	0
T41	0	407	0	0
T42	0	203	0	0
T74	0	10	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	9681939	0	0
T2	19142	10516	0	0
T3	1532	43	0	0
T4	3205	0	0	0
T5	6180	1923	0	0
T6	25760	11036	0	0
T7	60274	35680	0	0
T8	13521	8788	0	0
T9	4889	1903	0	0
T10	27270	7543	0	0
T22	1809	926	0	0
T41	0	11752	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	251946	0	0
T3	1532	83	0	0
T4	3205	0	0	0
T5	6180	86	0	0
T6	25760	605	0	0
T7	60274	1857	0	0
T8	13521	0	0	0
T9	4889	0	0	0
T10	27270	10	0	0
T22	1809	166	0	0
T23	2851	0	0	0
T26	0	500	0	0
T41	0	407	0	0
T42	0	203	0	0
T74	0	10	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	6130	0	0
T3	1532	1	0	0
T4	3205	0	0	0
T5	6180	4	0	0
T6	25760	21	0	0
T7	60274	26	0	0
T8	13521	0	0	0
T9	4889	0	0	0
T10	27270	1	0	0
T22	1809	2	0	0
T23	2851	0	0	0
T26	0	20	0	0
T41	0	15	0	0
T42	0	6	0	0
T74	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	251975	0	0
T3	1532	83	0	0
T4	3205	0	0	0
T5	6180	86	0	0
T6	25760	605	0	0
T7	60274	1857	0	0
T8	13521	0	0	0
T9	4889	0	0	0
T10	27270	10	0	0
T22	1809	166	0	0
T23	2851	0	0	0
T26	0	500	0	0
T41	0	407	0	0
T42	0	203	0	0
T74	0	10	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	9681939	0	0
T2	19142	10516	0	0
T3	1532	43	0	0
T4	3205	0	0	0
T5	6180	1923	0	0
T6	25760	11036	0	0
T7	60274	35680	0	0
T8	13521	8788	0	0
T9	4889	1903	0	0
T10	27270	7543	0	0
T22	1809	926	0	0
T41	0	11752	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	251946	0	0
T3	1532	83	0	0
T4	3205	0	0	0
T5	6180	86	0	0
T6	25760	605	0	0
T7	60274	1857	0	0
T8	13521	0	0	0
T9	4889	0	0	0
T10	27270	10	0	0
T22	1809	166	0	0
T23	2851	0	0	0
T26	0	500	0	0
T41	0	407	0	0
T42	0	203	0	0
T74	0	10	0	0