Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23289021	13566	0	0
intr_enable_rd_A	23289021	35902	0	0
reset_en_rd_A	23289021	1559	0	0
reset_en_regwen_rd_A	23289021	1213	0	0
wake_info_capture_dis_rd_A	23289021	1256	0	0
wakeup_en_rd_A	23289021	1611	0	0
wakeup_en_regwen_rd_A	23289021	1253	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23289021	13566	0	0
T14	675539	80	0	0
T24	452272	45	0	0
T25	0	8	0	0
T47	2470	0	0	0
T49	3192	0	0	0
T52	0	9	0	0
T53	0	765	0	0
T54	0	4	0	0
T55	0	19	0	0
T56	0	5	0	0
T68	0	83	0	0
T76	2033	0	0	0
T77	66806	0	0	0
T78	1722	0	0	0
T79	37138	0	0	0
T82	0	18	0	0
T120	1300	0	0	0
T121	3734	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23289021	35902	0	0
T2	19142	56	0	0
T3	1532	0	0	0
T4	3205	0	0	0
T5	6180	0	0	0
T6	25760	0	0	0
T7	60274	176	0	0
T8	13521	0	0	0
T9	4889	0	0	0
T10	27270	181	0	0
T22	1809	0	0	0
T77	0	151	0	0
T81	0	88	0	0
T122	0	60	0	0
T123	0	131	0	0
T124	0	83	0	0
T125	0	105	0	0
T126	0	4	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23289021	1559	0	0
T18	1215	0	0	0
T25	237039	13	0	0
T53	0	56	0	0
T55	249268	22	0	0
T56	0	7	0	0
T57	0	38	0	0
T58	0	20	0	0
T63	0	7	0	0
T82	509753	9	0	0
T85	0	460	0	0
T127	0	5	0	0
T128	1485	0	0	0
T129	3018	0	0	0
T130	25509	0	0	0
T131	4328	0	0	0
T132	733	0	0	0
T133	1605	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23289021	1213	0	0
T18	1215	0	0	0
T25	237039	3	0	0
T53	0	24	0	0
T55	249268	7	0	0
T56	0	16	0	0
T57	0	34	0	0
T58	0	14	0	0
T63	0	3	0	0
T82	509753	17	0	0
T85	0	444	0	0
T127	0	11	0	0
T128	1485	0	0	0
T129	3018	0	0	0
T130	25509	0	0	0
T131	4328	0	0	0
T132	733	0	0	0
T133	1605	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23289021	1256	0	0
T18	1215	0	0	0
T25	237039	12	0	0
T53	0	49	0	0
T55	249268	11	0	0
T56	0	1	0	0
T57	0	6	0	0
T58	0	22	0	0
T63	0	14	0	0
T82	509753	30	0	0
T85	0	349	0	0
T127	0	10	0	0
T128	1485	0	0	0
T129	3018	0	0	0
T130	25509	0	0	0
T131	4328	0	0	0
T132	733	0	0	0
T133	1605	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23289021	1611	0	0
T18	1215	0	0	0
T25	237039	10	0	0
T53	0	25	0	0
T55	249268	5	0	0
T56	0	6	0	0
T57	0	57	0	0
T58	0	15	0	0
T63	0	13	0	0
T82	509753	16	0	0
T85	0	410	0	0
T127	0	26	0	0
T128	1485	0	0	0
T129	3018	0	0	0
T130	25509	0	0	0
T131	4328	0	0	0
T132	733	0	0	0
T133	1605	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23289021	1253	0	0
T18	1215	0	0	0
T25	237039	3	0	0
T53	0	23	0	0
T55	249268	8	0	0
T56	0	8	0	0
T57	0	19	0	0
T63	0	15	0	0
T82	509753	13	0	0
T85	0	425	0	0
T116	0	9	0	0
T127	0	7	0	0
T128	1485	0	0	0
T129	3018	0	0	0
T130	25509	0	0	0
T131	4328	0	0	0
T132	733	0	0	0
T133	1605	0	0	0