Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	22716859	51838	0	0
IoStatusRise_A	22716859	57703	0	0
MainStatusFall_A	22716859	51839	0	0
MainStatusRise_A	22716859	57703	0	0
UsbStatusFall_A	22716859	39954	0	0
UsbStatusRise_A	22716859	44784	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	51838	0	0
T1	2967	18	0	0
T2	19142	20	0	0
T3	1532	4	0	0
T4	3205	18	0	0
T5	6180	23	0	0
T6	25760	90	0	0
T7	60274	91	0	0
T8	13521	17	0	0
T9	4889	17	0	0
T10	27270	50	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	57703	0	0
T1	2967	19	0	0
T2	19142	21	0	0
T3	1532	5	0	0
T4	3205	19	0	0
T5	6180	24	0	0
T6	25760	91	0	0
T7	60274	93	0	0
T8	13521	18	0	0
T9	4889	18	0	0
T10	27270	58	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	51839	0	0
T1	2967	18	0	0
T2	19142	20	0	0
T3	1532	4	0	0
T4	3205	18	0	0
T5	6180	23	0	0
T6	25760	90	0	0
T7	60274	91	0	0
T8	13521	17	0	0
T9	4889	17	0	0
T10	27270	50	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	57703	0	0
T1	2967	19	0	0
T2	19142	21	0	0
T3	1532	5	0	0
T4	3205	19	0	0
T5	6180	24	0	0
T6	25760	91	0	0
T7	60274	93	0	0
T8	13521	18	0	0
T9	4889	18	0	0
T10	27270	58	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	39954	0	0
T1	2967	18	0	0
T2	19142	16	0	0
T3	1532	4	0	0
T4	3205	18	0	0
T5	6180	18	0	0
T6	25760	64	0	0
T7	60274	53	0	0
T8	13521	9	0	0
T9	4889	13	0	0
T10	27270	46	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	44784	0	0
T1	2967	19	0	0
T2	19142	17	0	0
T3	1532	5	0	0
T4	3205	19	0	0
T5	6180	19	0	0
T6	25760	64	0	0
T7	60274	54	0	0
T8	13521	9	0	0
T9	4889	13	0	0
T10	27270	53	0	0