Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	22716859	57305	0	0
RomAllowCheckGoodState_A	22716859	57354	0	0
RomBlockActiveState_A	22716859	26483	0	0
RomBlockCheckGoodState_A	22716859	410323	0	0
RomIntgChkDisFalse_A	22716859	22111474	0	0
RomIntgChkDisTrue_A	22716859	102378	0	0
RstreqChkEsctimeout_A	22716859	4016	0	0
RstreqChkFsmterm_A	22716859	120	0	0
RstreqChkGlbesc_A	22716859	4019	0	0
RstreqChkMainpd_A	22716859	936169	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	57305	0	0
T1	2967	12	0	0
T2	19142	21	0	0
T3	1532	5	0	0
T4	3205	12	0	0
T5	6180	24	0	0
T6	25760	91	0	0
T7	60274	93	0	0
T8	13521	18	0	0
T9	4889	18	0	0
T10	27270	58	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	57354	0	0
T1	2967	13	0	0
T2	19142	21	0	0
T3	1532	5	0	0
T4	3205	13	0	0
T5	6180	24	0	0
T6	25760	91	0	0
T7	60274	93	0	0
T8	13521	18	0	0
T9	4889	18	0	0
T10	27270	58	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	26483	0	0
T11	2520	0	0	0
T12	1429	0	0	0
T13	1230	0	0	0
T23	2851	512	0	0
T28	2741	371	0	0
T40	8539	0	0	0
T41	34946	0	0	0
T45	1454	0	0	0
T51	0	41	0	0
T60	5642	0	0	0
T75	14070	0	0	0
T76	0	342	0	0
T134	0	224	0	0
T135	0	7	0	0
T136	0	440	0	0
T137	0	257	0	0
T138	0	232	0	0
T139	0	8	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	410323	0	0
T5	6180	344	0	0
T6	25760	1765	0	0
T7	60274	4022	0	0
T8	13521	0	0	0
T9	4889	0	0	0
T10	27270	0	0	0
T11	2520	0	0	0
T14	0	4060	0	0
T22	1809	0	0	0
T23	2851	209	0	0
T26	0	1313	0	0
T27	0	4033	0	0
T28	0	238	0	0
T40	8539	0	0	0
T41	0	2273	0	0
T42	0	276	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	22111474	0	0
T1	2967	2053	0	0
T2	19142	19049	0	0
T3	1532	1136	0	0
T4	3205	2272	0	0
T5	6180	6086	0	0
T6	25760	25684	0	0
T7	60274	60119	0	0
T8	13521	13453	0	0
T9	4889	4794	0	0
T10	27270	26653	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	102378	0	0
T11	2520	0	0	0
T12	1429	0	0	0
T13	1230	0	0	0
T23	2851	1045	0	0
T26	21764	145	0	0
T27	0	1455	0	0
T28	0	1091	0	0
T40	8539	0	0	0
T41	34946	0	0	0
T45	1454	0	0	0
T60	5642	0	0	0
T75	14070	0	0	0
T76	0	697	0	0
T79	0	1734	0	0
T134	0	466	0	0
T140	0	1349	0	0
T141	0	4018	0	0
T142	0	1037	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	4016	0	0
T1	2967	3	0	0
T2	19142	0	0	0
T3	1532	0	0	0
T4	3205	5	0	0
T5	6180	0	0	0
T6	25760	0	0	0
T7	60274	0	0	0
T8	13521	0	0	0
T9	4889	0	0	0
T10	27270	5	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T23	0	1	0	0
T40	0	12	0	0
T43	0	1	0	0
T45	0	5	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	120	0	0
T19	8430	20	0	0
T20	0	20	0	0
T21	0	40	0	0
T29	0	20	0	0
T30	0	20	0	0
T31	11374	0	0	0
T32	2293	0	0	0
T33	1115	0	0	0
T34	3952	0	0	0
T35	574513	0	0	0
T36	37991	0	0	0
T37	7206	0	0	0
T38	16456	0	0	0
T39	6344	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	4019	0	0
T1	2967	3	0	0
T2	19142	0	0	0
T3	1532	0	0	0
T4	3205	5	0	0
T5	6180	0	0	0
T6	25760	0	0	0
T7	60274	0	0	0
T8	13521	0	0	0
T9	4889	0	0	0
T10	27270	5	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T23	0	1	0	0
T40	0	12	0	0
T43	0	1	0	0
T45	0	5	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22716859	936169	0	0
T1	2967	111	0	0
T2	19142	0	0	0
T3	1532	0	0	0
T4	3205	130	0	0
T5	6180	465	0	0
T6	25760	2345	0	0
T7	60274	7201	0	0
T8	13521	0	0	0
T9	4889	0	0	0
T10	27270	343	0	0
T23	0	90	0	0
T40	0	735	0	0
T41	0	1197	0	0
T42	0	792	0	0