Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	425869	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

211968

1

T1

26

T2

25

T3

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	407572	1			T1	65		T2	182		T3	64
values[0x0]	114576	1			T1	13		T2	33		T3	7
values[0x1]	115689	1			T1	9		T2	29		T3	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	337295	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

300542

1

T1

41

T2

91

T3

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1960	1			T6	2		T7	1		T44	2
valid_sources[0x01]	2153	1			T8	1		T14	3		T41	1
valid_sources[0x02]	1978	1			T3	1		T7	1		T14	4
valid_sources[0x03]	8056	1			T6	3		T10	1		T14	1
valid_sources[0x04]	2297	1			T8	1		T43	1		T45	1
valid_sources[0x05]	2299	1			T3	1		T6	2		T8	2
valid_sources[0x06]	2066	1			T6	1		T10	1		T41	1
valid_sources[0x07]	2006	1			T2	1		T6	1		T7	3
valid_sources[0x08]	2273	1			T3	1		T6	1		T8	1
valid_sources[0x09]	2014	1			T1	1		T2	2		T78	9
valid_sources[0x0a]	1982	1			T6	4		T14	6		T57	1
valid_sources[0x0b]	2075	1			T2	2		T6	1		T7	2
valid_sources[0x0c]	2121	1			T1	2		T2	1		T3	1
valid_sources[0x0d]	1888	1			T6	3		T61	1		T47	7
valid_sources[0x0e]	3033	1			T6	1		T7	3		T9	2
valid_sources[0x0f]	1814	1			T14	1		T41	1		T57	1
valid_sources[0x10]	2175	1			T57	1		T45	2		T46	2
valid_sources[0x11]	2003	1			T3	1		T6	1		T7	1
valid_sources[0x12]	1947	1			T6	2		T7	2		T9	5
valid_sources[0x13]	2069	1			T2	1		T6	1		T9	5
valid_sources[0x14]	3012	1			T3	1		T6	1		T8	2
valid_sources[0x15]	2056	1			T2	2		T7	1		T10	1
valid_sources[0x16]	1807	1			T3	1		T8	1		T14	2
valid_sources[0x17]	2029	1			T2	1		T6	3		T41	3
valid_sources[0x18]	2065	1			T14	1		T41	1		T57	1
valid_sources[0x19]	2171	1			T2	1		T14	2		T16	1
valid_sources[0x1a]	2535	1			T8	1		T14	2		T42	18
valid_sources[0x1b]	1863	1			T7	1		T14	4		T41	1
valid_sources[0x1c]	2804	1			T2	9		T6	2		T9	8
valid_sources[0x1d]	2122	1			T2	3		T6	1		T8	1
valid_sources[0x1e]	4288	1			T2	1		T3	1		T10	2
valid_sources[0x1f]	2071	1			T3	1		T6	1		T8	1
valid_sources[0x20]	6784	1			T3	1		T6	1		T14	3
valid_sources[0x21]	2148	1			T6	1		T7	1		T14	3
valid_sources[0x22]	2198	1			T2	5		T4	244		T6	4
valid_sources[0x23]	2019	1			T2	1		T6	2		T7	1
valid_sources[0x24]	2003	1			T6	1		T14	3		T41	1
valid_sources[0x25]	2462	1			T7	1		T8	1		T10	2
valid_sources[0x26]	1924	1			T6	2		T7	2		T10	1
valid_sources[0x27]	2038	1			T3	2		T14	2		T41	4
valid_sources[0x28]	3217	1			T2	2		T7	1		T14	2
valid_sources[0x29]	2091	1			T6	1		T14	5		T41	2
valid_sources[0x2a]	2135	1			T6	1		T14	4		T41	1
valid_sources[0x2b]	2050	1			T8	1		T10	1		T14	4
valid_sources[0x2c]	3077	1			T2	1		T5	40		T6	1
valid_sources[0x2d]	2203	1			T7	4		T8	1		T14	1
valid_sources[0x2e]	2276	1			T3	1		T7	2		T8	1
valid_sources[0x2f]	2061	1			T6	1		T7	1		T78	3
valid_sources[0x30]	2187	1			T6	3		T41	2		T43	1
valid_sources[0x31]	5519	1			T8	1		T14	3		T41	4
valid_sources[0x32]	2166	1			T2	2		T44	5		T57	1
valid_sources[0x33]	3305	1			T1	5		T6	2		T8	1
valid_sources[0x34]	1917	1			T2	4		T6	2		T14	4
valid_sources[0x35]	4422	1			T2	4		T6	2		T14	4
valid_sources[0x36]	2089	1			T2	2		T3	1		T6	3
valid_sources[0x37]	2083	1			T2	3		T6	1		T7	1
valid_sources[0x38]	1972	1			T3	1		T6	1		T8	2
valid_sources[0x39]	2273	1			T3	1		T6	1		T78	7
valid_sources[0x3a]	2139	1			T2	2		T8	1		T78	13
valid_sources[0x3b]	2108	1			T7	1		T8	1		T10	4
valid_sources[0x3c]	2012	1			T2	1		T6	1		T7	1
valid_sources[0x3d]	2193	1			T1	3		T2	3		T6	1
valid_sources[0x3e]	2320	1			T2	1		T3	1		T6	1
valid_sources[0x3f]	2107	1			T6	2		T10	2		T14	1
valid_sources[0x40]	2817	1			T3	2		T6	1		T7	2
valid_sources[0x41]	2067	1			T2	2		T6	1		T41	1
valid_sources[0x42]	2075	1			T2	3		T6	1		T10	1
valid_sources[0x43]	1931	1			T2	7		T8	1		T41	2
valid_sources[0x44]	4109	1			T2	1		T6	1		T7	1
valid_sources[0x45]	2191	1			T6	1		T14	2		T41	4
valid_sources[0x46]	2007	1			T2	1		T6	1		T8	1
valid_sources[0x47]	1859	1			T3	1		T7	1		T8	1
valid_sources[0x48]	2807	1			T6	1		T7	1		T8	3
valid_sources[0x49]	3378	1			T6	1		T44	1		T47	3
valid_sources[0x4a]	3438	1			T2	6		T6	1		T7	1
valid_sources[0x4b]	2481	1			T2	1		T3	3		T7	1
valid_sources[0x4c]	2590	1			T7	1		T14	2		T41	1
valid_sources[0x4d]	4953	1			T2	1		T6	2		T14	2
valid_sources[0x4e]	3307	1			T7	1		T11	1		T46	3
valid_sources[0x4f]	2038	1			T3	1		T8	1		T41	1
valid_sources[0x50]	3015	1			T6	1		T8	1		T43	1
valid_sources[0x51]	2023	1			T6	3		T10	1		T41	3
valid_sources[0x52]	2668	1			T6	1		T7	4		T8	1
valid_sources[0x53]	2428	1			T3	1		T6	2		T7	1
valid_sources[0x54]	1836	1			T6	1		T8	1		T41	3
valid_sources[0x55]	1925	1			T6	1		T8	1		T41	4
valid_sources[0x56]	2234	1			T6	1		T14	1		T41	4
valid_sources[0x57]	2128	1			T6	1		T7	2		T45	2
valid_sources[0x58]	2090	1			T1	2		T2	1		T6	1
valid_sources[0x59]	6576	1			T2	2		T3	1		T6	1
valid_sources[0x5a]	1971	1			T1	8		T3	2		T6	1
valid_sources[0x5b]	2040	1			T1	5		T14	2		T41	3
valid_sources[0x5c]	2228	1			T2	1		T6	1		T7	1
valid_sources[0x5d]	2074	1			T2	3		T6	2		T14	1
valid_sources[0x5e]	1889	1			T2	1		T7	1		T8	1
valid_sources[0x5f]	2046	1			T6	1		T8	1		T10	1
valid_sources[0x60]	1764	1			T2	1		T6	1		T9	4
valid_sources[0x61]	2206	1			T1	13		T2	4		T3	1
valid_sources[0x62]	1964	1			T2	1		T7	1		T8	1
valid_sources[0x63]	1987	1			T1	4		T8	1		T10	3
valid_sources[0x64]	1929	1			T2	2		T14	1		T57	1
valid_sources[0x65]	2063	1			T6	1		T14	5		T41	1
valid_sources[0x66]	2015	1			T2	1		T3	1		T6	1
valid_sources[0x67]	3429	1			T2	1		T3	2		T6	1
valid_sources[0x68]	2019	1			T2	8		T8	1		T14	2
valid_sources[0x69]	2088	1			T2	4		T6	2		T8	1
valid_sources[0x6a]	1865	1			T3	1		T6	2		T8	1
valid_sources[0x6b]	2015	1			T1	3		T3	1		T6	1
valid_sources[0x6c]	2051	1			T2	2		T43	2		T57	1
valid_sources[0x6d]	1910	1			T14	1		T41	1		T57	1
valid_sources[0x6e]	1963	1			T2	2		T6	2		T14	2
valid_sources[0x6f]	2052	1			T6	3		T9	1		T14	2
valid_sources[0x70]	2806	1			T9	2		T78	2		T15	951
valid_sources[0x71]	3887	1			T2	2		T6	1		T14	2
valid_sources[0x72]	1898	1			T6	1		T14	2		T44	5
valid_sources[0x73]	1896	1			T8	1		T14	1		T41	1
valid_sources[0x74]	12774	1			T1	5		T2	4		T3	1
valid_sources[0x75]	1939	1			T6	1		T14	1		T41	2
valid_sources[0x76]	11970	1			T6	1		T9	3		T10	1
valid_sources[0x77]	1993	1			T3	2		T9	2		T10	2
valid_sources[0x78]	1934	1			T2	1		T6	1		T78	1
valid_sources[0x79]	1991	1			T6	4		T14	2		T41	2
valid_sources[0x7a]	2071	1			T2	2		T41	2		T43	1
valid_sources[0x7b]	1972	1			T2	4		T6	1		T8	1
valid_sources[0x7c]	2156	1			T3	1		T7	1		T14	1
valid_sources[0x7d]	1921	1			T1	3		T2	1		T14	3
valid_sources[0x7e]	1896	1			T6	1		T7	2		T8	1
valid_sources[0x7f]	1995	1			T6	2		T7	1		T41	2
valid_sources[0x80]	2181	1			T2	5		T6	1		T7	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

144210

1

T1

19

T2

15

T3

22

values[0x0]

all_enables

biggest_size

43340

1

T1

4

T2

6

T3

3

values[0x1]

all_enables

biggest_size

24418

1

T1

3

T2

4

T3

3