SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34355 | 1 | T3 | 1 | T15 | 373 | T47 | 396 | ||||
others[1] | 34250 | 1 | T15 | 407 | T47 | 413 | T30 | 289 | ||||
others[2] | 34241 | 1 | T15 | 387 | T47 | 416 | T30 | 286 | ||||
others[3] | 57177 | 1 | T15 | 678 | T47 | 642 | T30 | 518 | ||||
false | 13991 | 1 | T1 | 5 | T3 | 2 | T15 | 50 | ||||
true | 22071 | 1 | T1 | 4 | T2 | 1 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34241 | 1 | T15 | 400 | T47 | 390 | T30 | 288 | ||||
others[1] | 34334 | 1 | T15 | 414 | T47 | 406 | T30 | 303 | ||||
others[2] | 34513 | 1 | T15 | 398 | T47 | 422 | T30 | 331 | ||||
others[3] | 57064 | 1 | T15 | 636 | T47 | 669 | T30 | 483 | ||||
false | 9522 | 1 | T1 | 3 | T3 | 4 | T15 | 50 | ||||
true | 17683 | 1 | T1 | 5 | T2 | 1 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 488 | 1 | T2 | 5 | T4 | 8 | T6 | 7 | ||||
others[1] | 536 | 1 | T2 | 6 | T4 | 6 | T6 | 3 | ||||
others[2] | 505 | 1 | T2 | 5 | T4 | 4 | T6 | 5 | ||||
others[3] | 878 | 1 | T2 | 11 | T3 | 2 | T4 | 6 | ||||
false | 9567 | 1 | T1 | 6 | T2 | 4 | T3 | 5 | ||||
true | 2630 | 1 | T1 | 4 | T2 | 3 | T3 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |