Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T14,T15
0	1	Covered	T1,T2,T3
1	0	Covered	T46,T47,T50

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	16491367	4775	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	16491367	194306	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	16491367	6694323	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	16491367	194288	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	16491367	4775	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	16491367	194306	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	16491367	6694323	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	16491367	194288	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	4775	0	0
T5	1011	1	0	0
T6	4263	0	0	0
T7	8609	0	0	0
T8	7707	0	0	0
T9	3229	0	0	0
T10	3216	0	0	0
T14	10390	2	0	0
T15	0	21	0	0
T30	0	21	0	0
T41	3211	0	0	0
T42	7777	0	0	0
T46	0	7	0	0
T47	0	19	0	0
T50	0	2	0	0
T51	0	2	0	0
T76	0	1	0	0
T77	0	7	0	0
T78	4488	0	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	194306	0	0
T5	1011	12	0	0
T6	4263	0	0	0
T7	8609	0	0	0
T8	7707	0	0	0
T9	3229	0	0	0
T10	3216	0	0	0
T14	10390	24	0	0
T15	0	454	0	0
T30	0	577	0	0
T41	3211	0	0	0
T42	7777	0	0	0
T46	0	377	0	0
T47	0	524	0	0
T50	0	156	0	0
T51	0	325	0	0
T76	0	12	0	0
T77	0	208	0	0
T78	4488	0	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	6694323	0	0
T5	1011	727	0	0
T6	4263	0	0	0
T7	8609	0	0	0
T8	7707	0	0	0
T9	3229	0	0	0
T10	3216	0	0	0
T14	10390	5641	0	0
T15	0	12602	0	0
T16	0	105	0	0
T28	0	1218	0	0
T41	3211	0	0	0
T42	7777	0	0	0
T46	0	4930	0	0
T47	0	8101	0	0
T57	0	3058	0	0
T61	0	11012	0	0
T78	4488	0	0	0
T79	0	2330	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	194288	0	0
T5	1011	12	0	0
T6	4263	0	0	0
T7	8609	0	0	0
T8	7707	0	0	0
T9	3229	0	0	0
T10	3216	0	0	0
T14	10390	24	0	0
T15	0	454	0	0
T30	0	577	0	0
T41	3211	0	0	0
T42	7777	0	0	0
T46	0	377	0	0
T47	0	526	0	0
T50	0	156	0	0
T51	0	325	0	0
T76	0	12	0	0
T77	0	208	0	0
T78	4488	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	4775	0	0
T5	1011	1	0	0
T6	4263	0	0	0
T7	8609	0	0	0
T8	7707	0	0	0
T9	3229	0	0	0
T10	3216	0	0	0
T14	10390	2	0	0
T15	0	21	0	0
T30	0	21	0	0
T41	3211	0	0	0
T42	7777	0	0	0
T46	0	7	0	0
T47	0	19	0	0
T50	0	2	0	0
T51	0	2	0	0
T76	0	1	0	0
T77	0	7	0	0
T78	4488	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	194306	0	0
T5	1011	12	0	0
T6	4263	0	0	0
T7	8609	0	0	0
T8	7707	0	0	0
T9	3229	0	0	0
T10	3216	0	0	0
T14	10390	24	0	0
T15	0	454	0	0
T30	0	577	0	0
T41	3211	0	0	0
T42	7777	0	0	0
T46	0	377	0	0
T47	0	524	0	0
T50	0	156	0	0
T51	0	325	0	0
T76	0	12	0	0
T77	0	208	0	0
T78	4488	0	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	6694323	0	0
T5	1011	727	0	0
T6	4263	0	0	0
T7	8609	0	0	0
T8	7707	0	0	0
T9	3229	0	0	0
T10	3216	0	0	0
T14	10390	5641	0	0
T15	0	12602	0	0
T16	0	105	0	0
T28	0	1218	0	0
T41	3211	0	0	0
T42	7777	0	0	0
T46	0	4930	0	0
T47	0	8101	0	0
T57	0	3058	0	0
T61	0	11012	0	0
T78	4488	0	0	0
T79	0	2330	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	194288	0	0
T5	1011	12	0	0
T6	4263	0	0	0
T7	8609	0	0	0
T8	7707	0	0	0
T9	3229	0	0	0
T10	3216	0	0	0
T14	10390	24	0	0
T15	0	454	0	0
T30	0	577	0	0
T41	3211	0	0	0
T42	7777	0	0	0
T46	0	377	0	0
T47	0	526	0	0
T50	0	156	0	0
T51	0	325	0	0
T76	0	12	0	0
T77	0	208	0	0
T78	4488	0	0	0