Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	17012192	13569	0	0
intr_enable_rd_A	17012192	13599	0	0
reset_en_rd_A	17012192	874	0	0
reset_en_regwen_rd_A	17012192	713	0	0
wake_info_capture_dis_rd_A	17012192	682	0	0
wakeup_en_rd_A	17012192	1316	0	0
wakeup_en_regwen_rd_A	17012192	672	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17012192	13569	0	0
T25	179166	2	0	0
T26	164416	14	0	0
T27	0	16	0	0
T53	0	224	0	0
T54	0	778	0	0
T55	0	7	0	0
T60	0	348	0	0
T69	0	197	0	0
T72	0	18	0	0
T73	0	44	0	0
T114	1489	0	0	0
T115	1691	0	0	0
T116	2202	0	0	0
T117	55741	0	0	0
T118	1769	0	0	0
T119	4675	0	0	0
T120	1662	0	0	0
T121	7435	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17012192	13599	0	0
T3	4800	2	0	0
T4	3209	0	0	0
T5	1011	0	0	0
T6	4263	0	0	0
T7	8609	0	0	0
T8	7707	0	0	0
T9	3229	0	0	0
T10	3216	0	0	0
T14	10390	0	0	0
T15	0	187	0	0
T16	0	3	0	0
T46	0	25	0	0
T48	0	301	0	0
T57	0	57	0	0
T78	4488	0	0	0
T80	0	12	0	0
T122	0	24	0	0
T123	0	5	0	0
T124	0	2	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17012192	874	0	0
T65	6616	12	0	0
T66	1169	0	0	0
T67	787	0	0	0
T68	1940	0	0	0
T70	3633	77	0	0
T75	4256	0	0	0
T81	2331	0	0	0
T84	2048	18	0	0
T85	1294	0	0	0
T95	0	2	0	0
T98	0	57	0	0
T113	0	12	0	0
T125	2919	6	0	0
T126	0	21	0	0
T127	0	6	0	0
T128	0	17	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17012192	713	0	0
T65	6616	6	0	0
T66	1169	0	0	0
T67	787	0	0	0
T68	1940	0	0	0
T70	3633	15	0	0
T75	4256	0	0	0
T81	2331	0	0	0
T84	2048	19	0	0
T85	1294	0	0	0
T95	0	3	0	0
T98	0	60	0	0
T113	0	6	0	0
T125	2919	11	0	0
T126	0	10	0	0
T127	0	3	0	0
T128	0	6	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17012192	682	0	0
T65	6616	10	0	0
T66	1169	0	0	0
T67	787	0	0	0
T68	1940	0	0	0
T70	3633	40	0	0
T75	4256	0	0	0
T81	2331	0	0	0
T84	2048	14	0	0
T85	1294	0	0	0
T95	0	1	0	0
T98	0	58	0	0
T113	0	10	0	0
T125	2919	16	0	0
T126	0	12	0	0
T127	0	17	0	0
T129	0	22	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17012192	1316	0	0
T65	6616	13	0	0
T66	1169	0	0	0
T67	787	0	0	0
T68	1940	0	0	0
T70	3633	62	0	0
T75	4256	0	0	0
T81	2331	0	0	0
T84	2048	11	0	0
T85	1294	0	0	0
T95	0	3	0	0
T98	0	44	0	0
T113	0	32	0	0
T125	2919	6	0	0
T126	0	23	0	0
T127	0	2	0	0
T128	0	10	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17012192	672	0	0
T65	6616	8	0	0
T66	1169	0	0	0
T67	787	0	0	0
T68	1940	0	0	0
T70	3633	43	0	0
T75	4256	0	0	0
T81	2331	0	0	0
T84	2048	40	0	0
T85	1294	0	0	0
T98	0	59	0	0
T100	0	1	0	0
T113	0	10	0	0
T125	2919	20	0	0
T126	0	1	0	0
T127	0	19	0	0
T128	0	18	0	0